Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:
 "Mostly PMU fixes and a reworking of the pseudo-NMI disabling on broken
  MediaTek firmware:

   - Move the MediaTek GIC quirk handling from irqchip to core. Before
     the merging window commit 44bd78dd2b88 ("irqchip/gic-v3: Disable
     pseudo NMIs on MediaTek devices w/ firmware issues") temporarily
     addressed this issue. Fixed now at a deeper level in the arch code

   - Reject events meant for other PMUs in the CoreSight PMU driver,
     otherwise some of the core PMU events would disappear

   - Fix the Armv8 PMUv3 driver driver to not truncate 64-bit registers,
     causing some events to be invisible

   - Remove duplicate declaration of __arm64_sys##name following the
     patch to avoid prototype warning for syscalls

   - Typos in the elf_hwcap documentation"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/syscall: Remove duplicate declaration
  Revert "arm64: smp: avoid NMI IPIs with broken MediaTek FW"
  arm64: Move MediaTek GIC quirk handling from irqchip to core
  arm64/arm: arm_pmuv3: perf: Don't truncate 64-bit registers
  perf: arm_cspmu: Reject events meant for other PMUs
  Documentation/arm64: Fix typos in elf_hwcaps

diff --combined arch/arm64/kernel/smp.c
index be95b523c101811569c4ef73da8f39e184ecbc7b,03204e841172057f5093ccee5503e09fc1e872a1..defbab84e9e5c7968cabe030e28ef261c9507fb7
--- 1/arch/arm64/kernel/smp.c
--- 2/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@@ -223,7 -223,7 +223,7 @@@ asmlinkage notrace void secondary_start
        if (system_uses_irq_prio_masking())
                init_gic_priority_masking();
  
 -      rcu_cpu_starting(cpu);
 +      rcutree_report_cpu_starting(cpu);
        trace_hardirqs_off();
  
        /*
@@@ -409,7 -409,7 +409,7 @@@ void __noreturn cpu_die_early(void
  
        /* Mark this CPU absent */
        set_cpu_present(cpu, 0);
 -      rcu_report_dead(cpu);
 +      rcutree_report_cpu_dead();
  
        if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
                update_cpu_boot_status(CPU_KILL_ME);
@@@ -965,10 -965,7 +965,7 @@@ static void smp_cross_call(const struc
  
  static bool ipi_should_be_nmi(enum ipi_msg_type ipi)
  {
-       DECLARE_STATIC_KEY_FALSE(supports_pseudo_nmis);
- 
-       if (!system_uses_irq_prio_masking() ||
-           !static_branch_likely(&supports_pseudo_nmis))
+       if (!system_uses_irq_prio_masking())
                return false;
  
        switch (ipi) {

diff --combined drivers/irqchip/irq-gic-v3.c
index 68d11ccee44120829051b803fe593827440ac0bf,dd41635547384e7de47cd21dca18fba94158c3fb..98b0329b7154a4377afaa6b3cf5622e304dd2110
--- 1/drivers/irqchip/irq-gic-v3.c
--- 2/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@@ -39,8 -39,7 +39,7 @@@
  
  #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996   (1ULL << 0)
  #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1)
- #define FLAGS_WORKAROUND_MTK_GICR_SAVE                (1ULL << 2)
- #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001  (1ULL << 3)
+ #define FLAGS_WORKAROUND_ASR_ERRATUM_8601001  (1ULL << 2)
  
  #define GIC_IRQ_TYPE_PARTITION        (GIC_IRQ_TYPE_LPI + 1)
  
@@@ -106,7 -105,7 +105,7 @@@ static DEFINE_STATIC_KEY_TRUE(supports_
   * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
   *   interrupt.
   */
- DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
+ static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
  
  DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
  EXPORT_SYMBOL(gic_nonsecure_priorities);
@@@ -1779,15 -1778,6 +1778,6 @@@ static bool gic_enable_quirk_msm8996(vo
        return true;
  }
  
- static bool gic_enable_quirk_mtk_gicr(void *data)
- {
-       struct gic_chip_data *d = data;
- 
-       d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE;
- 
-       return true;
- }
- 
  static bool gic_enable_quirk_cavium_38539(void *data)
  {
        struct gic_chip_data *d = data;
@@@ -1869,14 -1859,6 +1859,14 @@@ static bool gic_enable_quirk_arm64_2941
        return true;
  }
  
 +static bool rd_set_non_coherent(void *data)
 +{
 +      struct gic_chip_data *d = data;
 +
 +      d->rdists.flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
 +      return true;
 +}
 +
  static const struct gic_quirk gic_quirks[] = {
        {
                .desc   = "GICv3: Qualcomm MSM8996 broken firmware",
@@@ -1888,11 -1870,6 +1878,6 @@@
                .compatible = "asr,asr8601-gic-v3",
                .init   = gic_enable_quirk_asr8601,
        },
-       {
-               .desc   = "GICv3: Mediatek Chromebook GICR save problem",
-               .property = "mediatek,broken-save-restore-fw",
-               .init   = gic_enable_quirk_mtk_gicr,
-       },
        {
                .desc   = "GICv3: HIP06 erratum 161010803",
                .iidr   = 0x0204043b,
@@@ -1943,11 -1920,6 +1928,11 @@@
                .mask   = 0xff0f0fff,
                .init   = gic_enable_quirk_arm64_2941627,
        },
 +      {
 +              .desc   = "GICv3: non-coherent attribute",
 +              .property = "dma-noncoherent",
 +              .init   = rd_set_non_coherent,
 +      },
        {
        }
  };
@@@ -1959,11 -1931,6 +1944,6 @@@ static void gic_enable_nmi_support(void
        if (!gic_prio_masking_enabled())
                return;
  
-       if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) {
-               pr_warn("Skipping NMI enable due to firmware issues\n");
-               return;
-       }
- 
        rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR,
                                 sizeof(*rdist_nmi_refs), GFP_KERNEL);
        if (!rdist_nmi_refs)

diff --combined drivers/perf/arm_cspmu/arm_cspmu.c
index 42b72042f6b3759d2d1cbfd57d1268d070b584ae,9f478f2c85543eb7ca2f68e448e401f82a73adcf..2cc35dded0079f9f3a59289e476fd1f579114556
--- 1/drivers/perf/arm_cspmu/arm_cspmu.c
--- 2/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@@ -676,6 -676,9 +676,9 @@@ static int arm_cspmu_event_init(struct 
  
        cspmu = to_arm_cspmu(event->pmu);
  
+       if (event->attr.type != event->pmu->type)
+               return -ENOENT;
+ 
        /*
         * Following other "uncore" PMUs, we do not support sampling mode or
         * attach to a task (per-process mode).
@@@ -1105,7 -1108,7 +1108,7 @@@ static int arm_cspmu_request_irq(struc
  
  static inline int arm_cspmu_find_cpu_container(int cpu, u32 container_uid)
  {
 -      u32 acpi_uid;
 +      u64 acpi_uid;
        struct device *cpu_dev;
        struct acpi_device *acpi_dev;
  
@@@ -1115,8 -1118,10 +1118,8 @@@
  
        acpi_dev = ACPI_COMPANION(cpu_dev);
        while (acpi_dev) {
 -              if (!strcmp(acpi_device_hid(acpi_dev),
 -                          ACPI_PROCESSOR_CONTAINER_HID) &&
 -                  !kstrtouint(acpi_device_uid(acpi_dev), 0, &acpi_uid) &&
 -                  acpi_uid == container_uid)
 +              if (acpi_dev_hid_uid_match(acpi_dev, ACPI_PROCESSOR_CONTAINER_HID, NULL) &&
 +                  !acpi_dev_uid_to_integer(acpi_dev, &acpi_uid) && acpi_uid == container_uid)
                        return 0;
  
                acpi_dev = acpi_dev_parent(acpi_dev);

diff --combined drivers/perf/arm_pmuv3.c
index 18b91b56af1d467ceb155cd8ce89739a2df1c240,ee98e213a3de312d6d7aa65600fd7fe34daf456e..6ca7be05229c107e87ad2301cd8107b55d2a0e01
--- 1/drivers/perf/arm_pmuv3.c
--- 2/drivers/perf/arm_pmuv3.c
+++ b/drivers/perf/arm_pmuv3.c
@@@ -428,12 -428,12 +428,12 @@@ static inline bool armv8pmu_event_is_ch
  #define       ARMV8_IDX_TO_COUNTER(x) \
        (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
  
- static inline u32 armv8pmu_pmcr_read(void)
+ static inline u64 armv8pmu_pmcr_read(void)
  {
        return read_pmcr();
  }
  
- static inline void armv8pmu_pmcr_write(u32 val)
+ static inline void armv8pmu_pmcr_write(u64 val)
  {
        val &= ARMV8_PMU_PMCR_MASK;
        isb();
@@@ -957,7 -957,7 +957,7 @@@ static int armv8pmu_set_event_filter(st
  static void armv8pmu_reset(void *info)
  {
        struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
-       u32 pmcr;
+       u64 pmcr;
  
        /* The counter and interrupt enable registers are unknown at reset. */
        armv8pmu_disable_counter(U32_MAX);
@@@ -1175,6 -1175,7 +1175,6 @@@ static struct ctl_table armv8_pmu_sysct
                .extra1         = SYSCTL_ZERO,
                .extra2         = SYSCTL_ONE,
        },
 -      { }
  };
  
  static void armv8_pmu_register_sysctl_table(void)