Merge tag 'gvt-fixes-2022-01-13' of https://github.com/intel/gvt-linux into drm-intel...

gvt-fixes-2022-01-13

- Make DRM_I915_GVT depend on X86 (Siva Mullati)
- Clean kernel doc in gtt.c (Randy Dunlap)

Signed-off-by: Tvrtko Ursulin <[email protected]>
From: Zhi Wang <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

diff --combined drivers/gpu/drm/i915/Kconfig
index a4c94dc2e2164363175990eab9a7a30f3ab842e5,0bddb75fa7e012b406f74dfa3e38e2719dd2db7d..cfd932514da274fe389931eba91ce846f021bab4
--- 1/drivers/gpu/drm/i915/Kconfig
--- 2/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@@ -21,7 -21,7 +21,7 @@@ config DRM_I91
        select ACPI_VIDEO if ACPI
        select ACPI_BUTTON if ACPI
        select SYNC_FILE
 -      select IOSF_MBI
 +      select IOSF_MBI if X86
        select CRC32
        select SND_HDA_I915 if SND_HDA_CORE
        select CEC_CORE if CEC_NOTIFIER
@@@ -101,6 -101,7 +101,7 @@@ config DRM_I915_USERPT
  config DRM_I915_GVT
        bool "Enable Intel GVT-g graphics virtualization host support"
        depends on DRM_I915
+       depends on X86
        depends on 64BIT
        default n
        help

diff --combined drivers/gpu/drm/i915/gvt/gtt.c
index 99d1781fa5f0c1dc054032793d62b89f09dcaacc,93ce786905dd484022af511508f90c3cc5b74b09..af79b39048f7ee2ad5418704bf86ba4e85db2e0b
--- 1/drivers/gpu/drm/i915/gvt/gtt.c
--- 2/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@@ -446,17 -446,17 +446,17 @@@ static bool gen8_gtt_test_present(struc
                        || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
                return (e->val64 != 0);
        else
 -              return (e->val64 & _PAGE_PRESENT);
 +              return (e->val64 & GEN8_PAGE_PRESENT);
  }
  
  static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
  {
 -      e->val64 &= ~_PAGE_PRESENT;
 +      e->val64 &= ~GEN8_PAGE_PRESENT;
  }
  
  static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
  {
 -      e->val64 |= _PAGE_PRESENT;
 +      e->val64 |= GEN8_PAGE_PRESENT;
  }
  
  static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
@@@ -1148,7 -1148,7 +1148,7 @@@ static inline void ppgtt_generate_shado
        ops->set_pfn(se, s->shadow_page.mfn);
  }
  
- /**
+ /*
   * Check if can do 2M page
   * @vgpu: target vgpu
   * @entry: target pfn's gtt entry
@@@ -2193,7 -2193,7 +2193,7 @@@ static int emulate_ggtt_mmio_read(struc
  }
  
  /**
-  * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
+  * intel_vgpu_emulate_ggtt_mmio_read - emulate GTT MMIO register read
   * @vgpu: a vGPU
   * @off: register offset
   * @p_data: data will be returned to guest
@@@ -2439,7 -2439,7 +2439,7 @@@ static int alloc_scratch_pages(struct i
                /* The entry parameters like present/writeable/cache type
                 * set to the same as i915's scratch page tree.
                 */
 -              se.val64 |= _PAGE_PRESENT | _PAGE_RW;
 +              se.val64 |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
                if (type == GTT_TYPE_PPGTT_PDE_PT)
                        se.val64 |= PPAT_CACHED;
  
@@@ -2896,7 -2896,7 +2896,7 @@@ void intel_gvt_restore_ggtt(struct inte
                offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
                for (idx = 0; idx < num_low; idx++) {
                        pte = mm->ggtt_mm.host_ggtt_aperture[idx];
 -                      if (pte & _PAGE_PRESENT)
 +                      if (pte & GEN8_PAGE_PRESENT)
                                write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
                }
  
@@@ -2904,7 -2904,7 +2904,7 @@@
                offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
                for (idx = 0; idx < num_hi; idx++) {
                        pte = mm->ggtt_mm.host_ggtt_hidden[idx];
 -                      if (pte & _PAGE_PRESENT)
 +                      if (pte & GEN8_PAGE_PRESENT)
                                write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
                }
        }