clk: stm32mp25: add security clocks

Add ck_icn_p_iwdg1, ck_icn_p_pka, ck_icn_p_rng, ck_icn_p_saes,
ck_icn_p_serc clocks.
They could be configured for non secured world.

Signed-off-by: Gabriel Fernandez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c
index 65a2d6bac271eb348fd5cda82831538ba48c9948..52f0e8a1292626ac3e355d107b5b7fe9925e9883 100644 (file)
--- a/drivers/clk/stm32/clk-stm32mp25.c
+++ b/drivers/clk/stm32/clk-stm32mp25.c
@@ -888,6 +888,11 @@ static struct clk_stm32_gate ck_icn_p_is2m = {
 };
 
 /* IWDG */
+static struct clk_stm32_gate ck_icn_p_iwdg1 = {
+       .gate_id = GATE_IWDG1,
+       .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg1", ICN_APB3, &clk_stm32_gate_ops, 0),
+};
+
 static struct clk_stm32_gate ck_icn_p_iwdg2 = {
        .gate_id = GATE_IWDG2,
        .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_iwdg2", ICN_APB3, &clk_stm32_gate_ops, 0),
@@ -1008,6 +1013,24 @@ static struct clk_stm32_gate ck_icn_p_pcie = {
        .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pcie", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
 };
 
+/* PKA */
+static struct clk_stm32_gate ck_icn_p_pka = {
+       .gate_id = GATE_PKA,
+       .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_pka", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
+};
+
+/* RNG */
+static struct clk_stm32_gate ck_icn_p_rng = {
+       .gate_id = GATE_RNG,
+       .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_rng", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
+};
+
+/* SAES */
+static struct clk_stm32_gate ck_icn_p_saes = {
+       .gate_id = GATE_SAES,
+       .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_saes", ICN_LS_MCU, &clk_stm32_gate_ops, 0),
+};
+
 /* SAI */
 static struct clk_stm32_gate ck_icn_p_sai1 = {
        .gate_id = GATE_SAI1,
@@ -1084,6 +1107,12 @@ static struct clk_stm32_gate ck_ker_sdmmc3 = {
        .hw.init = CLK_HW_INIT_INDEX("ck_ker_sdmmc3", FLEXGEN_53, &clk_stm32_gate_ops, 0),
 };
 
+/* SERC */
+static struct clk_stm32_gate ck_icn_p_serc = {
+       .gate_id = GATE_SERC,
+       .hw.init = CLK_HW_INIT_INDEX("ck_icn_p_serc", ICN_APB3, &clk_stm32_gate_ops, 0),
+};
+
 /* SPDIF */
 static struct clk_stm32_gate ck_icn_p_spdifrx = {
        .gate_id = GATE_SPDIFRX,
@@ -1607,8 +1636,11 @@ static const struct clock_config stm32mp25_clock_cfg[] = {
        STM32_GATE_CFG(CK_BUS_MDF1,             ck_icn_p_mdf1,          SEC_RIFSC(54)),
        STM32_GATE_CFG(CK_BUS_OSPIIOM,          ck_icn_p_ospiiom,       SEC_RIFSC(111)),
        STM32_GATE_CFG(CK_BUS_HASH,             ck_icn_p_hash,          SEC_RIFSC(95)),
+       STM32_GATE_CFG(CK_BUS_RNG,              ck_icn_p_rng,           SEC_RIFSC(92)),
        STM32_GATE_CFG(CK_BUS_CRYP1,            ck_icn_p_cryp1,         SEC_RIFSC(96)),
        STM32_GATE_CFG(CK_BUS_CRYP2,            ck_icn_p_cryp2,         SEC_RIFSC(97)),
+       STM32_GATE_CFG(CK_BUS_SAES,             ck_icn_p_saes,          SEC_RIFSC(94)),
+       STM32_GATE_CFG(CK_BUS_PKA,              ck_icn_p_pka,           SEC_RIFSC(93)),
        STM32_GATE_CFG(CK_BUS_ADF1,             ck_icn_p_adf1,          SEC_RIFSC(55)),
        STM32_GATE_CFG(CK_BUS_SPI8,             ck_icn_p_spi8,          SEC_RIFSC(29)),
        STM32_GATE_CFG(CK_BUS_LPUART1,          ck_icn_p_lpuart1,       SEC_RIFSC(40)),
@@ -1676,11 +1708,13 @@ static const struct clock_config stm32mp25_clock_cfg[] = {
        STM32_GATE_CFG(CK_BUS_SPI5,             ck_icn_p_spi5,          SEC_RIFSC(26)),
        STM32_GATE_CFG(CK_BUS_SPI6,             ck_icn_p_spi6,          SEC_RIFSC(27)),
        STM32_GATE_CFG(CK_BUS_SPI7,             ck_icn_p_spi7,          SEC_RIFSC(28)),
+       STM32_GATE_CFG(CK_BUS_IWDG1,            ck_icn_p_iwdg1,         SEC_RIFSC(98)),
        STM32_GATE_CFG(CK_BUS_IWDG2,            ck_icn_p_iwdg2,         SEC_RIFSC(99)),
        STM32_GATE_CFG(CK_BUS_IWDG3,            ck_icn_p_iwdg3,         SEC_RIFSC(100)),
        STM32_GATE_CFG(CK_BUS_IWDG4,            ck_icn_p_iwdg4,         SEC_RIFSC(101)),
        STM32_GATE_CFG(CK_BUS_WWDG1,            ck_icn_p_wwdg1,         SEC_RIFSC(103)),
        STM32_GATE_CFG(CK_BUS_VREF,             ck_icn_p_vref,          SEC_RIFSC(106)),
+       STM32_GATE_CFG(CK_BUS_SERC,             ck_icn_p_serc,          SEC_RIFSC(110)),
        STM32_GATE_CFG(CK_BUS_HDP,              ck_icn_p_hdp,           SEC_RIFSC(57)),
        STM32_GATE_CFG(CK_BUS_IS2M,             ck_icn_p_is2m,          MP25_RIF_RCC_IS2M),
        STM32_GATE_CFG(CK_BUS_DSI,              ck_icn_p_dsi,           SEC_RIFSC(81)),