clk: qoriq: add LS1021A core pll mux options

This allows to clock the cores with 1 GHz, 500 MHz and 250 MHz.

Signed-off-by: Michael Krummsdorf <[email protected]>
Signed-off-by: Matthias Schiffer <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 374afcab89af5978c076826c21699ab3d58b0b14..5942e9874bc08243bc5d5c7737a8daafb0b14cdd 100644 (file)
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -244,6 +244,14 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
        },
 };
 
+static const struct clockgen_muxinfo ls1021a_cmux = {
+       {
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
+               { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
+       }
+};
+
 static const struct clockgen_muxinfo ls1028a_hwa1 = {
        {
                { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
@@ -577,7 +585,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
        {
                .compat = "fsl,ls1021a-clockgen",
                .cmux_groups = {
-                       &t1023_cmux
+                       &ls1021a_cmux
                },
                .cmux_to_group = {
                        0, -1