Merge tag 'icc-6.9-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc...

Georgi writes:

interconnect fixes for v6.9-rc

Here are fixes for two reported issues. One of them is a fix for
a driver that tries to access a non-existent resource which prints
a warning message during boot. The other one is fixing a race
condition in the core framework where one struct member has been
left unprotected by mutex.

- interconnect: qcom: x1e80100: Remove inexistent ACV_PERF BCM
- interconnect: Don't access req_list while it's being manipulated

Signed-off-by: Georgi Djakov <[email protected]>
* tag 'icc-6.9-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: Don't access req_list while it's being manipulated
  interconnect: qcom: x1e80100: Remove inexistent ACV_PERF BCM

diff --combined drivers/interconnect/core.c
index 5d1010cafed8d3a3b65349dd58a0741d445ffcd7,68edb07d4443e95b985f6a754a9efef83f06af66..7e9b996b47c833c59873520d28c723f7ca97d07a
--- 1/drivers/interconnect/core.c
--- 2/drivers/interconnect/core.c
+++ b/drivers/interconnect/core.c
@@@ -176,6 -176,8 +176,8 @@@ static struct icc_path *path_init(struc
  
        path->num_nodes = num_nodes;
  
+       mutex_lock(&icc_bw_lock);
+ 
        for (i = num_nodes - 1; i >= 0; i--) {
                node->provider->users++;
                hlist_add_head(&path->reqs[i].req_node, &node->req_list);
@@@ -186,6 -188,8 +188,8 @@@
                node = node->reverse;
        }
  
+       mutex_unlock(&icc_bw_lock);
+ 
        return path;
  }
  
@@@ -343,7 -347,7 +347,7 @@@ EXPORT_SYMBOL_GPL(icc_std_aggregate)
   * an array of icc nodes specified in the icc_onecell_data struct when
   * registering the provider.
   */
 -struct icc_node *of_icc_xlate_onecell(struct of_phandle_args *spec,
 +struct icc_node *of_icc_xlate_onecell(const struct of_phandle_args *spec,
                                      void *data)
  {
        struct icc_onecell_data *icc_data = data;
@@@ -368,7 -372,7 +372,7 @@@ EXPORT_SYMBOL_GPL(of_icc_xlate_onecell)
   * Returns a valid pointer to struct icc_node_data on success or ERR_PTR()
   * on failure.
   */
 -struct icc_node_data *of_icc_get_from_provider(struct of_phandle_args *spec)
 +struct icc_node_data *of_icc_get_from_provider(const struct of_phandle_args *spec)
  {
        struct icc_node *node = ERR_PTR(-EPROBE_DEFER);
        struct icc_node_data *data = NULL;
@@@ -792,12 -796,16 +796,16 @@@ void icc_put(struct icc_path *path
                pr_err("%s: error (%d)\n", __func__, ret);
  
        mutex_lock(&icc_lock);
+       mutex_lock(&icc_bw_lock);
+ 
        for (i = 0; i < path->num_nodes; i++) {
                node = path->reqs[i].node;
                hlist_del(&path->reqs[i].req_node);
                if (!WARN_ON(!node->provider->users))
                        node->provider->users--;
        }
+ 
+       mutex_unlock(&icc_bw_lock);
        mutex_unlock(&icc_lock);
  
        kfree_const(path->name);

diff --combined drivers/interconnect/qcom/x1e80100.c
index 99824675ee3f495cb8adeabae6c01c185c3a60c1,06f0a6d6cbbc035d49a7d66df1e7d6caede87f83..654abb9ce08eedaa06dbe12945cc42d45e0844b0
--- 1/drivers/interconnect/qcom/x1e80100.c
--- 2/drivers/interconnect/qcom/x1e80100.c
+++ b/drivers/interconnect/qcom/x1e80100.c
@@@ -116,15 -116,6 +116,6 @@@ static struct qcom_icc_node xm_sdc2 = 
        .links = { X1E80100_SLAVE_A2NOC_SNOC },
  };
  
- static struct qcom_icc_node ddr_perf_mode_master = {
-       .name = "ddr_perf_mode_master",
-       .id = X1E80100_MASTER_DDR_PERF_MODE,
-       .channels = 1,
-       .buswidth = 4,
-       .num_links = 1,
-       .links = { X1E80100_SLAVE_DDR_PERF_MODE },
- };
- 
  static struct qcom_icc_node qup0_core_master = {
        .name = "qup0_core_master",
        .id = X1E80100_MASTER_QUP_CORE_0,
@@@ -670,6 -661,150 +661,6 @@@ static struct qcom_icc_node xm_usb4_2 
        .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH },
  };
  
 -static struct qcom_icc_node qnm_mnoc_hf_disp = {
 -      .name = "qnm_mnoc_hf_disp",
 -      .id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP,
 -      .channels = 2,
 -      .buswidth = 32,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_LLCC_DISP },
 -};
 -
 -static struct qcom_icc_node qnm_pcie_disp = {
 -      .name = "qnm_pcie_disp",
 -      .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_LLCC_DISP },
 -};
 -
 -static struct qcom_icc_node llcc_mc_disp = {
 -      .name = "llcc_mc_disp",
 -      .id = X1E80100_MASTER_LLCC_DISP,
 -      .channels = 8,
 -      .buswidth = 4,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_EBI1_DISP },
 -};
 -
 -static struct qcom_icc_node qnm_mdp_disp = {
 -      .name = "qnm_mdp_disp",
 -      .id = X1E80100_MASTER_MDP_DISP,
 -      .channels = 2,
 -      .buswidth = 32,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP },
 -};
 -
 -static struct qcom_icc_node qnm_pcie_pcie = {
 -      .name = "qnm_pcie_pcie",
 -      .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_LLCC_PCIE },
 -};
 -
 -static struct qcom_icc_node llcc_mc_pcie = {
 -      .name = "llcc_mc_pcie",
 -      .id = X1E80100_MASTER_LLCC_PCIE,
 -      .channels = 8,
 -      .buswidth = 4,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_EBI1_PCIE },
 -};
 -
 -static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = {
 -      .name = "qnm_pcie_north_gem_noc_pcie",
 -      .id = X1E80100_MASTER_PCIE_NORTH_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
 -};
 -
 -static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = {
 -      .name = "qnm_pcie_south_gem_noc_pcie",
 -      .id = X1E80100_MASTER_PCIE_SOUTH_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_3_pcie = {
 -      .name = "xm_pcie_3_pcie",
 -      .id = X1E80100_MASTER_PCIE_3_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_4_pcie = {
 -      .name = "xm_pcie_4_pcie",
 -      .id = X1E80100_MASTER_PCIE_4_PCIE,
 -      .channels = 1,
 -      .buswidth = 8,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_5_pcie = {
 -      .name = "xm_pcie_5_pcie",
 -      .id = X1E80100_MASTER_PCIE_5_PCIE,
 -      .channels = 1,
 -      .buswidth = 8,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_0_pcie = {
 -      .name = "xm_pcie_0_pcie",
 -      .id = X1E80100_MASTER_PCIE_0_PCIE,
 -      .channels = 1,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_1_pcie = {
 -      .name = "xm_pcie_1_pcie",
 -      .id = X1E80100_MASTER_PCIE_1_PCIE,
 -      .channels = 1,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_2_pcie = {
 -      .name = "xm_pcie_2_pcie",
 -      .id = X1E80100_MASTER_PCIE_2_PCIE,
 -      .channels = 1,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_6a_pcie = {
 -      .name = "xm_pcie_6a_pcie",
 -      .id = X1E80100_MASTER_PCIE_6A_PCIE,
 -      .channels = 1,
 -      .buswidth = 32,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
 -};
 -
 -static struct qcom_icc_node xm_pcie_6b_pcie = {
 -      .name = "xm_pcie_6b_pcie",
 -      .id = X1E80100_MASTER_PCIE_6B_PCIE,
 -      .channels = 1,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE },
 -};
 -
  static struct qcom_icc_node qns_a1noc_snoc = {
        .name = "qns_a1noc_snoc",
        .id = X1E80100_SLAVE_A1NOC_SNOC,
@@@ -688,14 -823,6 +679,6 @@@ static struct qcom_icc_node qns_a2noc_s
        .links = { X1E80100_MASTER_A2NOC_SNOC },
  };
  
- static struct qcom_icc_node ddr_perf_mode_slave = {
-       .name = "ddr_perf_mode_slave",
-       .id = X1E80100_SLAVE_DDR_PERF_MODE,
-       .channels = 1,
-       .buswidth = 4,
-       .num_links = 0,
- };
- 
  static struct qcom_icc_node qup0_core_slave = {
        .name = "qup0_core_slave",
        .id = X1E80100_SLAVE_QUP_CORE_0,
@@@ -1370,6 -1497,76 +1353,6 @@@ static struct qcom_icc_node qns_aggre_u
        .links = { X1E80100_MASTER_AGGRE_USB_SOUTH },
  };
  
 -static struct qcom_icc_node qns_llcc_disp = {
 -      .name = "qns_llcc_disp",
 -      .id = X1E80100_SLAVE_LLCC_DISP,
 -      .channels = 8,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_LLCC_DISP },
 -};
 -
 -static struct qcom_icc_node ebi_disp = {
 -      .name = "ebi_disp",
 -      .id = X1E80100_SLAVE_EBI1_DISP,
 -      .channels = 8,
 -      .buswidth = 4,
 -      .num_links = 0,
 -};
 -
 -static struct qcom_icc_node qns_mem_noc_hf_disp = {
 -      .name = "qns_mem_noc_hf_disp",
 -      .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP,
 -      .channels = 2,
 -      .buswidth = 32,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP },
 -};
 -
 -static struct qcom_icc_node qns_llcc_pcie = {
 -      .name = "qns_llcc_pcie",
 -      .id = X1E80100_SLAVE_LLCC_PCIE,
 -      .channels = 8,
 -      .buswidth = 16,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_LLCC_PCIE },
 -};
 -
 -static struct qcom_icc_node ebi_pcie = {
 -      .name = "ebi_pcie",
 -      .id = X1E80100_SLAVE_EBI1_PCIE,
 -      .channels = 8,
 -      .buswidth = 4,
 -      .num_links = 0,
 -};
 -
 -static struct qcom_icc_node qns_pcie_mem_noc_pcie = {
 -      .name = "qns_pcie_mem_noc_pcie",
 -      .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE },
 -};
 -
 -static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = {
 -      .name = "qns_pcie_north_gem_noc_pcie",
 -      .id = X1E80100_SLAVE_PCIE_NORTH_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_PCIE_NORTH_PCIE },
 -};
 -
 -static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = {
 -      .name = "qns_pcie_south_gem_noc_pcie",
 -      .id = X1E80100_SLAVE_PCIE_SOUTH_PCIE,
 -      .channels = 1,
 -      .buswidth = 64,
 -      .num_links = 1,
 -      .links = { X1E80100_MASTER_PCIE_SOUTH_PCIE },
 -};
 -
  static struct qcom_icc_bcm bcm_acv = {
        .name = "ACV",
        .enable_mask = BIT(3),
@@@ -1377,12 -1574,6 +1360,6 @@@
        .nodes = { &ebi },
  };
  
- static struct qcom_icc_bcm bcm_acv_perf = {
-       .name = "ACV_PERF",
-       .num_nodes = 1,
-       .nodes = { &ddr_perf_mode_slave },
- };
- 
  static struct qcom_icc_bcm bcm_ce0 = {
        .name = "CE0",
        .num_nodes = 1,
@@@ -1542,7 -1733,73 +1519,7 @@@ static struct qcom_icc_bcm bcm_sn4 = 
        .nodes = { &qnm_usb_anoc },
  };
  
 -static struct qcom_icc_bcm bcm_acv_disp = {
 -      .name = "ACV",
 -      .num_nodes = 1,
 -      .nodes = { &ebi_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_mc0_disp = {
 -      .name = "MC0",
 -      .num_nodes = 1,
 -      .nodes = { &ebi_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_mm0_disp = {
 -      .name = "MM0",
 -      .num_nodes = 1,
 -      .nodes = { &qns_mem_noc_hf_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_mm1_disp = {
 -      .name = "MM1",
 -      .num_nodes = 1,
 -      .nodes = { &qnm_mdp_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_sh0_disp = {
 -      .name = "SH0",
 -      .num_nodes = 1,
 -      .nodes = { &qns_llcc_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_sh1_disp = {
 -      .name = "SH1",
 -      .num_nodes = 2,
 -      .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
 -};
 -
 -static struct qcom_icc_bcm bcm_acv_pcie = {
 -      .name = "ACV",
 -      .num_nodes = 1,
 -      .nodes = { &ebi_pcie },
 -};
 -
 -static struct qcom_icc_bcm bcm_mc0_pcie = {
 -      .name = "MC0",
 -      .num_nodes = 1,
 -      .nodes = { &ebi_pcie },
 -};
 -
 -static struct qcom_icc_bcm bcm_pc0_pcie = {
 -      .name = "PC0",
 -      .num_nodes = 1,
 -      .nodes = { &qns_pcie_mem_noc_pcie },
 -};
 -
 -static struct qcom_icc_bcm bcm_sh0_pcie = {
 -      .name = "SH0",
 -      .num_nodes = 1,
 -      .nodes = { &qns_llcc_pcie },
 -};
 -
 -static struct qcom_icc_bcm bcm_sh1_pcie = {
 -      .name = "SH1",
 -      .num_nodes = 1,
 -      .nodes = { &qnm_pcie_pcie },
 -};
 -
 -static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
 +static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
  };
  
  static struct qcom_icc_node * const aggre1_noc_nodes[] = {
@@@ -1583,18 -1840,15 +1560,15 @@@ static const struct qcom_icc_desc x1e80
  };
  
  static struct qcom_icc_bcm * const clk_virt_bcms[] = {
-       &bcm_acv_perf,
        &bcm_qup0,
        &bcm_qup1,
        &bcm_qup2,
  };
  
  static struct qcom_icc_node * const clk_virt_nodes[] = {
-       [MASTER_DDR_PERF_MODE] = &ddr_perf_mode_master,
        [MASTER_QUP_CORE_0] = &qup0_core_master,
        [MASTER_QUP_CORE_1] = &qup1_core_master,
        [MASTER_QUP_CORE_2] = &qup2_core_master,
-       [SLAVE_DDR_PERF_MODE] = &ddr_perf_mode_slave,
        [SLAVE_QUP_CORE_0] = &qup0_core_slave,
        [SLAVE_QUP_CORE_1] = &qup1_core_slave,
        [SLAVE_QUP_CORE_2] = &qup2_core_slave,
@@@ -1703,6 -1957,10 +1677,6 @@@ static const struct qcom_icc_desc x1e80
  static struct qcom_icc_bcm * const gem_noc_bcms[] = {
        &bcm_sh0,
        &bcm_sh1,
 -      &bcm_sh0_disp,
 -      &bcm_sh1_disp,
 -      &bcm_sh0_pcie,
 -      &bcm_sh1_pcie,
  };
  
  static struct qcom_icc_node * const gem_noc_nodes[] = {
@@@ -1721,6 -1979,11 +1695,6 @@@
        [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
        [SLAVE_LLCC] = &qns_llcc,
        [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
 -      [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp,
 -      [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp,
 -      [SLAVE_LLCC_DISP] = &qns_llcc_disp,
 -      [MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie,
 -      [SLAVE_LLCC_PCIE] = &qns_llcc_pcie,
  };
  
  static const struct qcom_icc_desc x1e80100_gem_noc = {
@@@ -1730,7 -1993,7 +1704,7 @@@
        .num_bcms = ARRAY_SIZE(gem_noc_bcms),
  };
  
 -static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
 +static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
  };
  
  static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
@@@ -1779,11 -2042,19 +1753,11 @@@ static const struct qcom_icc_desc x1e80
  static struct qcom_icc_bcm * const mc_virt_bcms[] = {
        &bcm_acv,
        &bcm_mc0,
 -      &bcm_acv_disp,
 -      &bcm_mc0_disp,
 -      &bcm_acv_pcie,
 -      &bcm_mc0_pcie,
  };
  
  static struct qcom_icc_node * const mc_virt_nodes[] = {
        [MASTER_LLCC] = &llcc_mc,
        [SLAVE_EBI1] = &ebi,
 -      [MASTER_LLCC_DISP] = &llcc_mc_disp,
 -      [SLAVE_EBI1_DISP] = &ebi_disp,
 -      [MASTER_LLCC_PCIE] = &llcc_mc_pcie,
 -      [SLAVE_EBI1_PCIE] = &ebi_pcie,
  };
  
  static const struct qcom_icc_desc x1e80100_mc_virt = {
@@@ -1796,6 -2067,8 +1770,6 @@@
  static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
        &bcm_mm0,
        &bcm_mm1,
 -      &bcm_mm0_disp,
 -      &bcm_mm1_disp,
  };
  
  static struct qcom_icc_node * const mmss_noc_nodes[] = {
@@@ -1812,6 -2085,8 +1786,6 @@@
        [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
        [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
        [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
 -      [MASTER_MDP_DISP] = &qnm_mdp_disp,
 -      [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp,
  };
  
  static const struct qcom_icc_desc x1e80100_mmss_noc = {
@@@ -1839,12 -2114,16 +1813,12 @@@ static const struct qcom_icc_desc x1e80
  
  static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = {
        &bcm_pc0,
 -      &bcm_pc0_pcie,
  };
  
  static struct qcom_icc_node * const pcie_center_anoc_nodes[] = {
        [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc,
        [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc,
        [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
 -      [MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie,
 -      [MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie,
 -      [SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie,
  };
  
  static const struct qcom_icc_desc x1e80100_pcie_center_anoc = {
@@@ -1862,6 -2141,10 +1836,6 @@@ static struct qcom_icc_node * const pci
        [MASTER_PCIE_4] = &xm_pcie_4,
        [MASTER_PCIE_5] = &xm_pcie_5,
        [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc,
 -      [MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie,
 -      [MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie,
 -      [MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie,
 -      [SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie,
  };
  
  static const struct qcom_icc_desc x1e80100_pcie_north_anoc = {
@@@ -1871,7 -2154,7 +1845,7 @@@
        .num_bcms = ARRAY_SIZE(pcie_north_anoc_bcms),
  };
  
 -static struct qcom_icc_bcm *pcie_south_anoc_bcms[] = {
 +static struct qcom_icc_bcm * const pcie_south_anoc_bcms[] = {
  };
  
  static struct qcom_icc_node * const pcie_south_anoc_nodes[] = {
@@@ -1881,6 -2164,12 +1855,6 @@@
        [MASTER_PCIE_6A] = &xm_pcie_6a,
        [MASTER_PCIE_6B] = &xm_pcie_6b,
        [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc,
 -      [MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie,
 -      [MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie,
 -      [MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie,
 -      [MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie,
 -      [MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie,
 -      [SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie,
  };
  
  static const struct qcom_icc_desc x1e80100_pcie_south_anoc = {
@@@ -1890,7 -2179,7 +1864,7 @@@
        .num_bcms = ARRAY_SIZE(pcie_south_anoc_bcms),
  };
  
 -static struct qcom_icc_bcm *system_noc_bcms[] = {
 +static struct qcom_icc_bcm * const system_noc_bcms[] = {
        &bcm_sn0,
        &bcm_sn2,
        &bcm_sn3,
@@@ -1928,7 -2217,7 +1902,7 @@@ static const struct qcom_icc_desc x1e80
        .num_bcms = ARRAY_SIZE(usb_center_anoc_bcms),
  };
  
 -static struct qcom_icc_bcm *usb_north_anoc_bcms[] = {
 +static struct qcom_icc_bcm * const usb_north_anoc_bcms[] = {
  };
  
  static struct qcom_icc_node * const usb_north_anoc_nodes[] = {
@@@ -1944,7 -2233,7 +1918,7 @@@ static const struct qcom_icc_desc x1e80
        .num_bcms = ARRAY_SIZE(usb_north_anoc_bcms),
  };
  
 -static struct qcom_icc_bcm *usb_south_anoc_bcms[] = {
 +static struct qcom_icc_bcm * const usb_south_anoc_bcms[] = {
  };
  
  static struct qcom_icc_node * const usb_south_anoc_nodes[] = {