Merge tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry...

Pull pwm updates from Thierry Reding:
 "This contains a couple of fixes and cleanups for the Meson and
  ACPI/LPSS drivers as well as capture support for STM32.

  Note that given the cross- subsystem changes, the STM32 patches were
  merged through the MFD and PWM trees, both sharing an immutable
  branch"

* tag 'pwm/for-4.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
  pwm: stm32: Fix build warning with CONFIG_DMA_ENGINE disabled
  pwm: stm32: Enforce dependency on CONFIG_MFD_STM32_TIMERS
  ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices
  pwm: lpss: platform: Save/restore the ctrl register over a suspend/resume
  dt-bindings: mfd: stm32-timers: Add support for dmas
  pwm: simplify getting .drvdata
  pwm: meson: Fix allocation of PWM channel array

diff --combined drivers/acpi/acpi_lpss.c
index cb6ac5c65c2e4c97f4cc9432d8d701b9e3b3f0da,c4ba9164e582d7ea0c59ff068f04f357ca14adfd..38a286975c31e152206b3e55b28473a2763a717a
--- 1/drivers/acpi/acpi_lpss.c
--- 2/drivers/acpi/acpi_lpss.c
+++ b/drivers/acpi/acpi_lpss.c
@@@ -69,10 -69,6 +69,10 @@@ ACPI_MODULE_NAME("acpi_lpss")
  #define LPSS_SAVE_CTX                 BIT(4)
  #define LPSS_NO_D3_DELAY              BIT(5)
  
 +/* Crystal Cove PMIC shares same ACPI ID between different platforms */
 +#define BYT_CRC_HRV                   2
 +#define CHT_CRC_HRV                   3
 +
  struct lpss_private_data;
  
  struct lpss_device_desc {
@@@ -166,7 -162,7 +166,7 @@@ static void byt_pwm_setup(struct lpss_p
        if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1"))
                return;
  
 -      if (!acpi_dev_present("INT33FD", NULL, -1))
 +      if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV))
                pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup));
  }
  
@@@ -233,11 -229,13 +233,13 @@@ static const struct lpss_device_desc lp
  
  static const struct lpss_device_desc byt_pwm_dev_desc = {
        .flags = LPSS_SAVE_CTX,
+       .prv_offset = 0x800,
        .setup = byt_pwm_setup,
  };
  
  static const struct lpss_device_desc bsw_pwm_dev_desc = {
        .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
+       .prv_offset = 0x800,
        .setup = bsw_pwm_setup,
  };
  

diff --combined drivers/pwm/pwm-stm32.c
index 09383c6720fb623c59bf387909af4eaff010edba,97bbc1f18fd6d25d791a3ef3dd7ad443fc075141..4f842550fbd127ce1b0f53522dfb7f4e60b74329
--- 1/drivers/pwm/pwm-stm32.c
--- 2/drivers/pwm/pwm-stm32.c
+++ b/drivers/pwm/pwm-stm32.c
@@@ -170,7 -170,7 +170,7 @@@ static int stm32_pwm_capture(struct pwm
        unsigned long long prd, div, dty;
        unsigned long rate;
        unsigned int psc = 0, icpsc, scale;
 -      u32 raw_prd, raw_dty;
 +      u32 raw_prd = 0, raw_dty = 0;
        int ret = 0;
  
        mutex_lock(&priv->lock);
@@@ -484,9 -484,7 +484,7 @@@ static int stm32_pwm_apply_locked(struc
  static const struct pwm_ops stm32pwm_ops = {
        .owner = THIS_MODULE,
        .apply = stm32_pwm_apply_locked,
- #if IS_ENABLED(CONFIG_DMA_ENGINE)
-       .capture = stm32_pwm_capture,
- #endif
+       .capture = IS_ENABLED(CONFIG_DMA_ENGINE) ? stm32_pwm_capture : NULL,
  };
  
  static int stm32_pwm_set_breakinput(struct stm32_pwm *priv,