bus: mhi: host: pci_generic: Add generic edl_trigger to allow devices to enter EDL...

Some of the MHI modems like SDX65 based ones are capable of entering the
EDL mode as per the standard triggering mechanism defined in the MHI spec
v1.2. So let's add a common mhi_pci_generic_edl_trigger() function that
triggers the EDL mode in the device when user writes to the
/sys/bus/mhi/devices/.../trigger_edl file.

As per the spec, the EDL mode can be triggered by writing a cookie to the
EDL doorbell register and then resetting the device.

Devices supporting this standard way of entering EDL mode can set the
mhi_pci_dev_info::edl_trigger flag.

Signed-off-by: Qiang Yu <[email protected]>
Reviewed-by: Jeffrey Hugo <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[mani: reworded commit message]
Signed-off-by: Manivannan Sadhasivam <[email protected]>

diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
index 51639bfcfec70835b65d4864ddcc6e7937bb64d0..08844ee79654ae9a7567434328f9e29ce8b5ccd4 100644 (file)
--- a/drivers/bus/mhi/host/pci_generic.c
+++ b/drivers/bus/mhi/host/pci_generic.c
@@ -27,12 +27,16 @@
 #define PCI_VENDOR_ID_THALES   0x1269
 #define PCI_VENDOR_ID_QUECTEL  0x1eac
 
+#define MHI_EDL_DB                     91
+#define MHI_EDL_COOKIE                 0xEDEDEDED
+
 /**
  * struct mhi_pci_dev_info - MHI PCI device specific information
  * @config: MHI controller configuration
  * @name: name of the PCI module
  * @fw: firmware path (if any)
  * @edl: emergency download mode firmware path (if any)
+ * @edl_trigger: capable of triggering EDL mode in the device (if supported)
  * @bar_num: PCI base address register to use for MHI MMIO register space
  * @dma_data_width: DMA transfer word size (32 or 64 bits)
  * @mru_default: default MRU size for MBIM network packets
@@ -44,6 +48,7 @@ struct mhi_pci_dev_info {
        const char *name;
        const char *fw;
        const char *edl;
+       bool edl_trigger;
        unsigned int bar_num;
        unsigned int dma_data_width;
        unsigned int mru_default;
@@ -292,6 +297,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
        .name = "qcom-sdx75m",
        .fw = "qcom/sdx75m/xbl.elf",
        .edl = "qcom/sdx75m/edl.mbn",
+       .edl_trigger = true,
        .config = &modem_qcom_v2_mhiv_config,
        .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
        .dma_data_width = 32,
@@ -302,6 +308,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
        .name = "qcom-sdx65m",
        .fw = "qcom/sdx65m/xbl.elf",
        .edl = "qcom/sdx65m/edl.mbn",
+       .edl_trigger = true,
        .config = &modem_qcom_v1_mhiv_config,
        .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
        .dma_data_width = 32,
@@ -312,6 +319,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
        .name = "qcom-sdx55m",
        .fw = "qcom/sdx55m/sbl1.mbn",
        .edl = "qcom/sdx55m/edl.mbn",
+       .edl_trigger = true,
        .config = &modem_qcom_v1_mhiv_config,
        .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
        .dma_data_width = 32,
@@ -928,6 +936,40 @@ static void health_check(struct timer_list *t)
        mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
 }
 
+static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl)
+{
+       void __iomem *base = mhi_cntrl->regs;
+       void __iomem *edl_db;
+       int ret;
+       u32 val;
+
+       ret = mhi_device_get_sync(mhi_cntrl->mhi_dev);
+       if (ret) {
+               dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n");
+               return ret;
+       }
+
+       pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0);
+       mhi_cntrl->runtime_get(mhi_cntrl);
+
+       ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val);
+       if (ret)
+               goto err_get_chdb;
+
+       edl_db = base + val + (8 * MHI_EDL_DB);
+
+       mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE));
+       mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE));
+
+       mhi_soc_reset(mhi_cntrl);
+
+err_get_chdb:
+       mhi_cntrl->runtime_put(mhi_cntrl);
+       mhi_device_put(mhi_cntrl->mhi_dev);
+
+       return ret;
+}
+
 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 {
        const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data;
@@ -962,6 +1004,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        mhi_cntrl->runtime_put = mhi_pci_runtime_put;
        mhi_cntrl->mru = info->mru_default;
 
+       if (info->edl_trigger)
+               mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger;
+
        if (info->sideband_wake) {
                mhi_cntrl->wake_get = mhi_pci_wake_get_nop;
                mhi_cntrl->wake_put = mhi_pci_wake_put_nop;