x86/tsc: Trust initial offset in architectural TSC-adjust MSRs

When the BIOS configures the architectural TSC-adjust MSRs on secondary
sockets to correct a constant inter-chassis offset, after Linux brings the
cores online, the TSC sync check later resets the core-local MSR to 0,
triggering HPET fallback and leading to performance loss.

Fix this by unconditionally using the initial adjust values read from the
MSRs. Trusting the initial offsets in this architectural mechanism is a
better approach than special-casing workarounds for specific platforms.

Signed-off-by: Daniel J Blueman <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Reviewed-by: Steffen Persvold <[email protected]>
Reviewed-by: James Cleverdon <[email protected]>
Reviewed-by: Dimitri Sivanich <[email protected]>
Reviewed-by: Prarit Bhargava <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 1123ef3ccf9011f55f60d72fb78de75b947b0474..4334033658edfbbe71ec48bda9f8fbcda2749c33 100644 (file)
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -193,11 +193,9 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
        cur->warned = false;
 
        /*
-        * If a non-zero TSC value for socket 0 may be valid then the default
-        * adjusted value cannot assumed to be zero either.
+        * The default adjust value cannot be assumed to be zero on any socket.
         */
-       if (tsc_async_resets)
-               cur->adjusted = bootval;
+       cur->adjusted = bootval;
 
        /*
         * Check whether this CPU is the first in a package to come up. In