Merge 'pci/enumeration' into loongarch-next

LoongArch architecture changes for 6.3 depend on the pci changes
to work well, so merge them to create a base.

diff --combined drivers/pci/pci.c
index 5641786bd020663ebfcb81e09a45b1ed645a339b,9d98bba72af9f957172c6b0b97be593efbd9639c..aee2c9dd2ddca367fea89b0fb193fba8564d479b
--- 1/drivers/pci/pci.c
--- 2/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@@ -1665,6 -1665,7 +1665,6 @@@ int pci_save_state(struct pci_dev *dev
                return i;
  
        pci_save_ltr_state(dev);
 -      pci_save_aspm_l1ss_state(dev);
        pci_save_dpc_state(dev);
        pci_save_aer_state(dev);
        pci_save_ptm_state(dev);
@@@ -1771,6 -1772,7 +1771,6 @@@ void pci_restore_state(struct pci_dev *
         * LTR itself (in the PCIe capability).
         */
        pci_restore_ltr_state(dev);
 -      pci_restore_aspm_l1ss_state(dev);
  
        pci_restore_pcie_state(dev);
        pci_restore_pasid_state(dev);
@@@ -3463,6 -3465,11 +3463,6 @@@ void pci_allocate_cap_save_buffers(stru
        if (error)
                pci_err(dev, "unable to allocate suspend buffer for LTR\n");
  
 -      error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
 -                                          2 * sizeof(u32));
 -      if (error)
 -              pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
 -
        pci_allocate_vc_save_buffers(dev);
  }
  
@@@ -6026,6 -6033,7 +6026,7 @@@ int pcie_set_readrq(struct pci_dev *dev
  {
        u16 v;
        int ret;
+       struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
  
        if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
                return -EINVAL;
@@@ -6044,6 -6052,15 +6045,15 @@@
  
        v = (ffs(rq) - 8) << 12;
  
+       if (bridge->no_inc_mrrs) {
+               int max_mrrs = pcie_get_readrq(dev);
+ 
+               if (rq > max_mrrs) {
+                       pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
+                       return -EINVAL;
+               }
+       }
+ 
        ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
                                                  PCI_EXP_DEVCTL_READRQ, v);
  

diff --combined include/linux/pci.h
index 254c8a4126a89864626c5ca91bd593cc26560355,3df2049ec4a837108aad506aeea7115074f9326d..50042ea8e008377f39389506672aa10167abef07
--- 1/include/linux/pci.h
--- 2/include/linux/pci.h
+++ b/include/linux/pci.h
@@@ -572,6 -572,7 +572,7 @@@ struct pci_host_bridge 
        void            *release_data;
        unsigned int    ignore_reset_delay:1;   /* For entire hierarchy */
        unsigned int    no_ext_tags:1;          /* No Extended Tags */
+       unsigned int    no_inc_mrrs:1;          /* No Increase MRRS */
        unsigned int    native_aer:1;           /* OS may use PCIe AER */
        unsigned int    native_pcie_hotplug:1;  /* OS may use PCIe hotplug */
        unsigned int    native_shpc_hotplug:1;  /* OS may use SHPC hotplug */
@@@ -1621,18 -1622,6 +1622,18 @@@ pci_alloc_irq_vectors(struct pci_dev *d
                                              flags, NULL);
  }
  
 +static inline struct msi_map pci_msix_alloc_irq_at(struct pci_dev *dev, unsigned int index,
 +                                                 const struct irq_affinity_desc *affdesc)
 +{
 +      struct msi_map map = { .index = -ENOSYS, };
 +
 +      return map;
 +}
 +
 +static inline void pci_msix_free_irq(struct pci_dev *pdev, struct msi_map map)
 +{
 +}
 +
  static inline void pci_free_irq_vectors(struct pci_dev *dev)
  {
  }