Merge tag 'x86_sev_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 SEV updates from Borislav Petkov:

 - Add support for running the kernel in a SEV-SNP guest, over a Secure
   VM Service Module (SVSM).

   When running over a SVSM, different services can run at different
   protection levels, apart from the guest OS but still within the
   secure SNP environment. They can provide services to the guest, like
   a vTPM, for example.

   This series adds the required facilities to interface with such a
   SVSM module.

 - The usual fixlets, refactoring and cleanups

[ And as always: "SEV" is AMD's "Secure Encrypted Virtualization".

  I can't be the only one who gets all the newer x86 TLA's confused,
  can I?
              - Linus ]

* tag 'x86_sev_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  Documentation/ABI/configfs-tsm: Fix an unexpected indentation silly
  x86/sev: Do RMP memory coverage check after max_pfn has been set
  x86/sev: Move SEV compilation units
  virt: sev-guest: Mark driver struct with __refdata to prevent section mismatch
  x86/sev: Allow non-VMPL0 execution when an SVSM is present
  x86/sev: Extend the config-fs attestation support for an SVSM
  x86/sev: Take advantage of configfs visibility support in TSM
  fs/configfs: Add a callback to determine attribute visibility
  sev-guest: configfs-tsm: Allow the privlevel_floor attribute to be updated
  virt: sev-guest: Choose the VMPCK key based on executing VMPL
  x86/sev: Provide guest VMPL level to userspace
  x86/sev: Provide SVSM discovery support
  x86/sev: Use the SVSM to create a vCPU when not in VMPL0
  x86/sev: Perform PVALIDATE using the SVSM when not at VMPL0
  x86/sev: Use kernel provided SVSM Calling Areas
  x86/sev: Check for the presence of an SVSM in the SNP secrets page
  x86/irqflags: Provide native versions of the local_irq_save()/restore()

diff --cc Documentation/ABI/testing/sysfs-devices-system-cpu
Simple merge

diff --cc arch/x86/include/asm/cpufeatures.h
index a1dd81027c2d3197645f06c5f188d2a871fe0098,1826f1f9411155639db970537f1ed9a3b3754847..b51e88d01b21da6ebd1f3f908944d2a70779d23d
--- 1/arch/x86/include/asm/cpufeatures.h
--- 2/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@@ -370,94 -370,95 +370,95 @@@
  #define X86_FEATURE_NRIPS             (15*32+ 3) /* "nrip_save" SVM next_rip save */
  #define X86_FEATURE_TSCRATEMSR                (15*32+ 4) /* "tsc_scale" TSC scaling support */
  #define X86_FEATURE_VMCBCLEAN         (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
 -#define X86_FEATURE_FLUSHBYASID               (15*32+ 6) /* flush-by-ASID support */
 -#define X86_FEATURE_DECODEASSISTS     (15*32+ 7) /* Decode Assists support */
 -#define X86_FEATURE_PAUSEFILTER               (15*32+10) /* filtered pause intercept */
 -#define X86_FEATURE_PFTHRESHOLD               (15*32+12) /* pause filter threshold */
 -#define X86_FEATURE_AVIC              (15*32+13) /* Virtual Interrupt Controller */
 -#define X86_FEATURE_V_VMSAVE_VMLOAD   (15*32+15) /* Virtual VMSAVE VMLOAD */
 -#define X86_FEATURE_VGIF              (15*32+16) /* Virtual GIF */
 -#define X86_FEATURE_X2AVIC            (15*32+18) /* Virtual x2apic */
 -#define X86_FEATURE_V_SPEC_CTRL               (15*32+20) /* Virtual SPEC_CTRL */
 -#define X86_FEATURE_VNMI              (15*32+25) /* Virtual NMI */
 -#define X86_FEATURE_SVME_ADDR_CHK     (15*32+28) /* "" SVME addr check */
 +#define X86_FEATURE_FLUSHBYASID               (15*32+ 6) /* "flushbyasid" Flush-by-ASID support */
 +#define X86_FEATURE_DECODEASSISTS     (15*32+ 7) /* "decodeassists" Decode Assists support */
 +#define X86_FEATURE_PAUSEFILTER               (15*32+10) /* "pausefilter" Filtered pause intercept */
 +#define X86_FEATURE_PFTHRESHOLD               (15*32+12) /* "pfthreshold" Pause filter threshold */
 +#define X86_FEATURE_AVIC              (15*32+13) /* "avic" Virtual Interrupt Controller */
 +#define X86_FEATURE_V_VMSAVE_VMLOAD   (15*32+15) /* "v_vmsave_vmload" Virtual VMSAVE VMLOAD */
 +#define X86_FEATURE_VGIF              (15*32+16) /* "vgif" Virtual GIF */
 +#define X86_FEATURE_X2AVIC            (15*32+18) /* "x2avic" Virtual x2apic */
 +#define X86_FEATURE_V_SPEC_CTRL               (15*32+20) /* "v_spec_ctrl" Virtual SPEC_CTRL */
 +#define X86_FEATURE_VNMI              (15*32+25) /* "vnmi" Virtual NMI */
 +#define X86_FEATURE_SVME_ADDR_CHK     (15*32+28) /* SVME addr check */
  
  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
 -#define X86_FEATURE_AVX512VBMI                (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
 -#define X86_FEATURE_UMIP              (16*32+ 2) /* User Mode Instruction Protection */
 -#define X86_FEATURE_PKU                       (16*32+ 3) /* Protection Keys for Userspace */
 -#define X86_FEATURE_OSPKE             (16*32+ 4) /* OS Protection Keys Enable */
 -#define X86_FEATURE_WAITPKG           (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
 -#define X86_FEATURE_AVX512_VBMI2      (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
 -#define X86_FEATURE_SHSTK             (16*32+ 7) /* "" Shadow stack */
 -#define X86_FEATURE_GFNI              (16*32+ 8) /* Galois Field New Instructions */
 -#define X86_FEATURE_VAES              (16*32+ 9) /* Vector AES */
 -#define X86_FEATURE_VPCLMULQDQ                (16*32+10) /* Carry-Less Multiplication Double Quadword */
 -#define X86_FEATURE_AVX512_VNNI               (16*32+11) /* Vector Neural Network Instructions */
 -#define X86_FEATURE_AVX512_BITALG     (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
 -#define X86_FEATURE_TME                       (16*32+13) /* Intel Total Memory Encryption */
 -#define X86_FEATURE_AVX512_VPOPCNTDQ  (16*32+14) /* POPCNT for vectors of DW/QW */
 -#define X86_FEATURE_LA57              (16*32+16) /* 5-level page tables */
 -#define X86_FEATURE_RDPID             (16*32+22) /* RDPID instruction */
 -#define X86_FEATURE_BUS_LOCK_DETECT   (16*32+24) /* Bus Lock detect */
 -#define X86_FEATURE_CLDEMOTE          (16*32+25) /* CLDEMOTE instruction */
 -#define X86_FEATURE_MOVDIRI           (16*32+27) /* MOVDIRI instruction */
 -#define X86_FEATURE_MOVDIR64B         (16*32+28) /* MOVDIR64B instruction */
 -#define X86_FEATURE_ENQCMD            (16*32+29) /* ENQCMD and ENQCMDS instructions */
 -#define X86_FEATURE_SGX_LC            (16*32+30) /* Software Guard Extensions Launch Control */
 +#define X86_FEATURE_AVX512VBMI                (16*32+ 1) /* "avx512vbmi" AVX512 Vector Bit Manipulation instructions*/
 +#define X86_FEATURE_UMIP              (16*32+ 2) /* "umip" User Mode Instruction Protection */
 +#define X86_FEATURE_PKU                       (16*32+ 3) /* "pku" Protection Keys for Userspace */
 +#define X86_FEATURE_OSPKE             (16*32+ 4) /* "ospke" OS Protection Keys Enable */
 +#define X86_FEATURE_WAITPKG           (16*32+ 5) /* "waitpkg" UMONITOR/UMWAIT/TPAUSE Instructions */
 +#define X86_FEATURE_AVX512_VBMI2      (16*32+ 6) /* "avx512_vbmi2" Additional AVX512 Vector Bit Manipulation Instructions */
 +#define X86_FEATURE_SHSTK             (16*32+ 7) /* Shadow stack */
 +#define X86_FEATURE_GFNI              (16*32+ 8) /* "gfni" Galois Field New Instructions */
 +#define X86_FEATURE_VAES              (16*32+ 9) /* "vaes" Vector AES */
 +#define X86_FEATURE_VPCLMULQDQ                (16*32+10) /* "vpclmulqdq" Carry-Less Multiplication Double Quadword */
 +#define X86_FEATURE_AVX512_VNNI               (16*32+11) /* "avx512_vnni" Vector Neural Network Instructions */
 +#define X86_FEATURE_AVX512_BITALG     (16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
 +#define X86_FEATURE_TME                       (16*32+13) /* "tme" Intel Total Memory Encryption */
 +#define X86_FEATURE_AVX512_VPOPCNTDQ  (16*32+14) /* "avx512_vpopcntdq" POPCNT for vectors of DW/QW */
 +#define X86_FEATURE_LA57              (16*32+16) /* "la57" 5-level page tables */
 +#define X86_FEATURE_RDPID             (16*32+22) /* "rdpid" RDPID instruction */
 +#define X86_FEATURE_BUS_LOCK_DETECT   (16*32+24) /* "bus_lock_detect" Bus Lock detect */
 +#define X86_FEATURE_CLDEMOTE          (16*32+25) /* "cldemote" CLDEMOTE instruction */
 +#define X86_FEATURE_MOVDIRI           (16*32+27) /* "movdiri" MOVDIRI instruction */
 +#define X86_FEATURE_MOVDIR64B         (16*32+28) /* "movdir64b" MOVDIR64B instruction */
 +#define X86_FEATURE_ENQCMD            (16*32+29) /* "enqcmd" ENQCMD and ENQCMDS instructions */
 +#define X86_FEATURE_SGX_LC            (16*32+30) /* "sgx_lc" Software Guard Extensions Launch Control */
  
  /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
 -#define X86_FEATURE_OVERFLOW_RECOV    (17*32+ 0) /* MCA overflow recovery support */
 -#define X86_FEATURE_SUCCOR            (17*32+ 1) /* Uncorrectable error containment and recovery */
 -#define X86_FEATURE_SMCA              (17*32+ 3) /* Scalable MCA */
 +#define X86_FEATURE_OVERFLOW_RECOV    (17*32+ 0) /* "overflow_recov" MCA overflow recovery support */
 +#define X86_FEATURE_SUCCOR            (17*32+ 1) /* "succor" Uncorrectable error containment and recovery */
 +#define X86_FEATURE_SMCA              (17*32+ 3) /* "smca" Scalable MCA */
  
  /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
 -#define X86_FEATURE_AVX512_4VNNIW     (18*32+ 2) /* AVX-512 Neural Network Instructions */
 -#define X86_FEATURE_AVX512_4FMAPS     (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
 -#define X86_FEATURE_FSRM              (18*32+ 4) /* Fast Short Rep Mov */
 -#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
 -#define X86_FEATURE_SRBDS_CTRL                (18*32+ 9) /* "" SRBDS mitigation MSR available */
 -#define X86_FEATURE_MD_CLEAR          (18*32+10) /* VERW clears CPU buffers */
 -#define X86_FEATURE_RTM_ALWAYS_ABORT  (18*32+11) /* "" RTM transaction always aborts */
 -#define X86_FEATURE_TSX_FORCE_ABORT   (18*32+13) /* "" TSX_FORCE_ABORT */
 -#define X86_FEATURE_SERIALIZE         (18*32+14) /* SERIALIZE instruction */
 -#define X86_FEATURE_HYBRID_CPU                (18*32+15) /* "" This part has CPUs of more than one type */
 -#define X86_FEATURE_TSXLDTRK          (18*32+16) /* TSX Suspend Load Address Tracking */
 -#define X86_FEATURE_PCONFIG           (18*32+18) /* Intel PCONFIG */
 -#define X86_FEATURE_ARCH_LBR          (18*32+19) /* Intel ARCH LBR */
 -#define X86_FEATURE_IBT                       (18*32+20) /* Indirect Branch Tracking */
 -#define X86_FEATURE_AMX_BF16          (18*32+22) /* AMX bf16 Support */
 -#define X86_FEATURE_AVX512_FP16               (18*32+23) /* AVX512 FP16 */
 -#define X86_FEATURE_AMX_TILE          (18*32+24) /* AMX tile Support */
 -#define X86_FEATURE_AMX_INT8          (18*32+25) /* AMX int8 Support */
 -#define X86_FEATURE_SPEC_CTRL         (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
 -#define X86_FEATURE_INTEL_STIBP               (18*32+27) /* "" Single Thread Indirect Branch Predictors */
 -#define X86_FEATURE_FLUSH_L1D         (18*32+28) /* Flush L1D cache */
 -#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
 -#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
 -#define X86_FEATURE_SPEC_CTRL_SSBD    (18*32+31) /* "" Speculative Store Bypass Disable */
 +#define X86_FEATURE_AVX512_4VNNIW     (18*32+ 2) /* "avx512_4vnniw" AVX-512 Neural Network Instructions */
 +#define X86_FEATURE_AVX512_4FMAPS     (18*32+ 3) /* "avx512_4fmaps" AVX-512 Multiply Accumulation Single precision */
 +#define X86_FEATURE_FSRM              (18*32+ 4) /* "fsrm" Fast Short Rep Mov */
 +#define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* "avx512_vp2intersect" AVX-512 Intersect for D/Q */
 +#define X86_FEATURE_SRBDS_CTRL                (18*32+ 9) /* SRBDS mitigation MSR available */
 +#define X86_FEATURE_MD_CLEAR          (18*32+10) /* "md_clear" VERW clears CPU buffers */
 +#define X86_FEATURE_RTM_ALWAYS_ABORT  (18*32+11) /* RTM transaction always aborts */
 +#define X86_FEATURE_TSX_FORCE_ABORT   (18*32+13) /* TSX_FORCE_ABORT */
 +#define X86_FEATURE_SERIALIZE         (18*32+14) /* "serialize" SERIALIZE instruction */
 +#define X86_FEATURE_HYBRID_CPU                (18*32+15) /* This part has CPUs of more than one type */
 +#define X86_FEATURE_TSXLDTRK          (18*32+16) /* "tsxldtrk" TSX Suspend Load Address Tracking */
 +#define X86_FEATURE_PCONFIG           (18*32+18) /* "pconfig" Intel PCONFIG */
 +#define X86_FEATURE_ARCH_LBR          (18*32+19) /* "arch_lbr" Intel ARCH LBR */
 +#define X86_FEATURE_IBT                       (18*32+20) /* "ibt" Indirect Branch Tracking */
 +#define X86_FEATURE_AMX_BF16          (18*32+22) /* "amx_bf16" AMX bf16 Support */
 +#define X86_FEATURE_AVX512_FP16               (18*32+23) /* "avx512_fp16" AVX512 FP16 */
 +#define X86_FEATURE_AMX_TILE          (18*32+24) /* "amx_tile" AMX tile Support */
 +#define X86_FEATURE_AMX_INT8          (18*32+25) /* "amx_int8" AMX int8 Support */
 +#define X86_FEATURE_SPEC_CTRL         (18*32+26) /* Speculation Control (IBRS + IBPB) */
 +#define X86_FEATURE_INTEL_STIBP               (18*32+27) /* Single Thread Indirect Branch Predictors */
 +#define X86_FEATURE_FLUSH_L1D         (18*32+28) /* "flush_l1d" Flush L1D cache */
 +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* "arch_capabilities" IA32_ARCH_CAPABILITIES MSR (Intel) */
 +#define X86_FEATURE_CORE_CAPABILITIES (18*32+30) /* IA32_CORE_CAPABILITIES MSR */
 +#define X86_FEATURE_SPEC_CTRL_SSBD    (18*32+31) /* Speculative Store Bypass Disable */
  
  /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
 -#define X86_FEATURE_SME                       (19*32+ 0) /* AMD Secure Memory Encryption */
 -#define X86_FEATURE_SEV                       (19*32+ 1) /* AMD Secure Encrypted Virtualization */
 -#define X86_FEATURE_VM_PAGE_FLUSH     (19*32+ 2) /* "" VM Page Flush MSR is supported */
 -#define X86_FEATURE_SEV_ES            (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
 -#define X86_FEATURE_SEV_SNP           (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */
 -#define X86_FEATURE_V_TSC_AUX         (19*32+ 9) /* "" Virtual TSC_AUX */
 -#define X86_FEATURE_SME_COHERENT      (19*32+10) /* "" AMD hardware-enforced cache coherency */
 -#define X86_FEATURE_DEBUG_SWAP                (19*32+14) /* AMD SEV-ES full debug state swap support */
 -#define X86_FEATURE_SVSM              (19*32+28) /* SVSM present */
 +#define X86_FEATURE_SME                       (19*32+ 0) /* "sme" AMD Secure Memory Encryption */
 +#define X86_FEATURE_SEV                       (19*32+ 1) /* "sev" AMD Secure Encrypted Virtualization */
 +#define X86_FEATURE_VM_PAGE_FLUSH     (19*32+ 2) /* VM Page Flush MSR is supported */
 +#define X86_FEATURE_SEV_ES            (19*32+ 3) /* "sev_es" AMD Secure Encrypted Virtualization - Encrypted State */
 +#define X86_FEATURE_SEV_SNP           (19*32+ 4) /* "sev_snp" AMD Secure Encrypted Virtualization - Secure Nested Paging */
 +#define X86_FEATURE_V_TSC_AUX         (19*32+ 9) /* Virtual TSC_AUX */
 +#define X86_FEATURE_SME_COHERENT      (19*32+10) /* AMD hardware-enforced cache coherency */
 +#define X86_FEATURE_DEBUG_SWAP                (19*32+14) /* "debug_swap" AMD SEV-ES full debug state swap support */
++#define X86_FEATURE_SVSM              (19*32+28) /* "svsm" SVSM present */
  
  /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
 -#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" No Nested Data Breakpoints */
 -#define X86_FEATURE_WRMSR_XX_BASE_NS  (20*32+ 1) /* "" WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
 -#define X86_FEATURE_LFENCE_RDTSC      (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */
 -#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* "" Null Selector Clears Base */
 -#define X86_FEATURE_AUTOIBRS          (20*32+ 8) /* "" Automatic IBRS */
 -#define X86_FEATURE_NO_SMM_CTL_MSR    (20*32+ 9) /* "" SMM_CTL MSR is not present */
 +#define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* No Nested Data Breakpoints */
 +#define X86_FEATURE_WRMSR_XX_BASE_NS  (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing */
 +#define X86_FEATURE_LFENCE_RDTSC      (20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */
 +#define X86_FEATURE_NULL_SEL_CLR_BASE (20*32+ 6) /* Null Selector Clears Base */
 +#define X86_FEATURE_AUTOIBRS          (20*32+ 8) /* Automatic IBRS */
 +#define X86_FEATURE_NO_SMM_CTL_MSR    (20*32+ 9) /* SMM_CTL MSR is not present */
  
 -#define X86_FEATURE_SBPB              (20*32+27) /* "" Selective Branch Prediction Barrier */
 -#define X86_FEATURE_IBPB_BRTYPE               (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
 -#define X86_FEATURE_SRSO_NO           (20*32+29) /* "" CPU is not affected by SRSO */
 +#define X86_FEATURE_SBPB              (20*32+27) /* Selective Branch Prediction Barrier */
 +#define X86_FEATURE_IBPB_BRTYPE               (20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */
 +#define X86_FEATURE_SRSO_NO           (20*32+29) /* CPU is not affected by SRSO */
  
  /*
   * Extended auxiliary flags: Linux defined - for features scattered in various

diff --cc arch/x86/include/asm/msr-index.h
Simple merge

diff --cc arch/x86/mm/mem_encrypt_amd.c
Simple merge