ASoC: Intel: sof-rt5682: support bclk as PLL source on rt5682s

For rt5682s codec, we could use bclk as PLL source when the frequency
is 3.072MHz but no 2.4MHz. Update the code to select correct pll_id
and clk_id for 3.072MHz bclk.

Reviewed-by: Bard Liao <[email protected]>
Signed-off-by: Brent Lu <[email protected]>
Signed-off-by: Pierre-Louis Bossart <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c
index c3b026868653ad0cc1221b7c8e160f1c6e34f5e6..e3a2ec6b4c7cd45c1a65a3a13a40660fe30a5366 100644 (file)
--- a/sound/soc/intel/boards/sof_rt5682.c
+++ b/sound/soc/intel/boards/sof_rt5682.c
@@ -355,18 +355,23 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream,
                        clk_id = RT5682_SCLK_S_PLL1;
                        break;
                case CODEC_RT5682S:
-                       /*
-                        * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1  We don't test
-                        * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
-                        * input, so we have no choice but to use PLL1. Besides, we will not use PLL at
-                        * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
-                        */
-                       if (pll_in == 24576000) {
+                       /* check plla_table and pllb_table in rt5682s.c */
+                       switch (pll_in) {
+                       case 3072000:
+                       case 24576000:
+                               /*
+                                * For MCLK = 24.576MHz and sample rate = 96KHz case, use PLL1  We don't test
+                                * pll_out or params_rate() here since rt5682s PLL2 doesn't support 24.576MHz
+                                * input, so we have no choice but to use PLL1. Besides, we will not use PLL at
+                                * all if pll_in == pll_out. ex, MCLK = 24.576Mhz and sample rate = 48KHz
+                                */
                                pll_id = RT5682S_PLL1;
                                clk_id = RT5682S_SCLK_S_PLL1;
-                       } else {
+                               break;
+                       default:
                                pll_id = RT5682S_PLL2;
                                clk_id = RT5682S_SCLK_S_PLL2;
+                               break;
                        }
                        break;
                default: