MIPS: CI20: Add second percpu timer for SMP.

1.Add a new TCU channel as the percpu timer of core1, this is to
  prepare for the subsequent SMP support. The newly added channel
  will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
  order in jz4780.dtsi file.

Tested-by: Nikolaus Schaller <[email protected]> # on CI20
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
Acked-by: Paul Cercueil <[email protected]>
Signed-off-by: Thomas Bogendoerfer <[email protected]>

diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 3a4eaf1f3f4878cfca68636e21ae135fd0e14738..a688809beebca7c754d8e7b3430b1762caef060c 100644 (file)
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,6 +118,20 @@
        assigned-clock-rates = <48000000>;
 };
 
        assigned-clock-rates = <48000000>;
 };
 

+&tcu {
+       /*
+        * 750 kHz for the system timers and clocksource,
+        * use channel #0 and #1 for the per cpu system timers,
+        * and use channel #2 for the clocksource.
+        *
+        * 3000 kHz for the OST timer to provide a higher
+        * precision clocksource.
+        */
+       assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+                                         <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+       assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
+};
+

 &mmc0 {
        status = "okay";
 
 &mmc0 {
        status = "okay";
 


@@ -522,13 +536,3 @@
                bias-disable;
        };
 };
                bias-disable;
        };
 };

-
-&tcu {
-       /*
-        * 750 kHz for the system timer and clocksource,
-        * use channel #0 for the system timer, #1 for the clocksource.
-        */
-       assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
-                                         <&tcu TCU_CLK_OST>;
-       assigned-clock-rates = <750000>, <750000>, <3000000>;
-};