Merge tag 'spi-fix-v6.6-merge-window' of git://git.kernel.org/pub/scm/linux/kernel...

Pull spi fixes from Mark Brown:
 "A couple of fixes for the sun6i driver. The patch to reduce DMA RX to
  single byte width all the time is *hopefully* excessively cautious but
  it's unclear which SoCs are affected so the fix just covers everything
  for safety"

* tag 'spi-fix-v6.6-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: sun6i: fix race between DMA RX transfer completion and RX FIFO drain
  spi: sun6i: reduce DMA RX transfer width to single byte

diff --combined drivers/spi/spi-sun6i.c
index 3f5b1556ece0227c4edfe2ab056d041408f4ff46,57c828e73c446372cbf05e9da1116bd02e4de764..fddc633097736a212df994130c514a2bd46f656e
--- 1/drivers/spi/spi-sun6i.c
--- 2/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@@ -14,7 -14,7 +14,7 @@@
  #include <linux/interrupt.h>
  #include <linux/io.h>
  #include <linux/module.h>
 -#include <linux/of_device.h>
 +#include <linux/of.h>
  #include <linux/platform_device.h>
  #include <linux/pm_runtime.h>
  #include <linux/reset.h>
@@@ -83,9 -83,6 +83,9 @@@
  #define SUN6I_XMIT_CNT_REG            0x34
  
  #define SUN6I_BURST_CTL_CNT_REG               0x38
 +#define SUN6I_BURST_CTL_CNT_STC_MASK          GENMASK(23, 0)
 +#define SUN6I_BURST_CTL_CNT_DRM                       BIT(28)
 +#define SUN6I_BURST_CTL_CNT_QUAD_EN           BIT(29)
  
  #define SUN6I_TXDATA_REG              0x200
  #define SUN6I_RXDATA_REG              0x300
@@@ -93,7 -90,6 +93,7 @@@
  struct sun6i_spi_cfg {
        unsigned long           fifo_depth;
        bool                    has_clk_ctl;
 +      u32                     mode_bits;
  };
  
  struct sun6i_spi {
@@@ -106,6 -102,7 +106,7 @@@
        struct reset_control    *rstc;
  
        struct completion       done;
+       struct completion       dma_rx_done;
  
        const u8                *tx_buf;
        u8                      *rx_buf;
@@@ -200,6 -197,13 +201,13 @@@ static size_t sun6i_spi_max_transfer_si
        return SUN6I_MAX_XFER_SIZE - 1;
  }
  
+ static void sun6i_spi_dma_rx_cb(void *param)
+ {
+       struct sun6i_spi *sspi = param;
+ 
+       complete(&sspi->dma_rx_done);
+ }
+ 
  static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
                                 struct spi_transfer *tfr)
  {
@@@ -211,7 -215,7 +219,7 @@@
                struct dma_slave_config rxconf = {
                        .direction = DMA_DEV_TO_MEM,
                        .src_addr = sspi->dma_addr_rx,
-                       .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
+                       .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
                        .src_maxburst = 8,
                };
  
@@@ -224,6 -228,8 +232,8 @@@
                                                 DMA_PREP_INTERRUPT);
                if (!rxdesc)
                        return -EINVAL;
+               rxdesc->callback_param = sspi;
+               rxdesc->callback = sun6i_spi_dma_rx_cb;
        }
  
        txdesc = NULL;
@@@ -270,7 -276,7 +280,7 @@@ static int sun6i_spi_transfer_one(struc
        unsigned int div, div_cdr1, div_cdr2, timeout;
        unsigned int start, end, tx_time;
        unsigned int trig_level;
 -      unsigned int tx_len = 0, rx_len = 0;
 +      unsigned int tx_len = 0, rx_len = 0, nbits = 0;
        bool use_dma;
        int ret = 0;
        u32 reg;
@@@ -279,6 -285,7 +289,7 @@@
                return -EINVAL;
  
        reinit_completion(&sspi->done);
+       reinit_completion(&sspi->dma_rx_done);
        sspi->tx_buf = tfr->tx_buf;
        sspi->rx_buf = tfr->rx_buf;
        sspi->len = tfr->len;
@@@ -422,29 -429,13 +433,29 @@@
        sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
  
        /* Setup the transfer now... */
 -      if (sspi->tx_buf)
 +      if (sspi->tx_buf) {
                tx_len = tfr->len;
 +              nbits = tfr->tx_nbits;
 +      } else if (tfr->rx_buf) {
 +              nbits = tfr->rx_nbits;
 +      }
 +
 +      switch (nbits) {
 +      case SPI_NBITS_DUAL:
 +              reg = SUN6I_BURST_CTL_CNT_DRM;
 +              break;
 +      case SPI_NBITS_QUAD:
 +              reg = SUN6I_BURST_CTL_CNT_QUAD_EN;
 +              break;
 +      case SPI_NBITS_SINGLE:
 +      default:
 +              reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len);
 +      }
  
        /* Setup the counters */
 +      sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
        sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
        sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
 -      sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
  
        if (!use_dma) {
                /* Fill the TX FIFO */
@@@ -479,6 -470,22 +490,22 @@@
        start = jiffies;
        timeout = wait_for_completion_timeout(&sspi->done,
                                              msecs_to_jiffies(tx_time));
+ 
+       if (!use_dma) {
+               sun6i_spi_drain_fifo(sspi);
+       } else {
+               if (timeout && rx_len) {
+                       /*
+                        * Even though RX on the peripheral side has finished
+                        * RX DMA might still be in flight
+                        */
+                       timeout = wait_for_completion_timeout(&sspi->dma_rx_done,
+                                                             timeout);
+                       if (!timeout)
+                               dev_warn(&master->dev, "RX DMA timeout\n");
+               }
+       }
+ 
        end = jiffies;
        if (!timeout) {
                dev_warn(&master->dev,
@@@ -506,7 -513,6 +533,6 @@@ static irqreturn_t sun6i_spi_handler(in
        /* Transfer complete */
        if (status & SUN6I_INT_CTL_TC) {
                sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
-               sun6i_spi_drain_fifo(sspi);
                complete(&sspi->done);
                return IRQ_HANDLED;
        }
@@@ -643,8 -649,7 +669,8 @@@ static int sun6i_spi_probe(struct platf
        master->set_cs = sun6i_spi_set_cs;
        master->transfer_one = sun6i_spi_transfer_one;
        master->num_chipselect = 4;
 -      master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 +      master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 +                          sspi->cfg->mode_bits;
        master->bits_per_word_mask = SPI_BPW_MASK(8);
        master->dev.of_node = pdev->dev.of_node;
        master->auto_runtime_pm = true;
@@@ -665,6 -670,7 +691,7 @@@
        }
  
        init_completion(&sspi->done);
+       init_completion(&sspi->dma_rx_done);
  
        sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
        if (IS_ERR(sspi->rstc)) {
@@@ -761,7 -767,6 +788,7 @@@ static const struct sun6i_spi_cfg sun8i
  
  static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
        .fifo_depth     = SUN8I_FIFO_DEPTH,
 +      .mode_bits      = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD,
  };
  
  static const struct of_device_id sun6i_spi_match[] = {