arm64: dts: renesas: r9a08g045: Add RTC node

Add the DT node for the RTC IP available on the Renesas RZ/G3S SoC.

Reviewed-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index a1d5084b074a493209d74fb9158d0ac1af566973..be8a0a768c65b4b51a9abca0e36453e8e8a75710 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r9a08g045-cpg.h>
+#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
 
 / {
        compatible = "renesas,r9a08g045";
@@ -72,6 +73,20 @@
                        status = "disabled";
                };
 
+               rtc: rtc@1004ec00 {
+                       compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
+                       reg = <0 0x1004ec00 0 0x400>;
+                       interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "alarm", "period", "carry";
+                       clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
+                       clock-names = "bus", "counter";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A08G045_VBAT_BRESETN>;
+                       status = "disabled";
+               };
+
                vbattb: clock-controller@1005c000 {
                        compatible = "renesas,r9a08g045-vbattb";
                        reg = <0 0x1005c000 0 0x1000>;