Merge branch 'for-5.4' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie...

diff --combined drivers/spi/spi-fsl-lpspi.c
index 5efd73cd0eadd33390e3c6d0f6edabada82c5783,3528ed5eea9b55e51594b235d4e4305e4835cafc..6f4769a53f8a11e52b76b31df020e529db09abf4
--- 1/drivers/spi/spi-fsl-lpspi.c
--- 2/drivers/spi/spi-fsl-lpspi.c
+++ b/drivers/spi/spi-fsl-lpspi.c
@@@ -779,7 -779,7 +779,7 @@@ static irqreturn_t fsl_lpspi_isr(int ir
  
        if (temp_SR & SR_FCF && (temp_IER & IER_FCIE)) {
                writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
 -                      complete(&fsl_lpspi->xfer_done);
 +              complete(&fsl_lpspi->xfer_done);
                return IRQ_HANDLED;
        }
  
@@@ -938,7 -938,7 +938,7 @@@ static int fsl_lpspi_probe(struct platf
        ret = pm_runtime_get_sync(fsl_lpspi->dev);
        if (ret < 0) {
                dev_err(fsl_lpspi->dev, "failed to enable clock\n");
-               return ret;
+               goto out_controller_put;
        }
  
        temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);

diff --combined drivers/spi/spi-fsl-qspi.c
index 51385b0927e3f45a16fb9347571a3eb0b4ccc409,63c9f7edaf6cb323a766fdceb6c595334e25e336..79b1558b74b8a43254c6a57ec356632c122a0b42
--- 1/drivers/spi/spi-fsl-qspi.c
--- 2/drivers/spi/spi-fsl-qspi.c
+++ b/drivers/spi/spi-fsl-qspi.c
@@@ -63,11 -63,11 +63,16 @@@
  #define QUADSPI_IPCR                  0x08
  #define QUADSPI_IPCR_SEQID(x)         ((x) << 24)
  
+ #define QUADSPI_FLSHCR                        0x0c
+ #define QUADSPI_FLSHCR_TCSS_MASK      GENMASK(3, 0)
+ #define QUADSPI_FLSHCR_TCSH_MASK      GENMASK(11, 8)
+ #define QUADSPI_FLSHCR_TDH_MASK               GENMASK(17, 16)
+ 
 +#define QUADSPI_BUF0CR                  0x10
 +#define QUADSPI_BUF1CR                  0x14
 +#define QUADSPI_BUF2CR                  0x18
 +#define QUADSPI_BUFXCR_INVALID_MSTRID   0xe
 +
  #define QUADSPI_BUF3CR                        0x1c
  #define QUADSPI_BUF3CR_ALLMST_MASK    BIT(31)
  #define QUADSPI_BUF3CR_ADATSZ(x)      ((x) << 8)
@@@ -100,6 -100,9 +105,9 @@@
  #define QUADSPI_FR                    0x160
  #define QUADSPI_FR_TFF_MASK           BIT(0)
  
+ #define QUADSPI_RSER                  0x164
+ #define QUADSPI_RSER_TFIE             BIT(0)
+ 
  #define QUADSPI_SPTRCLR                       0x16c
  #define QUADSPI_SPTRCLR_IPPTRC                BIT(8)
  #define QUADSPI_SPTRCLR_BFPTRC                BIT(0)
@@@ -117,9 -120,6 +125,6 @@@
  #define QUADSPI_LCKER_LOCK            BIT(0)
  #define QUADSPI_LCKER_UNLOCK          BIT(1)
  
- #define QUADSPI_RSER                  0x164
- #define QUADSPI_RSER_TFIE             BIT(0)
- 
  #define QUADSPI_LUT_BASE              0x310
  #define QUADSPI_LUT_OFFSET            (SEQID_LUT * 4 * 4)
  #define QUADSPI_LUT_REG(idx) \
@@@ -186,10 -186,15 +191,16 @@@
   */
  #define QUADSPI_QUIRK_BASE_INTERNAL   BIT(4)
  
+ /*
+  * Controller uses TDH bits in register QUADSPI_FLSHCR.
+  * They need to be set in accordance with the DDR/SDR mode.
+  */
+ #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
+ 
  struct fsl_qspi_devtype_data {
        unsigned int rxfifo;
        unsigned int txfifo;
 +      int invalid_mstrid;
        unsigned int ahb_buf_size;
        unsigned int quirks;
        bool little_endian;
@@@ -198,7 -203,6 +209,7 @@@
  static const struct fsl_qspi_devtype_data vybrid_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_64,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
        .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
        .little_endian = true,
@@@ -207,7 -211,6 +218,7 @@@
  static const struct fsl_qspi_devtype_data imx6sx_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
        .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
        .little_endian = true,
@@@ -216,25 -219,24 +227,27 @@@
  static const struct fsl_qspi_devtype_data imx7d_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
  };
  
  static const struct fsl_qspi_devtype_data imx6ul_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_512,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
-       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK,
+       .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
+                 QUADSPI_QUIRK_USE_TDH_SETTING,
        .little_endian = true,
  };
  
  static const struct fsl_qspi_devtype_data ls1021a_data = {
        .rxfifo = SZ_128,
        .txfifo = SZ_64,
 +      .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
        .ahb_buf_size = SZ_1K,
        .quirks = 0,
        .little_endian = false,
@@@ -244,7 -246,6 +257,7 @@@ static const struct fsl_qspi_devtype_da
        .rxfifo = SZ_128,
        .txfifo = SZ_64,
        .ahb_buf_size = SZ_1K,
 +      .invalid_mstrid = 0x0,
        .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_BASE_INTERNAL,
        .little_endian = true,
  };
@@@ -287,6 -288,11 +300,11 @@@ static inline int needs_amba_base_offse
        return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL);
  }
  
+ static inline int needs_tdh_setting(struct fsl_qspi *q)
+ {
+       return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
+ }
+ 
  /*
   * An IC bug makes it necessary to rearrange the 32-bit data.
   * Later chips, such as IMX6SLX, have fixed this bug.
@@@ -627,7 -633,6 +645,7 @@@ static int fsl_qspi_exec_op(struct spi_
        void __iomem *base = q->iobase;
        u32 addr_offset = 0;
        int err = 0;
 +      int invalid_mstrid = q->devtype_data->invalid_mstrid;
  
        mutex_lock(&q->lock);
  
@@@ -651,10 -656,6 +669,10 @@@
        qspi_writel(q, QUADSPI_SPTRCLR_BFPTRC | QUADSPI_SPTRCLR_IPPTRC,
                    base + QUADSPI_SPTRCLR);
  
 +      qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF0CR);
 +      qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF1CR);
 +      qspi_writel(q, invalid_mstrid, base + QUADSPI_BUF2CR);
 +
        fsl_qspi_prepare_lut(q, op);
  
        /*
@@@ -727,6 -728,16 +745,16 @@@ static int fsl_qspi_default_setup(struc
        qspi_writel(q, QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
                    base + QUADSPI_MCR);
  
+       /*
+        * Previous boot stages (BootROM, bootloader) might have used DDR
+        * mode and did not clear the TDH bits. As we currently use SDR mode
+        * only, clear the TDH bits if necessary.
+        */
+       if (needs_tdh_setting(q))
+               qspi_writel(q, qspi_readl(q, base + QUADSPI_FLSHCR) &
+                           ~QUADSPI_FLSHCR_TDH_MASK,
+                           base + QUADSPI_FLSHCR);
+ 
        reg = qspi_readl(q, base + QUADSPI_SMPR);
        qspi_writel(q, reg & ~(QUADSPI_SMPR_FSDLY_MASK
                        | QUADSPI_SMPR_FSPHS_MASK

diff --combined drivers/spi/spi-gpio.c
index 42f4d82e9c5ab42569a1d8af46e4e7801f59d924,f9c5bbb747142559be6700281dc56b958179a27b..7ceb0ba27b755ce2b7250798b7b37c33c9d60b92
--- 1/drivers/spi/spi-gpio.c
--- 2/drivers/spi/spi-gpio.c
+++ b/drivers/spi/spi-gpio.c
@@@ -362,16 -362,21 +362,18 @@@ static int spi_gpio_probe(struct platfo
        struct spi_gpio                 *spi_gpio;
        struct device                   *dev = &pdev->dev;
        struct spi_bitbang              *bb;
 -      const struct of_device_id       *of_id;
 -
 -      of_id = of_match_device(spi_gpio_dt_ids, &pdev->dev);
  
        master = spi_alloc_master(dev, sizeof(*spi_gpio));
        if (!master)
                return -ENOMEM;
  
        status = devm_add_action_or_reset(&pdev->dev, spi_gpio_put, master);
-       if (status)
+       if (status) {
+               spi_master_put(master);
                return status;
+       }
  
 -      if (of_id)
 +      if (pdev->dev.of_node)
                status = spi_gpio_probe_dt(pdev, master);
        else
                status = spi_gpio_probe_pdata(pdev, master);

diff --combined drivers/spi/spi-mxic.c
index 409bfa1636470f39f1755b6088167784e25912aa,a736fdf4711965e5c0418dfa8e9ccee2d079d962..69491f3a515da788a6af8b64fa3b07b106297b63
--- 1/drivers/spi/spi-mxic.c
--- 2/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@@ -145,8 -145,8 +145,8 @@@
  #define LWR_SUSP_CTRL_EN      BIT(31)
  
  #define DMAS_CTRL             0x9c
- #define DMAS_CTRL_DIR_READ    BIT(31)
- #define DMAS_CTRL_EN          BIT(30)
+ #define DMAS_CTRL_EN          BIT(31)
+ #define DMAS_CTRL_DIR_READ    BIT(30)
  
  #define DATA_STROB            0xa0
  #define DATA_STROB_EDO_EN     BIT(2)
@@@ -275,7 -275,7 +275,7 @@@ static void mxic_spi_hw_init(struct mxi
        writel(0, mxic->regs + HC_EN);
        writel(0, mxic->regs + LRD_CFG);
        writel(0, mxic->regs + LRD_CTRL);
-       writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NAND) |
+       writel(HC_CFG_NIO(1) | HC_CFG_TYPE(0, HC_CFG_TYPE_SPI_NOR) |
               HC_CFG_SLV_ACT(0) | HC_CFG_MAN_CS_EN | HC_CFG_IDLE_SIO_LVL(1),
               mxic->regs + HC_CFG);
  }
@@@ -346,7 -346,7 +346,7 @@@ static bool mxic_spi_mem_supports_op(st
        if (op->addr.nbytes > 7)
                return false;
  
 -      return true;
 +      return spi_mem_default_supports_op(mem, op);
  }
  
  static int mxic_spi_mem_exec_op(struct spi_mem *mem,