riscv: dts: starfive: add PCIe dts configuration for JH7110

Add PCIe dts configuraion for JH7110 SoC platform. The Star64 only has
one exposed PCIe port, so only the Mars and VisionFive 2 get two
enabled.

Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Hal Feng <[email protected]>
[conor: squash in star64's single exposed port]
Signed-off-by: Conor Dooley <[email protected]>

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 37b4c294ffcc53a3041a288ac5386b5bbd250801..20bc8c03b8215c3fe5184637d3ec46a6c8c7661b 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -294,6 +294,20 @@
        status = "okay";
 };
 
+&pcie0 {
+       perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>;
+       phys = <&pciephy0>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_pins>;
+};
+
+&pcie1 {
+       perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+       phys = <&pciephy1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_pins>;
+};
+
 &pwmdac {
        pinctrl-names = "default";
        pinctrl-0 = <&pwmdac_pins>;
@@ -473,6 +487,54 @@
                };
        };
 
+       pcie0_pins: pcie0-0 {
+               clkreq-pins {
+                       pinmux = <GPIOMUX(27, GPOUT_LOW,
+                                             GPOEN_DISABLE,
+                                             GPI_NONE)>;
+                       bias-pull-down;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               wake-pins {
+                       pinmux = <GPIOMUX(32, GPOUT_LOW,
+                                             GPOEN_DISABLE,
+                                             GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       pcie1_pins: pcie1-0 {
+               clkreq-pins {
+                       pinmux = <GPIOMUX(29, GPOUT_LOW,
+                                             GPOEN_DISABLE,
+                                             GPI_NONE)>;
+                       bias-pull-down;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               wake-pins {
+                       pinmux = <GPIOMUX(21, GPOUT_LOW,
+                                     GPOEN_DISABLE,
+                                             GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
        pwmdac_pins: pwmdac-0 {
                pwmdac-pins {
                        pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT,

diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
index fa0eac78e0ba6ed55a458c6c231ae7cc8e6f928a..5cb9e99e1dacd52134bfb2345111881ba0ac0b59 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
@@ -17,6 +17,13 @@
        assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
 };
 
+&pcie0 {
+       status = "okay";
+};
+
+&pcie1 {
+       status = "okay";
+};
 
 &phy0 {
        motorcomm,tx-clk-adj-enabled;

diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 2d41f18e035933638a76b34c45544bdfe77f7fce..b720cdd15ed6e806a772935bfcb45d7b29756625 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -39,6 +39,10 @@
        };
 };
 
+&pcie1 {
+       status = "okay";
+};
+
 &phy0 {
        rx-internal-delay-ps = <1900>;
        tx-internal-delay-ps = <1500>;

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 9d70f21c86fc6e56e849a0efab63329c87e32e24..18f38fc790a4d1b7d53910473e7f0f488e504a56 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -32,3 +32,11 @@
 &mmc0 {
        non-removable;
 };
+
+&pcie0 {
+       status = "okay";
+};
+
+&pcie1 {
+       status = "okay";
+};

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 18047195c600bdca0f98ac64337d79e91ce202ab..5ac70759e0ab9e0f1dde20a3df0a480037a4b81c 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -1214,5 +1214,91 @@
                        #reset-cells = <1>;
                        power-domains = <&pwrc JH7110_PD_VOUT>;
                };
+
+               pcie0: pcie@940000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       reg = <0x9 0x40000000 0x0 0x1000000>,
+                             <0x0 0x2b000000 0x0 0x100000>;
+                       reg-names = "cfg", "apb";
+                       linux,pci-domain = <0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+                       interrupts = <56>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
+                       msi-controller;
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon>;
+                       bus-range = <0x0 0xff>;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE0_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc0: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie1: pcie@9c0000000 {
+                       compatible = "starfive,jh7110-pcie";
+                       reg = <0x9 0xc0000000 0x0 0x1000000>,
+                             <0x0 0x2c000000 0x0 0x100000>;
+                       reg-names = "cfg", "apb";
+                       linux,pci-domain = <1>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+                                <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+                       interrupts = <57>;
+                       interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+                       interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
+                                       <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
+                                       <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
+                                       <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
+                       msi-controller;
+                       device_type = "pci";
+                       starfive,stg-syscon = <&stg_syscon>;
+                       bus-range = <0x0 0xff>;
+                       clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+                       clock-names = "noc", "tl", "axi_mst0", "apb";
+                       resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
+                                <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
+                                <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+                                <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+                                <&stgcrg JH7110_STGRST_PCIE1_APB>;
+                       reset-names = "mst0", "slv0", "slv", "brg",
+                                     "core", "apb";
+                       status = "disabled";
+
+                       pcie_intc1: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
        };
 };