Merge tag 'coresight-next-v5.16.v3' of gitolite.kernel.org:pub/scm/linux/kernel/git...

Mathieu writes:

Coresight changes for v5.16

- A new option to make coresight cpu-debug capabilities available as early
as possible in the kernel boot process.

- Make trace sessions more enduring by coping with scenarios where events
are scheduled on CPUs that can't reach the selected sink.

- A set of improvement to make the TMC-ETR driver more efficient.

- Enhancements to the TRBE driver to correct several errata.

- An enhancement to make the AXI burts size configurable for TMC devices
that can't work with the default value.

- A fix in the CTI module to use the correct device when calling
pm_runtime_put()

- The addition of the Kryo-5xx device to the list of support ETMs.

Signed-off-by: Mathieu Poirier <[email protected]>
* tag 'coresight-next-v5.16.v3' of gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux: (39 commits)
  arm64: errata: Enable TRBE workaround for write to out-of-range address
  arm64: errata: Enable workaround for TRBE overwrite in FILL mode
  coresight: trbe: Work around write to out of range
  coresight: trbe: Make sure we have enough space
  coresight: trbe: Add a helper to determine the minimum buffer size
  coresight: trbe: Workaround TRBE errata overwrite in FILL mode
  coresight: trbe: Add infrastructure for Errata handling
  coresight: trbe: Allow driver to choose a different alignment
  coresight: trbe: Decouple buffer base from the hardware base
  coresight: trbe: Add a helper to pad a given buffer area
  coresight: trbe: Add a helper to calculate the trace generated
  coresight: trbe: Defer the probe on offline CPUs
  coresight: trbe: Fix incorrect access of the sink specific data
  coresight: etm4x: Add ETM PID for Kryo-5XX
  coresight: trbe: Prohibit trace before disabling TRBE
  coresight: trbe: End the AUX handle on truncation
  coresight: trbe: Do not truncate buffer on IRQ
  coresight: trbe: Fix handling of spurious interrupts
  coresight: trbe: irq handler: Do not disable TRBE if no action is needed
  coresight: trbe: Unify the enabling sequence
  ...

diff --combined arch/arm64/Kconfig
index fee914c716aa262d12060cce3980471d510af283,9c33ce54509ac2553c8c779776937890754e3440..ebb77b89463038146915a4114b9bfa64d424b1a3
--- 1/arch/arm64/Kconfig
--- 2/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@@ -666,6 -666,117 +666,117 @@@ config ARM64_ERRATUM_150841
  
          If unsure, say Y.
  
+ config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       bool
+ 
+ config ARM64_ERRATUM_2119858
+       bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"
+       default y
+       depends on CORESIGHT_TRBE
+       select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       help
+         This option adds the workaround for ARM Cortex-A710 erratum 2119858.
+ 
+         Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace
+         data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
+         the event of a WRAP event.
+ 
+         Work around the issue by always making sure we move the TRBPTR_EL1 by
+         256 bytes before enabling the buffer and filling the first 256 bytes of
+         the buffer with ETM ignore packets upon disabling.
+ 
+         If unsure, say Y.
+ 
+ config ARM64_ERRATUM_2139208
+       bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
+       default y
+       depends on CORESIGHT_TRBE
+       select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
+       help
+         This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
+ 
+         Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
+         data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
+         the event of a WRAP event.
+ 
+         Work around the issue by always making sure we move the TRBPTR_EL1 by
+         256 bytes before enabling the buffer and filling the first 256 bytes of
+         the buffer with ETM ignore packets upon disabling.
+ 
+         If unsure, say Y.
+ 
+ config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
+       bool
+ 
+ config ARM64_ERRATUM_2054223
+       bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
+       default y
+       select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
+       help
+         Enable workaround for ARM Cortex-A710 erratum 2054223
+ 
+         Affected cores may fail to flush the trace data on a TSB instruction, when
+         the PE is in trace prohibited state. This will cause losing a few bytes
+         of the trace cached.
+ 
+         Workaround is to issue two TSB consecutively on affected cores.
+ 
+         If unsure, say Y.
+ 
+ config ARM64_ERRATUM_2067961
+       bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
+       default y
+       select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
+       help
+         Enable workaround for ARM Neoverse-N2 erratum 2067961
+ 
+         Affected cores may fail to flush the trace data on a TSB instruction, when
+         the PE is in trace prohibited state. This will cause losing a few bytes
+         of the trace cached.
+ 
+         Workaround is to issue two TSB consecutively on affected cores.
+ 
+         If unsure, say Y.
+ 
+ config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
+       bool
+ 
+ config ARM64_ERRATUM_2253138
+       bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
+       depends on CORESIGHT_TRBE
+       default y
+       select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
+       help
+         This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
+ 
+         Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
+         for TRBE. Under some conditions, the TRBE might generate a write to the next
+         virtually addressed page following the last page of the TRBE address space
+         (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
+ 
+         Work around this in the driver by always making sure that there is a
+         page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
+ 
+         If unsure, say Y.
+ 
+ config ARM64_ERRATUM_2224489
+       bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"
+       depends on CORESIGHT_TRBE
+       default y
+       select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
+       help
+         This option adds the workaround for ARM Cortex-A710 erratum 2224489.
+ 
+         Affected Cortex-A710 cores might write to an out-of-range address, not reserved
+         for TRBE. Under some conditions, the TRBE might generate a write to the next
+         virtually addressed page following the last page of the TRBE address space
+         (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
+ 
+         Work around this in the driver by always making sure that there is a
+         page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
+ 
+         If unsure, say Y.
+ 
  config CAVIUM_ERRATUM_22375
        bool "Cavium erratum 22375, 24313"
        default y
@@@ -1931,6 -2042,8 +2042,6 @@@ source "drivers/cpufreq/Kconfig
  
  endmenu
  
 -source "drivers/firmware/Kconfig"
 -
  source "drivers/acpi/Kconfig"
  
  source "arch/arm64/kvm/Kconfig"