pwm: axi-pwmgen: Enable FORCE_ALIGN by default

Enable the FORCE_ALIGN flag by default in the AXI PWMGEN driver. This
flag makes the behavior of the PWM output consistent with the
description at the top of the driver file.

    * Limitations:
    * - The writes to registers for period and duty are shadowed until
    *   LOAD_CONFIG is written to AXI_PWMGEN_REG_RSTN, at which point
    *   they take effect.
    * - Writing LOAD_CONFIG also has the effect of re-synchronizing all
    *   enabled channels, which could cause glitching on other channels. It
    *   is therefore expected that channels are assigned harmonic periods
    *   and all have a single user coordinating this.

Without this flag, the PWM output does not change until the period of
all PWM output channels has run out, which makes the PWM impossible to
use in some cases because it takes too long to change the output.

Signed-off-by: David Lechner <[email protected]>
Reviewed-by: Nuno Sa <[email protected]>
Link: https://lore.kernel.org/r/20241009-pwm-axi-pwmgen-enable-force_align-v1-2-5d6ad8cbf5b4@baylibre.com
Signed-off-by: Uwe Kleine-König <[email protected]>

diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c
index e1ddeaa4998b9f66335f776f85883f4db47ad4f0..4259a0db9ff45808eecae28680473292d165d1f6 100644 (file)
--- a/drivers/pwm/pwm-axi-pwmgen.c
+++ b/drivers/pwm/pwm-axi-pwmgen.c
@@ -37,6 +37,8 @@
 #define   AXI_PWMGEN_REG_RSTN_LOAD_CONFIG      BIT(1)
 #define   AXI_PWMGEN_REG_RSTN_RESET            BIT(0)
 #define AXI_PWMGEN_REG_NPWM            0x14
+#define AXI_PWMGEN_REG_CONFIG          0x18
+#define   AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN    BIT(1)
 #define AXI_PWMGEN_CHX_PERIOD(ch)      (0x40 + (4 * (ch)))
 #define AXI_PWMGEN_CHX_DUTY(ch)                (0x80 + (4 * (ch)))
 #define AXI_PWMGEN_CHX_OFFSET(ch)      (0xC0 + (4 * (ch)))
@@ -227,6 +229,16 @@ static int axi_pwmgen_setup(struct regmap *regmap, struct device *dev)
        if (ret)
                return ret;
 
+       /*
+        * Enable force align so that changes to PWM period and duty cycle take
+        * effect immediately. Otherwise, the effect of the change is delayed
+        * until the period of all channels run out, which can be long after the
+        * apply function returns.
+        */
+       ret = regmap_set_bits(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_REG_CONFIG_FORCE_ALIGN);
+       if (ret)
+               return ret;
+
        ret = regmap_read(regmap, AXI_PWMGEN_REG_NPWM, &val);
        if (ret)
                return ret;