]> Git Repo - J-linux.git/commitdiff
riscv: Fix default misaligned access trap
authorCharlie Jenkins <[email protected]>
Fri, 8 Nov 2024 23:47:36 +0000 (15:47 -0800)
committerPalmer Dabbelt <[email protected]>
Tue, 12 Nov 2024 22:45:26 +0000 (14:45 -0800)
Commit d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses
supported") removed the default handlers for handle_misaligned_load()
and handle_misaligned_store(). When the kernel is compiled without
RISCV_SCALAR_MISALIGNED, these handlers are never defined, causing
compilation errors.

Signed-off-by: Charlie Jenkins <[email protected]>
Fixes: d1703dc7bc8e ("RISC-V: Detect unaligned vector accesses supported")
Reviewed-by: Jesse Taube <[email protected]>
Link: https://lore.kernel.org/r/20241108-fix_handle_misaligned_load-v2-1-91d547ce64db@rivosinc.com
Signed-off-by: Palmer Dabbelt <[email protected]>
arch/riscv/include/asm/entry-common.h

index 7b32d2b08bb669790ac2567b4a977367747d9401..b28ccc6cdeea49fc32290caa02361def08600bf4 100644 (file)
@@ -25,7 +25,19 @@ static inline void arch_exit_to_user_mode_prepare(struct pt_regs *regs,
 void handle_page_fault(struct pt_regs *regs);
 void handle_break(struct pt_regs *regs);
 
+#ifdef CONFIG_RISCV_MISALIGNED
 int handle_misaligned_load(struct pt_regs *regs);
 int handle_misaligned_store(struct pt_regs *regs);
+#else
+static inline int handle_misaligned_load(struct pt_regs *regs)
+{
+       return -1;
+}
+
+static inline int handle_misaligned_store(struct pt_regs *regs)
+{
+       return -1;
+}
+#endif
 
 #endif /* _ASM_RISCV_ENTRY_COMMON_H */
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