Merge branches 'clk-mediatek', 'clk-trace', 'clk-qcom' and 'clk-microchip' into clk...

 - Tracepoints for clk_rate_request structures

* clk-mediatek:
  clk: mediatek: fix dependency of MT7986 ADC clocks
  clk: mediatek: Change PLL register API for MT8186
  clk: mediatek: Add new clock driver to handle FHCTL hardware
  dt-bindings: clock: mediatek: Add new bindings of MediaTek frequency hopping
  clk: mediatek: Export PLL operations symbols
  clk: mediatek: mt8186-topckgen: Add GPU clock mux notifier
  clk: mediatek: mt8186-mfg: Propagate rate changes to parent
  clk: mediatek: mt8195-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: mt8192: Drop flags for main/univpll fixed factors
  clk: mediatek: mt6795-topckgen: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8173: Drop flags for main/sys/univpll fixed factors
  clk: mediatek: mt8183: Drop flags for sys/univpll fixed factors
  clk: mediatek: mt8183: Compress top_divs array entries
  clk: mediatek: mt8186-topckgen: Drop flags for main/univpll fixed factors
  clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks

* clk-trace:
  clk: Add trace events for rate requests
  clk: Store clk_core for clk_rate_request

* clk-qcom: (69 commits)
  clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
  clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: mmcc-msm8974: move clock parent tables down
  clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
  clk: qcom: gcc-msm8974: move clock parent tables down
  clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
  dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
  dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
  clk: qcom: gcc-ipq4019: switch to devm_clk_notifier_register
  clk: qcom: rpmh: remove usage of platform name
  clk: qcom: rpmh: rename VRM clock data
  clk: qcom: rpmh: rename ARC clock data
  clk: qcom: rpmh: support separate symbol name for the RPMH clocks
  clk: qcom: rpmh: remove platform names from BCM clocks
  clk: qcom: rpmh: drop all _ao names
  clk: qcom: rpmh: reuse common duplicate clocks
  clk: qcom: rpmh: group clock definitions together
  clk: qcom: rpm: drop the platform from clock definitions
  clk: qcom: rpm: drop the _clk suffix completely
  ...

* clk-microchip:
  clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
  clk: microchip: check for null return of devm_kzalloc()

diff --combined drivers/clk/clk.c
index 57b83665e5c3a426a03ea542f436d68c5d0741b8,c3c3f8c072588d2a3581e7af7cad80115ffb081d,f0288499866a8bccfe7e020bb6b76ec9dda6c266,c3c3f8c072588d2a3581e7af7cad80115ffb081d,c3c3f8c072588d2a3581e7af7cad80115ffb081d..e62552a75f0890ab3b99fbcd372d0daa54d66250
--- 1/drivers/clk/clk.c
--- 2/drivers/clk/clk.c
--- 3/drivers/clk/clk.c
--- 4/drivers/clk/clk.c
--- 5/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@@@@@ -603,10 -603,10 -603,15 -603,10 -603,10 +603,15 @@@@@@ int clk_mux_determine_rate_flags(struc
                        }
     
                        clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
++ ++
++ ++                   trace_clk_rate_request_start(&parent_req);
++ ++
                        ret = clk_core_round_rate_nolock(parent, &parent_req);
                        if (ret)
                                return ret;
     
++ ++                   trace_clk_rate_request_done(&parent_req);
++ ++
                        best = parent_req.rate;
                } else if (parent) {
                        best = clk_core_get_rate_nolock(parent);
@@@@@@ -630,10 -630,10 -635,15 -630,10 -630,10 +635,15 @@@@@@
                        struct clk_rate_request parent_req;
     
                        clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
++ ++
++ ++                   trace_clk_rate_request_start(&parent_req);
++ ++
                        ret = clk_core_round_rate_nolock(parent, &parent_req);
                        if (ret)
                                continue;
     
++ ++                   trace_clk_rate_request_done(&parent_req);
++ ++
                        parent_rate = parent_req.rate;
                } else {
                        parent_rate = clk_core_get_rate_nolock(parent);
@@@@@@ -1459,15 -1459,11 -1469,12 -1459,11 -1459,11 +1469,16 @@@@@@ static void clk_core_init_rate_req(stru
     {
        struct clk_core *parent;
     
 ----   if (WARN_ON(!core || !req))
 ++++   if (WARN_ON(!req))
                return;
     
        memset(req, 0, sizeof(*req));
 ++++   req->max_rate = ULONG_MAX;
  +  
 ++++   if (!core)
 ++++           return;
 + ++
++ ++   req->core = core;
        req->rate = rate;
        clk_core_get_boundaries(core, &req->min_rate, &req->max_rate);
     
@@@@@@ -1550,10 -1546,10 -1557,15 -1546,10 -1546,10 +1561,15 @@@@@@ static int clk_core_round_rate_nolock(s
                struct clk_rate_request parent_req;
     
                clk_core_forward_rate_req(core, req, core->parent, &parent_req, req->rate);
++ ++
++ ++           trace_clk_rate_request_start(&parent_req);
++ ++
                ret = clk_core_round_rate_nolock(core->parent, &parent_req);
                if (ret)
                        return ret;
     
++ ++           trace_clk_rate_request_done(&parent_req);
++ ++
                req->best_parent_rate = parent_req.rate;
                req->rate = parent_req.rate;
     
@@@@@@ -1604,10 -1600,10 -1616,14 -1600,10 -1600,10 +1620,14 @@@@@@ unsigned long clk_hw_round_rate(struct 
     
        clk_core_init_rate_req(hw->core, &req, rate);
     
++ ++   trace_clk_rate_request_start(&req);
++ ++
        ret = clk_core_round_rate_nolock(hw->core, &req);
        if (ret)
                return 0;
     
++ ++   trace_clk_rate_request_done(&req);
++ ++
        return req.rate;
     }
     EXPORT_SYMBOL_GPL(clk_hw_round_rate);
@@@@@@ -1636,8 -1632,8 -1652,12 -1632,8 -1632,8 +1656,12 @@@@@@ long clk_round_rate(struct clk *clk, un
     
        clk_core_init_rate_req(clk->core, &req, rate);
     
++ ++   trace_clk_rate_request_start(&req);
++ ++
        ret = clk_core_round_rate_nolock(clk->core, &req);
     
++ ++   trace_clk_rate_request_done(&req);
++ ++
        if (clk->exclusive_count)
                clk_core_rate_protect(clk->core);
     
@@@@@@ -2129,10 -2125,10 -2149,14 -2125,10 -2125,10 +2153,14 @@@@@@ static struct clk_core *clk_calc_new_ra
     
                clk_core_init_rate_req(core, &req, rate);
     
++ ++           trace_clk_rate_request_start(&req);
++ ++
                ret = clk_core_determine_round_nolock(core, &req);
                if (ret < 0)
                        return NULL;
     
++ ++           trace_clk_rate_request_done(&req);
++ ++
                best_parent_rate = req.best_parent_rate;
                new_rate = req.rate;
                parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
@@@@@@ -2328,8 -2324,8 -2352,12 -2324,8 -2324,8 +2356,12 @@@@@@ static unsigned long clk_core_req_round
     
        clk_core_init_rate_req(core, &req, req_rate);
     
++ ++   trace_clk_rate_request_start(&req);
++ ++
        ret = clk_core_round_rate_nolock(core, &req);
     
++ ++   trace_clk_rate_request_done(&req);
++ ++
        /* restore the protection */
        clk_core_rate_restore_protect(core, cnt);
     

diff --combined drivers/clk/mediatek/clk-mt8195-topckgen.c
index 1e016329c1d23e19e71aa013a525e7978f4fb757,a243441782ae4552fe8c3a7daa0fd576e337bd82,8cbab5ca2e581dad2a183e6b433736fee8542ee9,8cbab5ca2e581dad2a183e6b433736fee8542ee9,8cbab5ca2e581dad2a183e6b433736fee8542ee9..93e96419da666a2bcc6980800d75ab0ff583ff52
--- 1/drivers/clk/mediatek/clk-mt8195-topckgen.c
--- 2/drivers/clk/mediatek/clk-mt8195-topckgen.c
--- 3/drivers/clk/mediatek/clk-mt8195-topckgen.c
--- 4/drivers/clk/mediatek/clk-mt8195-topckgen.c
--- 5/drivers/clk/mediatek/clk-mt8195-topckgen.c
+++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
@@@@@@ -35,45 -35,45 -35,45 -35,45 -35,45 +35,45 @@@@@@ static const struct mtk_fixed_factor to
        FACTOR(CLK_TOP_IN_DGI_D4, "in_dgi_d4", "in_dgi", 1, 4),
        FACTOR(CLK_TOP_IN_DGI_D6, "in_dgi_d6", "in_dgi", 1, 6),
        FACTOR(CLK_TOP_IN_DGI_D8, "in_dgi_d8", "in_dgi", 1, 8),
- ---   FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
- ---   FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
- ---   FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2),
- ---   FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4),
- ---   FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8),
- ---   FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
- ---   FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
- ---   FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
- ---   FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8),
- ---   FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
- ---   FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2),
- ---   FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4),
- ---   FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8),
- ---   FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
- ---   FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
- ---   FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
- ---   FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8),
- ---   FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
- ---   FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
- ---   FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
- ---   FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
- ---   FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2),
- ---   FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4),
- ---   FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8),
- ---   FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
- ---   FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
- ---   FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
- ---   FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
- ---   FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
- ---   FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2),
- ---   FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4),
- ---   FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8),
- ---   FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16),
- ---   FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
- ---   FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
- ---   FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
- ---   FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
- ---   FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
- ---   FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll_d4", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll_d4", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll_d4", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll_d5", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll_d6", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll_d6", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll_d6", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll_d7", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll_d4", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll_d4", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll_d4", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll_d6", 1, 2, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll_d6", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll_d6", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll_d6", 1, 16, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16, 0),
+ +++   FACTOR_FLAGS(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32, 0),
        FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
        FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
        FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
@@@@@@ -1270,10 -1270,8 -1270,8 -1270,8 -1270,8 +1270,10 @@@@@@ static int clk_mt8195_topck_probe(struc
        hw = devm_clk_hw_register_mux(&pdev->dev, "mfg_ck_fast_ref", mfg_fast_parents,
                                      ARRAY_SIZE(mfg_fast_parents), CLK_SET_RATE_PARENT,
                                      (base + 0x250), 8, 1, 0, &mt8195_clk_lock);
 ----   if (IS_ERR(hw))
 ++++   if (IS_ERR(hw)) {
 ++++           r = PTR_ERR(hw);
                goto unregister_muxes;
 ++++   }
        top_clk_data->hws[CLK_TOP_MFG_CK_FAST_REF] = hw;
     
        r = clk_mt8195_reg_mfg_mux_notifier(&pdev->dev,

diff --combined drivers/clk/qcom/gdsc.c
index 0f21a8a767ac198b683904bfc501899c3a5a7528,7cf5e130e92fb59f8d99759ebe656b7bceacf5a1,7cf5e130e92fb59f8d99759ebe656b7bceacf5a1,0cce12ff4c4bce212745cfb8fb86471637043cd2,7cf5e130e92fb59f8d99759ebe656b7bceacf5a1..9e4d6ce891aad7894af19e63540ea485664bc65d
--- 1/drivers/clk/qcom/gdsc.c
--- 2/drivers/clk/qcom/gdsc.c
--- 3/drivers/clk/qcom/gdsc.c
--- 4/drivers/clk/qcom/gdsc.c
--- 5/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@@@@@ -11,6 -11,7 -11,7 -11,7 -11,7 +11,6 @@@@@@
     #include <linux/kernel.h>
     #include <linux/ktime.h>
     #include <linux/pm_domain.h>
 ----#include <linux/pm_runtime.h>
     #include <linux/regmap.h>
     #include <linux/regulator/consumer.h>
     #include <linux/reset-controller.h>
@@@@@@ -46,6 -47,6 -47,6 -47,7 -47,6 +46,7 @@@@@@
     #define RETAIN_MEM         BIT(14)
     #define RETAIN_PERIPH              BIT(13)
     
+++ +#define STATUS_POLL_TIMEOUT_US     1500
     #define TIMEOUT_US         500
     
     #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
@@@@@@ -55,6 -56,22 -56,22 -57,22 -56,22 +56,6 @@@@@@ enum gdsc_status 
        GDSC_ON
     };
     
 ----static int gdsc_pm_runtime_get(struct gdsc *sc)
 ----{
 ----   if (!sc->dev)
 ----           return 0;
 ----
 ----   return pm_runtime_resume_and_get(sc->dev);
 ----}
 ----
 ----static int gdsc_pm_runtime_put(struct gdsc *sc)
 ----{
 ----   if (!sc->dev)
 ----           return 0;
 ----
 ----   return pm_runtime_put_sync(sc->dev);
 ----}
 ----
     /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
     static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
     {
@@@@@@ -107,7 -124,7 -124,7 -125,7 -124,7 +108,7 @@@@@@ static int gdsc_poll_status(struct gds
        do {
                if (gdsc_check_status(sc, status))
                        return 0;
--- -   } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
+++ +   } while (ktime_us_delta(ktime_get(), start) < STATUS_POLL_TIMEOUT_US);
     
        if (gdsc_check_status(sc, status))
                return 0;
@@@@@@ -254,9 -271,8 -271,8 -272,8 -271,8 +255,9 @@@@@@ static void gdsc_retain_ff_on(struct gd
        regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
     }
     
 ----static int _gdsc_enable(struct gdsc *sc)
 ++++static int gdsc_enable(struct generic_pm_domain *domain)
     {
 ++++   struct gdsc *sc = domain_to_gdsc(domain);
        int ret;
     
        if (sc->pwrsts == PWRSTS_ON)
@@@@@@ -312,11 -328,22 -328,22 -329,22 -328,22 +313,11 @@@@@@
        return 0;
     }
     
 ----static int gdsc_enable(struct generic_pm_domain *domain)
 ++++static int gdsc_disable(struct generic_pm_domain *domain)
     {
        struct gdsc *sc = domain_to_gdsc(domain);
        int ret;
     
 ----   ret = gdsc_pm_runtime_get(sc);
 ----   if (ret)
 ----           return ret;
 ----
 ----   return _gdsc_enable(sc);
 ----}
 ----
 ----static int _gdsc_disable(struct gdsc *sc)
 ----{
 ----   int ret;
 ----
        if (sc->pwrsts == PWRSTS_ON)
                return gdsc_assert_reset(sc);
     
@@@@@@ -361,6 -388,18 -388,18 -389,18 -388,18 +362,6 @@@@@@
        return 0;
     }
     
 ----static int gdsc_disable(struct generic_pm_domain *domain)
 ----{
 ----   struct gdsc *sc = domain_to_gdsc(domain);
 ----   int ret;
 ----
 ----   ret = _gdsc_disable(sc);
 ----
 ----   gdsc_pm_runtime_put(sc);
 ----
 ----   return ret;
 ----}
 ----
     static int gdsc_init(struct gdsc *sc)
     {
        u32 mask, val;
@@@@@@ -408,6 -447,11 -447,11 -448,11 -447,11 +409,6 @@@@@@
                                return ret;
                }
     
 ----           /* ...and the power-domain */
 ----           ret = gdsc_pm_runtime_get(sc);
 ----           if (ret)
 ----                   goto err_disable_supply;
 ----
                /*
                 * Votable GDSCs can be ON due to Vote from other masters.
                 * If a Votable GDSC is ON, make sure we have a Vote.
@@@@@@ -415,14 -459,14 -459,14 -460,14 -459,14 +416,14 @@@@@@
                if (sc->flags & VOTABLE) {
                        ret = gdsc_update_collapse_bit(sc, false);
                        if (ret)
 ----                           goto err_put_rpm;
 ++++                           goto err_disable_supply;
                }
     
                /* Turn on HW trigger mode if supported */
                if (sc->flags & HW_CTRL) {
                        ret = gdsc_hwctrl(sc, true);
                        if (ret < 0)
 ----                           goto err_put_rpm;
 ++++                           goto err_disable_supply;
                }
     
                /*
@@@@@@ -452,10 -496,13 -496,13 -497,13 -496,13 +453,10 @@@@@@
     
        ret = pm_genpd_init(&sc->pd, NULL, !on);
        if (ret)
 ----           goto err_put_rpm;
 ++++           goto err_disable_supply;
     
        return 0;
     
 ----err_put_rpm:
 ----   if (on)
 ----           gdsc_pm_runtime_put(sc);
     err_disable_supply:
        if (on && sc->rsupply)
                regulator_disable(sc->rsupply);
@@@@@@ -494,6 -541,8 -541,8 -542,8 -541,8 +495,6 @@@@@@ int gdsc_register(struct gdsc_desc *des
        for (i = 0; i < num; i++) {
                if (!scs[i])
                        continue;
 ----           if (pm_runtime_enabled(dev))
 ----                   scs[i]->dev = dev;
                scs[i]->regmap = regmap;
                scs[i]->rcdev = rcdev;
                ret = gdsc_init(scs[i]);