cxl/pci: Check dport->regs.rcd_pcie_cap availability before accessing

RCD Upstream Port's PCI Express Capability is a component registers
block stored in RCD Upstream Port RCRB. CXL PCI driver helps to map it
during the RCD probing, but mapping failure is allowed for component
registers blocks in CXL PCI driver.

dport->regs.rcd_pcie_cap is used to store the virtual address of the RCD
Upstream Port's PCI Express Capability, add a dport->regs.rcd_pcie_cap
checking in rcd_pcie_cap_emit() just in case user accesses a invalid
address via RCD sysfs.

Fixes: c5eaec79fa43 ("cxl/pci: Add sysfs attribute for CXL 1.1 device link status")
Signed-off-by: Li Ming <[email protected]>
Reviewed-by: Alison Schofield <[email protected]>
Reviewed-by: Dan Williams <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Dave Jiang <[email protected]>

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 26ab06c9deffb2bdb27758fca96eb2ed8ea1cc80..6d94ff4a4f1a62817538ccde3d123714bd8d4a8b 100644 (file)
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -836,6 +836,9 @@ static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size
        if (!root_dev)
                return -ENXIO;
 
+       if (!dport->regs.rcd_pcie_cap)
+               return -ENXIO;
+
        guard(device)(root_dev);
        if (!root_dev->driver)
                return -ENXIO;