arm64: dts: broadcom: Fix L2 linesize for Raspberry Pi 5

Set the cache-line-size parameter of the L2 cache for each core to the
correct value of 64 bytes.

Previously, the L2 cache line size was incorrectly set to 128 bytes
for the Broadcom BCM2712. This causes validation tests for the
Performance Application Programming Interface (PAPI) tool to fail as
they depend on sysfs accurately reporting cache line sizes.

The correct value of 64 bytes is stated in the official documentation of
the ARM Cortex A-72, which is linked in the comments of
arm64/boot/dts/broadcom/bcm2712.dtsi as the source for cache-line-size.

Fixes: faa3381267d0 ("arm64: dts: broadcom: Add minimal support for Raspberry Pi 5")
Signed-off-by: Willow Cunningham <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Florian Fainelli <[email protected]>

diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
index 6e5a984c1d4ea113d220bf5bbad6d35a8e3c83f6..26a29e5e5078d5840525dcb2ef5ff6fd07c26772 100644 (file)
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -67,7 +67,7 @@
                        l2_cache_l0: l2-cache-l0 {
                                compatible = "cache";
                                cache-size = <0x80000>;
-                               cache-line-size = <128>;
+                               cache-line-size = <64>;
                                cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
                                cache-level = <2>;
                                cache-unified;
@@ -91,7 +91,7 @@
                        l2_cache_l1: l2-cache-l1 {
                                compatible = "cache";
                                cache-size = <0x80000>;
-                               cache-line-size = <128>;
+                               cache-line-size = <64>;
                                cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
                                cache-level = <2>;
                                cache-unified;
@@ -115,7 +115,7 @@
                        l2_cache_l2: l2-cache-l2 {
                                compatible = "cache";
                                cache-size = <0x80000>;
-                               cache-line-size = <128>;
+                               cache-line-size = <64>;
                                cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
                                cache-level = <2>;
                                cache-unified;
@@ -139,7 +139,7 @@
                        l2_cache_l3: l2-cache-l3 {
                                compatible = "cache";
                                cache-size = <0x80000>;
-                               cache-line-size = <128>;
+                               cache-line-size = <64>;
                                cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
                                cache-level = <2>;
                                cache-unified;