help
Support for the Marvell PXA SoC.
-----config COMMON_CLK_OXNAS
----- bool "Clock driver for the OXNAS SoC Family"
----- depends on ARCH_OXNAS || COMPILE_TEST
----- select MFD_SYSCON
----- help
----- Support for the OXNAS SoC Family clocks.
-----
config COMMON_CLK_RS9_PCIE
tristate "Clock driver for Renesas 9-series PCIe clock generators"
depends on I2C
This driver supports the SkyWorks Si521xx PCIe clock generator
models Si52144/Si52146/Si52147.
+ ++++config COMMON_CLK_VC3
+ ++++ tristate "Clock driver for Renesas VersaClock 3 devices"
+ ++++ depends on I2C
+ ++++ depends on OF
+ ++++ select REGMAP_I2C
+ ++++ help
+ ++++ This driver supports the Renesas VersaClock 3 programmable clock
+ ++++ generators.
+ ++++
config COMMON_CLK_VC5
tristate "Clock driver for IDT VersaClock 5,6 devices"
depends on I2C
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
-----obj-$(CONFIG_COMMON_CLK_OXNAS) += clk-oxnas.o
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
+ ++++obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
-----#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/slab.h>
i2c_set_clientdata(client, vc5);
vc5->client = client;
- ---- vc5->chip_info = device_get_match_data(&client->dev);
+ ++++ vc5->chip_info = i2c_get_match_data(client);
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of.h>
-----#include <linux/of_platform.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/swab.h>
i2c_set_clientdata(client, vc7);
vc7->client = client;
- ---- vc7->chip_info = device_get_match_data(&client->dev);
+ ++++ vc7->chip_info = i2c_get_match_data(client);
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {
*/
#include <linux/clk-provider.h>
-----#include <linux/of_device.h>
+++++#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-peripherals.h"
#include "clk-dualdiv.h"
#include "clk-regmap.h"
+++ ++#include "meson-clkc-utils.h"
+++ ++
+++ ++#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
static struct clk_regmap xtal_in = {
.data = &(struct clk_regmap_gate_data){
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
/* Array of all clocks registered by this provider */
--- --static struct clk_hw_onecell_data a1_periphs_clks = {
--- -- .hws = {
--- -- [CLKID_XTAL_IN] = &xtal_in.hw,
--- -- [CLKID_FIXPLL_IN] = &fixpll_in.hw,
--- -- [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
--- -- [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
--- -- [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
--- -- [CLKID_SYSPLL_IN] = &syspll_in.hw,
--- -- [CLKID_DDS_IN] = &dds_in.hw,
--- -- [CLKID_SYS] = &sys.hw,
--- -- [CLKID_CLKTREE] = &clktree.hw,
--- -- [CLKID_RESET_CTRL] = &reset_ctrl.hw,
--- -- [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
--- -- [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
--- -- [CLKID_PAD_CTRL] = &pad_ctrl.hw,
--- -- [CLKID_SYS_CTRL] = &sys_ctrl.hw,
--- -- [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
--- -- [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
--- -- [CLKID_SPICC_B] = &spicc_b.hw,
--- -- [CLKID_SPICC_A] = &spicc_a.hw,
--- -- [CLKID_MSR] = &msr.hw,
--- -- [CLKID_AUDIO] = &audio.hw,
--- -- [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
--- -- [CLKID_SARADC_EN] = &saradc_en.hw,
--- -- [CLKID_PWM_EF] = &pwm_ef.hw,
--- -- [CLKID_PWM_CD] = &pwm_cd.hw,
--- -- [CLKID_PWM_AB] = &pwm_ab.hw,
--- -- [CLKID_CEC] = &cec.hw,
--- -- [CLKID_I2C_S] = &i2c_s.hw,
--- -- [CLKID_IR_CTRL] = &ir_ctrl.hw,
--- -- [CLKID_I2C_M_D] = &i2c_m_d.hw,
--- -- [CLKID_I2C_M_C] = &i2c_m_c.hw,
--- -- [CLKID_I2C_M_B] = &i2c_m_b.hw,
--- -- [CLKID_I2C_M_A] = &i2c_m_a.hw,
--- -- [CLKID_ACODEC] = &acodec.hw,
--- -- [CLKID_OTP] = &otp.hw,
--- -- [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
--- -- [CLKID_USB_PHY] = &usb_phy.hw,
--- -- [CLKID_USB_CTRL] = &usb_ctrl.hw,
--- -- [CLKID_SYS_DSPB] = &sys_dspb.hw,
--- -- [CLKID_SYS_DSPA] = &sys_dspa.hw,
--- -- [CLKID_DMA] = &dma.hw,
--- -- [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
--- -- [CLKID_NIC] = &nic.hw,
--- -- [CLKID_GIC] = &gic.hw,
--- -- [CLKID_UART_C] = &uart_c.hw,
--- -- [CLKID_UART_B] = &uart_b.hw,
--- -- [CLKID_UART_A] = &uart_a.hw,
--- -- [CLKID_SYS_PSRAM] = &sys_psram.hw,
--- -- [CLKID_RSA] = &rsa.hw,
--- -- [CLKID_CORESIGHT] = &coresight.hw,
--- -- [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
--- -- [CLKID_AUDIO_VAD] = &audio_vad.hw,
--- -- [CLKID_AXI_DMC] = &axi_dmc.hw,
--- -- [CLKID_AXI_PSRAM] = &axi_psram.hw,
--- -- [CLKID_RAMB] = &ramb.hw,
--- -- [CLKID_RAMA] = &rama.hw,
--- -- [CLKID_AXI_SPIFC] = &axi_spifc.hw,
--- -- [CLKID_AXI_NIC] = &axi_nic.hw,
--- -- [CLKID_AXI_DMA] = &axi_dma.hw,
--- -- [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
--- -- [CLKID_ROM] = &rom.hw,
--- -- [CLKID_PROC_I2C] = &prod_i2c.hw,
--- -- [CLKID_DSPA_SEL] = &dspa_sel.hw,
--- -- [CLKID_DSPB_SEL] = &dspb_sel.hw,
--- -- [CLKID_DSPA_EN] = &dspa_en.hw,
--- -- [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
--- -- [CLKID_DSPB_EN] = &dspb_en.hw,
--- -- [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
--- -- [CLKID_RTC] = &rtc.hw,
--- -- [CLKID_CECA_32K] = &ceca_32k_out.hw,
--- -- [CLKID_CECB_32K] = &cecb_32k_out.hw,
--- -- [CLKID_24M] = &clk_24m.hw,
--- -- [CLKID_12M] = &clk_12m.hw,
--- -- [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
--- -- [CLKID_GEN] = &gen.hw,
--- -- [CLKID_SARADC_SEL] = &saradc_sel.hw,
--- -- [CLKID_SARADC] = &saradc.hw,
--- -- [CLKID_PWM_A] = &pwm_a.hw,
--- -- [CLKID_PWM_B] = &pwm_b.hw,
--- -- [CLKID_PWM_C] = &pwm_c.hw,
--- -- [CLKID_PWM_D] = &pwm_d.hw,
--- -- [CLKID_PWM_E] = &pwm_e.hw,
--- -- [CLKID_PWM_F] = &pwm_f.hw,
--- -- [CLKID_SPICC] = &spicc.hw,
--- -- [CLKID_TS] = &ts.hw,
--- -- [CLKID_SPIFC] = &spifc.hw,
--- -- [CLKID_USB_BUS] = &usb_bus.hw,
--- -- [CLKID_SD_EMMC] = &sd_emmc.hw,
--- -- [CLKID_PSRAM] = &psram.hw,
--- -- [CLKID_DMC] = &dmc.hw,
--- -- [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
--- -- [CLKID_SYS_A_DIV] = &sys_a_div.hw,
--- -- [CLKID_SYS_A] = &sys_a.hw,
--- -- [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
--- -- [CLKID_SYS_B_DIV] = &sys_b_div.hw,
--- -- [CLKID_SYS_B] = &sys_b.hw,
--- -- [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
--- -- [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
--- -- [CLKID_DSPA_A] = &dspa_a.hw,
--- -- [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
--- -- [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
--- -- [CLKID_DSPA_B] = &dspa_b.hw,
--- -- [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
--- -- [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
--- -- [CLKID_DSPB_A] = &dspb_a.hw,
--- -- [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
--- -- [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
--- -- [CLKID_DSPB_B] = &dspb_b.hw,
--- -- [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
--- -- [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
--- -- [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
--- -- [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
--- -- [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
--- -- [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
--- -- [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
--- -- [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
--- -- [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
--- -- [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
--- -- [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
--- -- [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
--- -- [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
--- -- [CLKID_24M_DIV2] = &clk_24m_div2.hw,
--- -- [CLKID_GEN_SEL] = &gen_sel.hw,
--- -- [CLKID_GEN_DIV] = &gen_div.hw,
--- -- [CLKID_SARADC_DIV] = &saradc_div.hw,
--- -- [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
--- -- [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
--- -- [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
--- -- [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
--- -- [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
--- -- [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
--- -- [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
--- -- [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
--- -- [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
--- -- [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
--- -- [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
--- -- [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
--- -- [CLKID_SPICC_SEL] = &spicc_sel.hw,
--- -- [CLKID_SPICC_DIV] = &spicc_div.hw,
--- -- [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
--- -- [CLKID_TS_DIV] = &ts_div.hw,
--- -- [CLKID_SPIFC_SEL] = &spifc_sel.hw,
--- -- [CLKID_SPIFC_DIV] = &spifc_div.hw,
--- -- [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
--- -- [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
--- -- [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
--- -- [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
--- -- [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
--- -- [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
--- -- [CLKID_PSRAM_SEL] = &psram_sel.hw,
--- -- [CLKID_PSRAM_DIV] = &psram_div.hw,
--- -- [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
--- -- [CLKID_DMC_SEL] = &dmc_sel.hw,
--- -- [CLKID_DMC_DIV] = &dmc_div.hw,
--- -- [CLKID_DMC_SEL2] = &dmc_sel2.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *a1_periphs_hw_clks[] = {
+++ ++ [CLKID_XTAL_IN] = &xtal_in.hw,
+++ ++ [CLKID_FIXPLL_IN] = &fixpll_in.hw,
+++ ++ [CLKID_USB_PHY_IN] = &usb_phy_in.hw,
+++ ++ [CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
+++ ++ [CLKID_HIFIPLL_IN] = &hifipll_in.hw,
+++ ++ [CLKID_SYSPLL_IN] = &syspll_in.hw,
+++ ++ [CLKID_DDS_IN] = &dds_in.hw,
+++ ++ [CLKID_SYS] = &sys.hw,
+++ ++ [CLKID_CLKTREE] = &clktree.hw,
+++ ++ [CLKID_RESET_CTRL] = &reset_ctrl.hw,
+++ ++ [CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
+++ ++ [CLKID_PWR_CTRL] = &pwr_ctrl.hw,
+++ ++ [CLKID_PAD_CTRL] = &pad_ctrl.hw,
+++ ++ [CLKID_SYS_CTRL] = &sys_ctrl.hw,
+++ ++ [CLKID_TEMP_SENSOR] = &temp_sensor.hw,
+++ ++ [CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
+++ ++ [CLKID_SPICC_B] = &spicc_b.hw,
+++ ++ [CLKID_SPICC_A] = &spicc_a.hw,
+++ ++ [CLKID_MSR] = &msr.hw,
+++ ++ [CLKID_AUDIO] = &audio.hw,
+++ ++ [CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
+++ ++ [CLKID_SARADC_EN] = &saradc_en.hw,
+++ ++ [CLKID_PWM_EF] = &pwm_ef.hw,
+++ ++ [CLKID_PWM_CD] = &pwm_cd.hw,
+++ ++ [CLKID_PWM_AB] = &pwm_ab.hw,
+++ ++ [CLKID_CEC] = &cec.hw,
+++ ++ [CLKID_I2C_S] = &i2c_s.hw,
+++ ++ [CLKID_IR_CTRL] = &ir_ctrl.hw,
+++ ++ [CLKID_I2C_M_D] = &i2c_m_d.hw,
+++ ++ [CLKID_I2C_M_C] = &i2c_m_c.hw,
+++ ++ [CLKID_I2C_M_B] = &i2c_m_b.hw,
+++ ++ [CLKID_I2C_M_A] = &i2c_m_a.hw,
+++ ++ [CLKID_ACODEC] = &acodec.hw,
+++ ++ [CLKID_OTP] = &otp.hw,
+++ ++ [CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
+++ ++ [CLKID_USB_PHY] = &usb_phy.hw,
+++ ++ [CLKID_USB_CTRL] = &usb_ctrl.hw,
+++ ++ [CLKID_SYS_DSPB] = &sys_dspb.hw,
+++ ++ [CLKID_SYS_DSPA] = &sys_dspa.hw,
+++ ++ [CLKID_DMA] = &dma.hw,
+++ ++ [CLKID_IRQ_CTRL] = &irq_ctrl.hw,
+++ ++ [CLKID_NIC] = &nic.hw,
+++ ++ [CLKID_GIC] = &gic.hw,
+++ ++ [CLKID_UART_C] = &uart_c.hw,
+++ ++ [CLKID_UART_B] = &uart_b.hw,
+++ ++ [CLKID_UART_A] = &uart_a.hw,
+++ ++ [CLKID_SYS_PSRAM] = &sys_psram.hw,
+++ ++ [CLKID_RSA] = &rsa.hw,
+++ ++ [CLKID_CORESIGHT] = &coresight.hw,
+++ ++ [CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
+++ ++ [CLKID_AUDIO_VAD] = &audio_vad.hw,
+++ ++ [CLKID_AXI_DMC] = &axi_dmc.hw,
+++ ++ [CLKID_AXI_PSRAM] = &axi_psram.hw,
+++ ++ [CLKID_RAMB] = &ramb.hw,
+++ ++ [CLKID_RAMA] = &rama.hw,
+++ ++ [CLKID_AXI_SPIFC] = &axi_spifc.hw,
+++ ++ [CLKID_AXI_NIC] = &axi_nic.hw,
+++ ++ [CLKID_AXI_DMA] = &axi_dma.hw,
+++ ++ [CLKID_CPU_CTRL] = &cpu_ctrl.hw,
+++ ++ [CLKID_ROM] = &rom.hw,
+++ ++ [CLKID_PROC_I2C] = &prod_i2c.hw,
+++ ++ [CLKID_DSPA_SEL] = &dspa_sel.hw,
+++ ++ [CLKID_DSPB_SEL] = &dspb_sel.hw,
+++ ++ [CLKID_DSPA_EN] = &dspa_en.hw,
+++ ++ [CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
+++ ++ [CLKID_DSPB_EN] = &dspb_en.hw,
+++ ++ [CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
+++ ++ [CLKID_RTC] = &rtc.hw,
+++ ++ [CLKID_CECA_32K] = &ceca_32k_out.hw,
+++ ++ [CLKID_CECB_32K] = &cecb_32k_out.hw,
+++ ++ [CLKID_24M] = &clk_24m.hw,
+++ ++ [CLKID_12M] = &clk_12m.hw,
+++ ++ [CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
+++ ++ [CLKID_GEN] = &gen.hw,
+++ ++ [CLKID_SARADC_SEL] = &saradc_sel.hw,
+++ ++ [CLKID_SARADC] = &saradc.hw,
+++ ++ [CLKID_PWM_A] = &pwm_a.hw,
+++ ++ [CLKID_PWM_B] = &pwm_b.hw,
+++ ++ [CLKID_PWM_C] = &pwm_c.hw,
+++ ++ [CLKID_PWM_D] = &pwm_d.hw,
+++ ++ [CLKID_PWM_E] = &pwm_e.hw,
+++ ++ [CLKID_PWM_F] = &pwm_f.hw,
+++ ++ [CLKID_SPICC] = &spicc.hw,
+++ ++ [CLKID_TS] = &ts.hw,
+++ ++ [CLKID_SPIFC] = &spifc.hw,
+++ ++ [CLKID_USB_BUS] = &usb_bus.hw,
+++ ++ [CLKID_SD_EMMC] = &sd_emmc.hw,
+++ ++ [CLKID_PSRAM] = &psram.hw,
+++ ++ [CLKID_DMC] = &dmc.hw,
+++ ++ [CLKID_SYS_A_SEL] = &sys_a_sel.hw,
+++ ++ [CLKID_SYS_A_DIV] = &sys_a_div.hw,
+++ ++ [CLKID_SYS_A] = &sys_a.hw,
+++ ++ [CLKID_SYS_B_SEL] = &sys_b_sel.hw,
+++ ++ [CLKID_SYS_B_DIV] = &sys_b_div.hw,
+++ ++ [CLKID_SYS_B] = &sys_b.hw,
+++ ++ [CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
+++ ++ [CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
+++ ++ [CLKID_DSPA_A] = &dspa_a.hw,
+++ ++ [CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
+++ ++ [CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
+++ ++ [CLKID_DSPA_B] = &dspa_b.hw,
+++ ++ [CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
+++ ++ [CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
+++ ++ [CLKID_DSPB_A] = &dspb_a.hw,
+++ ++ [CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
+++ ++ [CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
+++ ++ [CLKID_DSPB_B] = &dspb_b.hw,
+++ ++ [CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
+++ ++ [CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
+++ ++ [CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
+++ ++ [CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
+++ ++ [CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
+++ ++ [CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
+++ ++ [CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
+++ ++ [CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
+++ ++ [CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
+++ ++ [CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
+++ ++ [CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
+++ ++ [CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
+++ ++ [CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
+++ ++ [CLKID_24M_DIV2] = &clk_24m_div2.hw,
+++ ++ [CLKID_GEN_SEL] = &gen_sel.hw,
+++ ++ [CLKID_GEN_DIV] = &gen_div.hw,
+++ ++ [CLKID_SARADC_DIV] = &saradc_div.hw,
+++ ++ [CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
+++ ++ [CLKID_PWM_A_DIV] = &pwm_a_div.hw,
+++ ++ [CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
+++ ++ [CLKID_PWM_B_DIV] = &pwm_b_div.hw,
+++ ++ [CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
+++ ++ [CLKID_PWM_C_DIV] = &pwm_c_div.hw,
+++ ++ [CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
+++ ++ [CLKID_PWM_D_DIV] = &pwm_d_div.hw,
+++ ++ [CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
+++ ++ [CLKID_PWM_E_DIV] = &pwm_e_div.hw,
+++ ++ [CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
+++ ++ [CLKID_PWM_F_DIV] = &pwm_f_div.hw,
+++ ++ [CLKID_SPICC_SEL] = &spicc_sel.hw,
+++ ++ [CLKID_SPICC_DIV] = &spicc_div.hw,
+++ ++ [CLKID_SPICC_SEL2] = &spicc_sel2.hw,
+++ ++ [CLKID_TS_DIV] = &ts_div.hw,
+++ ++ [CLKID_SPIFC_SEL] = &spifc_sel.hw,
+++ ++ [CLKID_SPIFC_DIV] = &spifc_div.hw,
+++ ++ [CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
+++ ++ [CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
+++ ++ [CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
+++ ++ [CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
+++ ++ [CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
+++ ++ [CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
+++ ++ [CLKID_PSRAM_SEL] = &psram_sel.hw,
+++ ++ [CLKID_PSRAM_DIV] = &psram_div.hw,
+++ ++ [CLKID_PSRAM_SEL2] = &psram_sel2.hw,
+++ ++ [CLKID_DMC_SEL] = &dmc_sel.hw,
+++ ++ [CLKID_DMC_DIV] = &dmc_div.hw,
+++ ++ [CLKID_DMC_SEL2] = &dmc_sel2.hw,
};
/* Convenience table to populate regmap in .probe */
.reg_stride = 4,
};
+++ ++static struct meson_clk_hw_data a1_periphs_clks = {
+++ ++ .hws = a1_periphs_hw_clks,
+++ ++ .num = ARRAY_SIZE(a1_periphs_hw_clks),
+++ ++};
+++ ++
static int meson_a1_periphs_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
clkid);
}
--- -- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
--- -- &a1_periphs_clks);
+++ ++ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);
}
static const struct of_device_id a1_periphs_clkc_match_table[] = {
*/
#include <linux/clk-provider.h>
-----#include <linux/of_device.h>
+++++#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include "a1-pll.h"
#include "clk-regmap.h"
+++ ++#include "meson-clkc-utils.h"
+++ ++
+++ ++#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
static struct clk_regmap fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
};
/* Array of all clocks registered by this provider */
--- --static struct clk_hw_onecell_data a1_pll_clks = {
--- -- .hws = {
--- -- [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
--- -- [CLKID_FIXED_PLL] = &fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
--- -- [CLKID_FCLK_DIV2] = &fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &fclk_div3.hw,
--- -- [CLKID_FCLK_DIV5] = &fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &fclk_div7.hw,
--- -- [CLKID_HIFI_PLL] = &hifi_pll.hw,
--- -- [NR_PLL_CLKS] = NULL,
--- -- },
--- -- .num = NR_PLL_CLKS,
+++ ++static struct clk_hw *a1_pll_hw_clks[] = {
+++ ++ [CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
+++ ++ [CLKID_FIXED_PLL] = &fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
+++ ++ [CLKID_FCLK_DIV2] = &fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV5] = &fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &fclk_div7.hw,
+++ ++ [CLKID_HIFI_PLL] = &hifi_pll.hw,
};
static struct clk_regmap *const a1_pll_regmaps[] = {
.reg_stride = 4,
};
+++ ++static struct meson_clk_hw_data a1_pll_clks = {
+++ ++ .hws = a1_pll_hw_clks,
+++ ++ .num = ARRAY_SIZE(a1_pll_hw_clks),
+++ ++};
+++ ++
static int meson_a1_pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
clkid);
}
--- -- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+++ ++ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
&a1_pll_clks);
}
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
-----#include <linux/of_device.h>
#include <linux/module.h>
+++++#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
+++ ++#include "meson-clkc-utils.h"
#include "axg-audio.h"
#include "clk-regmap.h"
#include "clk-phase.h"
#include "sclk-div.h"
+++ ++#include <dt-bindings/clock/axg-audio-clkc.h>
+++ ++
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
.data = &(struct clk_regmap_gate_data){ \
.offset = (_reg), \
* Array of all clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
--- --static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
--- -- .hws = {
--- -- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
--- -- [AUD_CLKID_PDM] = &pdm.hw,
--- -- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
--- -- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
--- -- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
--- -- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
--- -- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
--- -- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
--- -- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
--- -- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
--- -- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
--- -- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
--- -- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
--- -- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
--- -- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
--- -- [AUD_CLKID_LOOPBACK] = &loopback.hw,
--- -- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
--- -- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
--- -- [AUD_CLKID_RESAMPLE] = &resample.hw,
--- -- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
--- -- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
--- -- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
--- -- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
--- -- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
--- -- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
--- -- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
--- -- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
--- -- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
--- -- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
--- -- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
--- -- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
--- -- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
--- -- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
--- -- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
--- -- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
--- -- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
--- -- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
--- -- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
--- -- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
--- -- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
--- -- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
--- -- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
--- -- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
--- -- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
--- -- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
--- -- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
--- -- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
--- -- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
--- -- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
--- -- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
--- -- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
--- -- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
--- -- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
--- -- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
--- -- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
--- -- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
--- -- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
--- -- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
--- -- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
--- -- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
--- -- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
--- -- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
--- -- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
--- -- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
--- -- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
--- -- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
--- -- [AUD_CLKID_TOP] = &axg_aud_top,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *axg_audio_hw_clks[] = {
+++ ++ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+++ ++ [AUD_CLKID_PDM] = &pdm.hw,
+++ ++ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+++ ++ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+++ ++ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+++ ++ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+++ ++ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+++ ++ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+++ ++ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+++ ++ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+++ ++ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+++ ++ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+++ ++ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+++ ++ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+++ ++ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+++ ++ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+++ ++ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+++ ++ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+++ ++ [AUD_CLKID_RESAMPLE] = &resample.hw,
+++ ++ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+++ ++ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+++ ++ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all G12A clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
--- --static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
--- -- .hws = {
--- -- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
--- -- [AUD_CLKID_PDM] = &pdm.hw,
--- -- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
--- -- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
--- -- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
--- -- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
--- -- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
--- -- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
--- -- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
--- -- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
--- -- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
--- -- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
--- -- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
--- -- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
--- -- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
--- -- [AUD_CLKID_LOOPBACK] = &loopback.hw,
--- -- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
--- -- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
--- -- [AUD_CLKID_RESAMPLE] = &resample.hw,
--- -- [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
--- -- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
--- -- [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
--- -- [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
--- -- [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
--- -- [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
--- -- [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
--- -- [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
--- -- [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
--- -- [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
--- -- [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
--- -- [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
--- -- [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
--- -- [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
--- -- [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
--- -- [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
--- -- [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
--- -- [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
--- -- [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
--- -- [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
--- -- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
--- -- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
--- -- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
--- -- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
--- -- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
--- -- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
--- -- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
--- -- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
--- -- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
--- -- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
--- -- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
--- -- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
--- -- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
--- -- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
--- -- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
--- -- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
--- -- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
--- -- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
--- -- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
--- -- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
--- -- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
--- -- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
--- -- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
--- -- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
--- -- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
--- -- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
--- -- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
--- -- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
--- -- [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
--- -- [AUD_CLKID_TOP] = &axg_aud_top,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *g12a_audio_hw_clks[] = {
+++ ++ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+++ ++ [AUD_CLKID_PDM] = &pdm.hw,
+++ ++ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+++ ++ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+++ ++ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+++ ++ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+++ ++ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+++ ++ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+++ ++ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+++ ++ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+++ ++ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+++ ++ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+++ ++ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+++ ++ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+++ ++ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+++ ++ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+++ ++ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+++ ++ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+++ ++ [AUD_CLKID_RESAMPLE] = &resample.hw,
+++ ++ [AUD_CLKID_POWER_DETECT] = &power_detect.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+++ ++ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+++ ++ [AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
+++ ++ [AUD_CLKID_TOP] = &axg_aud_top,
};
/*
* Array of all SM1 clocks provided by this provider
* The input clocks of the controller will be populated at runtime
*/
--- --static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
--- -- .hws = {
--- -- [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
--- -- [AUD_CLKID_PDM] = &pdm.hw,
--- -- [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
--- -- [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
--- -- [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
--- -- [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
--- -- [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
--- -- [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
--- -- [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
--- -- [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
--- -- [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
--- -- [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
--- -- [AUD_CLKID_TODDR_A] = &toddr_a.hw,
--- -- [AUD_CLKID_TODDR_B] = &toddr_b.hw,
--- -- [AUD_CLKID_TODDR_C] = &toddr_c.hw,
--- -- [AUD_CLKID_LOOPBACK] = &loopback.hw,
--- -- [AUD_CLKID_SPDIFIN] = &spdifin.hw,
--- -- [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
--- -- [AUD_CLKID_RESAMPLE] = &resample.hw,
--- -- [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
--- -- [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
--- -- [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
--- -- [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
--- -- [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
--- -- [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
--- -- [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
--- -- [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
--- -- [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
--- -- [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
--- -- [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
--- -- [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
--- -- [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
--- -- [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
--- -- [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
--- -- [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
--- -- [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
--- -- [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
--- -- [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
--- -- [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
--- -- [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
--- -- [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
--- -- [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
--- -- [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
--- -- [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
--- -- [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
--- -- [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
--- -- [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
--- -- [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
--- -- [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
--- -- [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
--- -- [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
--- -- [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
--- -- [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
--- -- [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
--- -- [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
--- -- [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
--- -- [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
--- -- [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
--- -- [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
--- -- [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
--- -- [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
--- -- [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
--- -- [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
--- -- [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
--- -- [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
--- -- [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
--- -- [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
--- -- [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
--- -- [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
--- -- [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
--- -- [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
--- -- [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
--- -- [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
--- -- [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
--- -- [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
--- -- [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
--- -- [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
--- -- [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
--- -- [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
--- -- [AUD_CLKID_TOP] = &sm1_aud_top.hw,
--- -- [AUD_CLKID_TORAM] = &toram.hw,
--- -- [AUD_CLKID_EQDRC] = &eqdrc.hw,
--- -- [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
--- -- [AUD_CLKID_TOVAD] = &tovad.hw,
--- -- [AUD_CLKID_LOCKER] = &locker.hw,
--- -- [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
--- -- [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
--- -- [AUD_CLKID_TODDR_D] = &toddr_d.hw,
--- -- [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
--- -- [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
--- -- [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
--- -- [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
--- -- [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
--- -- [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *sm1_audio_hw_clks[] = {
+++ ++ [AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
+++ ++ [AUD_CLKID_PDM] = &pdm.hw,
+++ ++ [AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
+++ ++ [AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
+++ ++ [AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
+++ ++ [AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
+++ ++ [AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
+++ ++ [AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
+++ ++ [AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
+++ ++ [AUD_CLKID_FRDDR_A] = &frddr_a.hw,
+++ ++ [AUD_CLKID_FRDDR_B] = &frddr_b.hw,
+++ ++ [AUD_CLKID_FRDDR_C] = &frddr_c.hw,
+++ ++ [AUD_CLKID_TODDR_A] = &toddr_a.hw,
+++ ++ [AUD_CLKID_TODDR_B] = &toddr_b.hw,
+++ ++ [AUD_CLKID_TODDR_C] = &toddr_c.hw,
+++ ++ [AUD_CLKID_LOOPBACK] = &loopback.hw,
+++ ++ [AUD_CLKID_SPDIFIN] = &spdifin.hw,
+++ ++ [AUD_CLKID_SPDIFOUT] = &spdifout.hw,
+++ ++ [AUD_CLKID_RESAMPLE] = &resample.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
+++ ++ [AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
+++ ++ [AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
+++ ++ [AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
+++ ++ [AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
+++ ++ [AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
+++ ++ [AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
+++ ++ [AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
+++ ++ [AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
+++ ++ [AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
+++ ++ [AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
+++ ++ [AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
+++ ++ [AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
+++ ++ [AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
+++ ++ [AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
+++ ++ [AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
+++ ++ [AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
+++ ++ [AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
+++ ++ [AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
+++ ++ [AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
+++ ++ [AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
+++ ++ [AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
+++ ++ [AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
+++ ++ [AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
+++ ++ [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
+++ ++ [AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
+++ ++ [AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
+++ ++ [AUD_CLKID_TOP] = &sm1_aud_top.hw,
+++ ++ [AUD_CLKID_TORAM] = &toram.hw,
+++ ++ [AUD_CLKID_EQDRC] = &eqdrc.hw,
+++ ++ [AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
+++ ++ [AUD_CLKID_TOVAD] = &tovad.hw,
+++ ++ [AUD_CLKID_LOCKER] = &locker.hw,
+++ ++ [AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
+++ ++ [AUD_CLKID_FRDDR_D] = &frddr_d.hw,
+++ ++ [AUD_CLKID_TODDR_D] = &toddr_d.hw,
+++ ++ [AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
+++ ++ [AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
+++ ++ [AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
+++ ++ [AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
+++ ++ [AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
+++ ++ [AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
};
struct audioclk_data {
struct clk_regmap *const *regmap_clks;
unsigned int regmap_clk_num;
--- -- struct clk_hw_onecell_data *hw_onecell_data;
+++ ++ struct meson_clk_hw_data hw_clks;
unsigned int reset_offset;
unsigned int reset_num;
};
data->regmap_clks[i]->map = map;
/* Take care to skip the registered input clocks */
--- -- for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
+++ ++ for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
const char *name;
--- -- hw = data->hw_onecell_data->hws[i];
+++ ++ hw = data->hw_clks.hws[i];
/* array might be sparse */
if (!hw)
continue;
}
}
--- -- ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
--- -- data->hw_onecell_data);
+++ ++ ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
if (ret)
return ret;
static const struct audioclk_data axg_audioclk_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
--- -- .hw_onecell_data = &axg_audio_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = axg_audio_hw_clks,
+++ ++ .num = ARRAY_SIZE(axg_audio_hw_clks),
+++ ++ },
};
static const struct audioclk_data g12a_audioclk_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
--- -- .hw_onecell_data = &g12a_audio_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = g12a_audio_hw_clks,
+++ ++ .num = ARRAY_SIZE(g12a_audio_hw_clks),
+++ ++ },
.reset_offset = AUDIO_SW_RESET,
.reset_num = 26,
};
static const struct audioclk_data sm1_audioclk_data = {
.regmap_clks = sm1_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
--- -- .hw_onecell_data = &sm1_audio_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = sm1_audio_hw_clks,
+++ ++ .num = ARRAY_SIZE(sm1_audio_hw_clks),
+++ ++ },
.reset_offset = AUDIO_SM1_SW_RESET0,
.reset_num = 39,
};
#include <linux/clk-provider.h>
#include <linux/init.h>
-----#include <linux/of_device.h>
+++++#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include "axg.h"
#include "meson-eeclk.h"
+++ ++#include <dt-bindings/clock/axg-clkc.h>
+++ ++
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap axg_fixed_pll_dco = {
/* Array of all clocks provided by this provider */
--- --static struct clk_hw_onecell_data axg_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &axg_sys_pll.hw,
--- -- [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
--- -- [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &axg_clk81.hw,
--- -- [CLKID_MPLL0] = &axg_mpll0.hw,
--- -- [CLKID_MPLL1] = &axg_mpll1.hw,
--- -- [CLKID_MPLL2] = &axg_mpll2.hw,
--- -- [CLKID_MPLL3] = &axg_mpll3.hw,
--- -- [CLKID_DDR] = &axg_ddr.hw,
--- -- [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
--- -- [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
--- -- [CLKID_ISA] = &axg_isa.hw,
--- -- [CLKID_PL301] = &axg_pl301.hw,
--- -- [CLKID_PERIPHS] = &axg_periphs.hw,
--- -- [CLKID_SPICC0] = &axg_spicc_0.hw,
--- -- [CLKID_I2C] = &axg_i2c.hw,
--- -- [CLKID_RNG0] = &axg_rng0.hw,
--- -- [CLKID_UART0] = &axg_uart0.hw,
--- -- [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
--- -- [CLKID_SPICC1] = &axg_spicc_1.hw,
--- -- [CLKID_PCIE_A] = &axg_pcie_a.hw,
--- -- [CLKID_PCIE_B] = &axg_pcie_b.hw,
--- -- [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
--- -- [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
--- -- [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
--- -- [CLKID_DMA] = &axg_dma.hw,
--- -- [CLKID_SPI] = &axg_spi.hw,
--- -- [CLKID_AUDIO] = &axg_audio.hw,
--- -- [CLKID_ETH] = &axg_eth_core.hw,
--- -- [CLKID_UART1] = &axg_uart1.hw,
--- -- [CLKID_G2D] = &axg_g2d.hw,
--- -- [CLKID_USB0] = &axg_usb0.hw,
--- -- [CLKID_USB1] = &axg_usb1.hw,
--- -- [CLKID_RESET] = &axg_reset.hw,
--- -- [CLKID_USB] = &axg_usb_general.hw,
--- -- [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
--- -- [CLKID_EFUSE] = &axg_efuse.hw,
--- -- [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
--- -- [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
--- -- [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
--- -- [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
--- -- [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
--- -- [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
--- -- [CLKID_GIC] = &axg_gic.hw,
--- -- [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
--- -- [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
--- -- [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
--- -- [CLKID_AO_IFACE] = &axg_ao_iface.hw,
--- -- [CLKID_AO_I2C] = &axg_ao_i2c.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
--- -- [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
--- -- [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
--- -- [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
--- -- [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
--- -- [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
--- -- [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
--- -- [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
--- -- [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
--- -- [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
--- -- [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
--- -- [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
--- -- [CLKID_GEN_CLK] = &axg_gen_clk.hw,
--- -- [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
--- -- [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
--- -- [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
--- -- [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
--- -- [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
--- -- [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
--- -- [CLKID_VPU_0] = &axg_vpu_0.hw,
--- -- [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
--- -- [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
--- -- [CLKID_VPU_1] = &axg_vpu_1.hw,
--- -- [CLKID_VPU] = &axg_vpu.hw,
--- -- [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
--- -- [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0] = &axg_vapb_0.hw,
--- -- [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
--- -- [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1] = &axg_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
--- -- [CLKID_VAPB] = &axg_vapb.hw,
--- -- [CLKID_VCLK] = &axg_vclk.hw,
--- -- [CLKID_VCLK2] = &axg_vclk2.hw,
--- -- [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
--- -- [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
--- -- [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
--- -- [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
--- -- [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
--- -- [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *axg_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &axg_sys_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
+++ ++ [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &axg_clk81.hw,
+++ ++ [CLKID_MPLL0] = &axg_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &axg_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &axg_mpll2.hw,
+++ ++ [CLKID_MPLL3] = &axg_mpll3.hw,
+++ ++ [CLKID_DDR] = &axg_ddr.hw,
+++ ++ [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
+++ ++ [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
+++ ++ [CLKID_ISA] = &axg_isa.hw,
+++ ++ [CLKID_PL301] = &axg_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &axg_periphs.hw,
+++ ++ [CLKID_SPICC0] = &axg_spicc_0.hw,
+++ ++ [CLKID_I2C] = &axg_i2c.hw,
+++ ++ [CLKID_RNG0] = &axg_rng0.hw,
+++ ++ [CLKID_UART0] = &axg_uart0.hw,
+++ ++ [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
+++ ++ [CLKID_SPICC1] = &axg_spicc_1.hw,
+++ ++ [CLKID_PCIE_A] = &axg_pcie_a.hw,
+++ ++ [CLKID_PCIE_B] = &axg_pcie_b.hw,
+++ ++ [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
+++ ++ [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
+++ ++ [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
+++ ++ [CLKID_DMA] = &axg_dma.hw,
+++ ++ [CLKID_SPI] = &axg_spi.hw,
+++ ++ [CLKID_AUDIO] = &axg_audio.hw,
+++ ++ [CLKID_ETH] = &axg_eth_core.hw,
+++ ++ [CLKID_UART1] = &axg_uart1.hw,
+++ ++ [CLKID_G2D] = &axg_g2d.hw,
+++ ++ [CLKID_USB0] = &axg_usb0.hw,
+++ ++ [CLKID_USB1] = &axg_usb1.hw,
+++ ++ [CLKID_RESET] = &axg_reset.hw,
+++ ++ [CLKID_USB] = &axg_usb_general.hw,
+++ ++ [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
+++ ++ [CLKID_EFUSE] = &axg_efuse.hw,
+++ ++ [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
+++ ++ [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
+++ ++ [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
+++ ++ [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
+++ ++ [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
+++ ++ [CLKID_GIC] = &axg_gic.hw,
+++ ++ [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
+++ ++ [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
+++ ++ [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
+++ ++ [CLKID_AO_IFACE] = &axg_ao_iface.hw,
+++ ++ [CLKID_AO_I2C] = &axg_ao_i2c.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
+++ ++ [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
+++ ++ [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
+++ ++ [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
+++ ++ [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
+++ ++ [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
+++ ++ [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
+++ ++ [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
+++ ++ [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
+++ ++ [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
+++ ++ [CLKID_GEN_CLK] = &axg_gen_clk.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
+++ ++ [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
+++ ++ [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
+++ ++ [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
+++ ++ [CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0] = &axg_vpu_0.hw,
+++ ++ [CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1] = &axg_vpu_1.hw,
+++ ++ [CLKID_VPU] = &axg_vpu.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0] = &axg_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1] = &axg_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &axg_vapb.hw,
+++ ++ [CLKID_VCLK] = &axg_vclk.hw,
+++ ++ [CLKID_VCLK2] = &axg_vclk2.hw,
+++ ++ [CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &axg_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
+++ ++ [CLKID_CTS_ENCL] = &axg_cts_encl.hw,
+++ ++ [CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
+++ ++ [CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
+++ ++ [CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
};
/* Convenience table to populate regmap in .probe */
static const struct meson_eeclkc_data axg_clkc_data = {
.regmap_clks = axg_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
--- -- .hw_onecell_data = &axg_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = axg_hw_clks,
+++ ++ .num = ARRAY_SIZE(axg_hw_clks),
+++ ++ },
};
#include <linux/clk-provider.h>
#include <linux/init.h>
-----#include <linux/of_device.h>
+++++#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/module.h>
#include "meson-eeclk.h"
#include "g12a.h"
+++ ++#include <dt-bindings/clock/g12a-clkc.h>
+++ ++
static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap g12a_fixed_pll_dco = {
static MESON_GATE_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4);
/* Array of all clocks provided by this provider */
--- --static struct clk_hw_onecell_data g12a_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
--- -- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
--- -- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
--- -- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &g12a_clk81.hw,
--- -- [CLKID_MPLL0] = &g12a_mpll0.hw,
--- -- [CLKID_MPLL1] = &g12a_mpll1.hw,
--- -- [CLKID_MPLL2] = &g12a_mpll2.hw,
--- -- [CLKID_MPLL3] = &g12a_mpll3.hw,
--- -- [CLKID_DDR] = &g12a_ddr.hw,
--- -- [CLKID_DOS] = &g12a_dos.hw,
--- -- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
--- -- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
--- -- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
--- -- [CLKID_ISA] = &g12a_isa.hw,
--- -- [CLKID_PL301] = &g12a_pl301.hw,
--- -- [CLKID_PERIPHS] = &g12a_periphs.hw,
--- -- [CLKID_SPICC0] = &g12a_spicc_0.hw,
--- -- [CLKID_I2C] = &g12a_i2c.hw,
--- -- [CLKID_SANA] = &g12a_sana.hw,
--- -- [CLKID_SD] = &g12a_sd.hw,
--- -- [CLKID_RNG0] = &g12a_rng0.hw,
--- -- [CLKID_UART0] = &g12a_uart0.hw,
--- -- [CLKID_SPICC1] = &g12a_spicc_1.hw,
--- -- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
--- -- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
--- -- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
--- -- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
--- -- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
--- -- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
--- -- [CLKID_AUDIO] = &g12a_audio.hw,
--- -- [CLKID_ETH] = &g12a_eth_core.hw,
--- -- [CLKID_DEMUX] = &g12a_demux.hw,
--- -- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
--- -- [CLKID_ADC] = &g12a_adc.hw,
--- -- [CLKID_UART1] = &g12a_uart1.hw,
--- -- [CLKID_G2D] = &g12a_g2d.hw,
--- -- [CLKID_RESET] = &g12a_reset.hw,
--- -- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
--- -- [CLKID_PARSER] = &g12a_parser.hw,
--- -- [CLKID_USB] = &g12a_usb_general.hw,
--- -- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
--- -- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
--- -- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
--- -- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
--- -- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
--- -- [CLKID_BT656] = &g12a_bt656.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
--- -- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
--- -- [CLKID_UART2] = &g12a_uart2.hw,
--- -- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
--- -- [CLKID_GIC] = &g12a_gic.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
--- -- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
--- -- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
--- -- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
--- -- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
--- -- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
--- -- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
--- -- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
--- -- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
--- -- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
--- -- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
--- -- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
--- -- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
--- -- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
--- -- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
--- -- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
--- -- [CLKID_IEC958] = &g12a_iec958_gate.hw,
--- -- [CLKID_ENC480P] = &g12a_enc480p.hw,
--- -- [CLKID_RNG1] = &g12a_rng1.hw,
--- -- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
--- -- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
--- -- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
--- -- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
--- -- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
--- -- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
--- -- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
--- -- [CLKID_DMA] = &g12a_dma.hw,
--- -- [CLKID_EFUSE] = &g12a_efuse.hw,
--- -- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
--- -- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
--- -- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
--- -- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
--- -- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
--- -- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
--- -- [CLKID_VPU_0] = &g12a_vpu_0.hw,
--- -- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
--- -- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
--- -- [CLKID_VPU_1] = &g12a_vpu_1.hw,
--- -- [CLKID_VPU] = &g12a_vpu.hw,
--- -- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
--- -- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
--- -- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
--- -- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
--- -- [CLKID_VAPB] = &g12a_vapb.hw,
--- -- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
--- -- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
--- -- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
--- -- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
--- -- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
--- -- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
--- -- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
--- -- [CLKID_VCLK] = &g12a_vclk.hw,
--- -- [CLKID_VCLK2] = &g12a_vclk2.hw,
--- -- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
--- -- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
--- -- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
--- -- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
--- -- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
--- -- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
--- -- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
--- -- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
--- -- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
--- -- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
--- -- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
--- -- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
--- -- [CLKID_HDMI] = &g12a_hdmi.hw,
--- -- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
--- -- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
--- -- [CLKID_MALI_0] = &g12a_mali_0.hw,
--- -- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
--- -- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
--- -- [CLKID_MALI_1] = &g12a_mali_1.hw,
--- -- [CLKID_MALI] = &g12a_mali.hw,
--- -- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
--- -- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
--- -- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
--- -- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
--- -- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
--- -- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
--- -- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
--- -- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
--- -- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
--- -- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
--- -- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
--- -- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
--- -- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
--- -- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
--- -- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
--- -- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
--- -- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
--- -- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
--- -- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
--- -- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
--- -- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
--- -- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
--- -- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
--- -- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
--- -- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
--- -- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
--- -- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
--- -- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
--- -- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
--- -- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
--- -- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
--- -- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
--- -- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
--- -- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
--- -- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
--- -- [CLKID_TS_DIV] = &g12a_ts_div.hw,
--- -- [CLKID_TS] = &g12a_ts.hw,
--- -- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
--- -- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
--- -- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
--- -- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
--- -- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
--- -- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
--- -- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
--- --};
--- --
--- --static struct clk_hw_onecell_data g12b_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
--- -- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
--- -- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
--- -- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &g12a_clk81.hw,
--- -- [CLKID_MPLL0] = &g12a_mpll0.hw,
--- -- [CLKID_MPLL1] = &g12a_mpll1.hw,
--- -- [CLKID_MPLL2] = &g12a_mpll2.hw,
--- -- [CLKID_MPLL3] = &g12a_mpll3.hw,
--- -- [CLKID_DDR] = &g12a_ddr.hw,
--- -- [CLKID_DOS] = &g12a_dos.hw,
--- -- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
--- -- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
--- -- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
--- -- [CLKID_ISA] = &g12a_isa.hw,
--- -- [CLKID_PL301] = &g12a_pl301.hw,
--- -- [CLKID_PERIPHS] = &g12a_periphs.hw,
--- -- [CLKID_SPICC0] = &g12a_spicc_0.hw,
--- -- [CLKID_I2C] = &g12a_i2c.hw,
--- -- [CLKID_SANA] = &g12a_sana.hw,
--- -- [CLKID_SD] = &g12a_sd.hw,
--- -- [CLKID_RNG0] = &g12a_rng0.hw,
--- -- [CLKID_UART0] = &g12a_uart0.hw,
--- -- [CLKID_SPICC1] = &g12a_spicc_1.hw,
--- -- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
--- -- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
--- -- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
--- -- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
--- -- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
--- -- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
--- -- [CLKID_AUDIO] = &g12a_audio.hw,
--- -- [CLKID_ETH] = &g12a_eth_core.hw,
--- -- [CLKID_DEMUX] = &g12a_demux.hw,
--- -- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
--- -- [CLKID_ADC] = &g12a_adc.hw,
--- -- [CLKID_UART1] = &g12a_uart1.hw,
--- -- [CLKID_G2D] = &g12a_g2d.hw,
--- -- [CLKID_RESET] = &g12a_reset.hw,
--- -- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
--- -- [CLKID_PARSER] = &g12a_parser.hw,
--- -- [CLKID_USB] = &g12a_usb_general.hw,
--- -- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
--- -- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
--- -- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
--- -- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
--- -- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
--- -- [CLKID_BT656] = &g12a_bt656.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
--- -- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
--- -- [CLKID_UART2] = &g12a_uart2.hw,
--- -- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
--- -- [CLKID_GIC] = &g12a_gic.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
--- -- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
--- -- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
--- -- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
--- -- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
--- -- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
--- -- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
--- -- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
--- -- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
--- -- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
--- -- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
--- -- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
--- -- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
--- -- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
--- -- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
--- -- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
--- -- [CLKID_IEC958] = &g12a_iec958_gate.hw,
--- -- [CLKID_ENC480P] = &g12a_enc480p.hw,
--- -- [CLKID_RNG1] = &g12a_rng1.hw,
--- -- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
--- -- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
--- -- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
--- -- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
--- -- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
--- -- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
--- -- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
--- -- [CLKID_DMA] = &g12a_dma.hw,
--- -- [CLKID_EFUSE] = &g12a_efuse.hw,
--- -- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
--- -- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
--- -- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
--- -- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
--- -- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
--- -- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
--- -- [CLKID_VPU_0] = &g12a_vpu_0.hw,
--- -- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
--- -- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
--- -- [CLKID_VPU_1] = &g12a_vpu_1.hw,
--- -- [CLKID_VPU] = &g12a_vpu.hw,
--- -- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
--- -- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
--- -- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
--- -- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
--- -- [CLKID_VAPB] = &g12a_vapb.hw,
--- -- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
--- -- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
--- -- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
--- -- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
--- -- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
--- -- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
--- -- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
--- -- [CLKID_VCLK] = &g12a_vclk.hw,
--- -- [CLKID_VCLK2] = &g12a_vclk2.hw,
--- -- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
--- -- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
--- -- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
--- -- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
--- -- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
--- -- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
--- -- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
--- -- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
--- -- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
--- -- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
--- -- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
--- -- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
--- -- [CLKID_HDMI] = &g12a_hdmi.hw,
--- -- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
--- -- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
--- -- [CLKID_MALI_0] = &g12a_mali_0.hw,
--- -- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
--- -- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
--- -- [CLKID_MALI_1] = &g12a_mali_1.hw,
--- -- [CLKID_MALI] = &g12a_mali.hw,
--- -- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
--- -- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
--- -- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
--- -- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
--- -- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
--- -- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
--- -- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
--- -- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
--- -- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
--- -- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
--- -- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
--- -- [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
--- -- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
--- -- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
--- -- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
--- -- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
--- -- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
--- -- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
--- -- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
--- -- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
--- -- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
--- -- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
--- -- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
--- -- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
--- -- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
--- -- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
--- -- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
--- -- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
--- -- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
--- -- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
--- -- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
--- -- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
--- -- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
--- -- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
--- -- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
--- -- [CLKID_TS_DIV] = &g12a_ts_div.hw,
--- -- [CLKID_TS] = &g12a_ts.hw,
--- -- [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
--- -- [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
--- -- [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
--- -- [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
--- -- [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
--- -- [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
--- -- [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
--- -- [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
--- -- [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
--- -- [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
--- -- [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
--- -- [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
--- -- [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
--- -- [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
--- -- [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
--- -- [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
--- -- [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
--- -- [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
--- -- [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
--- -- [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
--- -- [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
--- -- [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
--- -- [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
--- -- [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
--- -- [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
--- -- [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
--- -- [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
--- -- [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
--- -- [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
--- -- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
--- -- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
--- -- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
--- -- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
--- -- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
--- -- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
--- -- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
--- -- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
--- -- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
--- -- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
--- -- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
--- -- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
--- -- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
--- --};
--- --
--- --static struct clk_hw_onecell_data sm1_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
--- -- [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
--- -- [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
--- -- [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &g12a_clk81.hw,
--- -- [CLKID_MPLL0] = &g12a_mpll0.hw,
--- -- [CLKID_MPLL1] = &g12a_mpll1.hw,
--- -- [CLKID_MPLL2] = &g12a_mpll2.hw,
--- -- [CLKID_MPLL3] = &g12a_mpll3.hw,
--- -- [CLKID_DDR] = &g12a_ddr.hw,
--- -- [CLKID_DOS] = &g12a_dos.hw,
--- -- [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
--- -- [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
--- -- [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
--- -- [CLKID_ISA] = &g12a_isa.hw,
--- -- [CLKID_PL301] = &g12a_pl301.hw,
--- -- [CLKID_PERIPHS] = &g12a_periphs.hw,
--- -- [CLKID_SPICC0] = &g12a_spicc_0.hw,
--- -- [CLKID_I2C] = &g12a_i2c.hw,
--- -- [CLKID_SANA] = &g12a_sana.hw,
--- -- [CLKID_SD] = &g12a_sd.hw,
--- -- [CLKID_RNG0] = &g12a_rng0.hw,
--- -- [CLKID_UART0] = &g12a_uart0.hw,
--- -- [CLKID_SPICC1] = &g12a_spicc_1.hw,
--- -- [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
--- -- [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
--- -- [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
--- -- [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
--- -- [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
--- -- [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
--- -- [CLKID_AUDIO] = &g12a_audio.hw,
--- -- [CLKID_ETH] = &g12a_eth_core.hw,
--- -- [CLKID_DEMUX] = &g12a_demux.hw,
--- -- [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
--- -- [CLKID_ADC] = &g12a_adc.hw,
--- -- [CLKID_UART1] = &g12a_uart1.hw,
--- -- [CLKID_G2D] = &g12a_g2d.hw,
--- -- [CLKID_RESET] = &g12a_reset.hw,
--- -- [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
--- -- [CLKID_PARSER] = &g12a_parser.hw,
--- -- [CLKID_USB] = &g12a_usb_general.hw,
--- -- [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
--- -- [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
--- -- [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
--- -- [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
--- -- [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
--- -- [CLKID_BT656] = &g12a_bt656.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
--- -- [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
--- -- [CLKID_UART2] = &g12a_uart2.hw,
--- -- [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
--- -- [CLKID_GIC] = &g12a_gic.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
--- -- [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
--- -- [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
--- -- [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
--- -- [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
--- -- [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
--- -- [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
--- -- [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
--- -- [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
--- -- [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
--- -- [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
--- -- [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
--- -- [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
--- -- [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
--- -- [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
--- -- [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
--- -- [CLKID_IEC958] = &g12a_iec958_gate.hw,
--- -- [CLKID_ENC480P] = &g12a_enc480p.hw,
--- -- [CLKID_RNG1] = &g12a_rng1.hw,
--- -- [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
--- -- [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
--- -- [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
--- -- [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
--- -- [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
--- -- [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
--- -- [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
--- -- [CLKID_DMA] = &g12a_dma.hw,
--- -- [CLKID_EFUSE] = &g12a_efuse.hw,
--- -- [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
--- -- [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
--- -- [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
--- -- [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
--- -- [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
--- -- [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
--- -- [CLKID_VPU_0] = &g12a_vpu_0.hw,
--- -- [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
--- -- [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
--- -- [CLKID_VPU_1] = &g12a_vpu_1.hw,
--- -- [CLKID_VPU] = &g12a_vpu.hw,
--- -- [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
--- -- [CLKID_VAPB_0] = &g12a_vapb_0.hw,
--- -- [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
--- -- [CLKID_VAPB_1] = &g12a_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
--- -- [CLKID_VAPB] = &g12a_vapb.hw,
--- -- [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
--- -- [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
--- -- [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
--- -- [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
--- -- [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
--- -- [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
--- -- [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
--- -- [CLKID_VCLK] = &g12a_vclk.hw,
--- -- [CLKID_VCLK2] = &g12a_vclk2.hw,
--- -- [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
--- -- [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
--- -- [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
--- -- [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
--- -- [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
--- -- [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
--- -- [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
--- -- [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
--- -- [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
--- -- [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
--- -- [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
--- -- [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
--- -- [CLKID_HDMI] = &g12a_hdmi.hw,
--- -- [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
--- -- [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
--- -- [CLKID_MALI_0] = &g12a_mali_0.hw,
--- -- [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
--- -- [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
--- -- [CLKID_MALI_1] = &g12a_mali_1.hw,
--- -- [CLKID_MALI] = &g12a_mali.hw,
--- -- [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
--- -- [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
--- -- [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
--- -- [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
--- -- [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
--- -- [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
--- -- [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
--- -- [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
--- -- [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
--- -- [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
--- -- [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
--- -- [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
--- -- [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
--- -- [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
--- -- [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
--- -- [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
--- -- [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
--- -- [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
--- -- [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
--- -- [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
--- -- [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
--- -- [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
--- -- [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
--- -- [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
--- -- [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
--- -- [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
--- -- [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
--- -- [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
--- -- [CLKID_VDEC_1] = &g12a_vdec_1.hw,
--- -- [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
--- -- [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
--- -- [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
--- -- [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
--- -- [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
--- -- [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
--- -- [CLKID_TS_DIV] = &g12a_ts_div.hw,
--- -- [CLKID_TS] = &g12a_ts.hw,
--- -- [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
--- -- [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
--- -- [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
--- -- [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
--- -- [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
--- -- [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
--- -- [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
--- -- [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
--- -- [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
--- -- [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
--- -- [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
--- -- [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
--- -- [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
--- -- [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
--- -- [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
--- -- [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
--- -- [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
--- -- [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
--- -- [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
--- -- [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
--- -- [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
--- -- [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
--- -- [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
--- -- [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
--- -- [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
--- -- [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
--- -- [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
--- -- [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *g12a_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+++ ++ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+++ ++ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &g12a_clk81.hw,
+++ ++ [CLKID_MPLL0] = &g12a_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &g12a_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &g12a_mpll2.hw,
+++ ++ [CLKID_MPLL3] = &g12a_mpll3.hw,
+++ ++ [CLKID_DDR] = &g12a_ddr.hw,
+++ ++ [CLKID_DOS] = &g12a_dos.hw,
+++ ++ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+++ ++ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+++ ++ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+++ ++ [CLKID_ISA] = &g12a_isa.hw,
+++ ++ [CLKID_PL301] = &g12a_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &g12a_periphs.hw,
+++ ++ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+++ ++ [CLKID_I2C] = &g12a_i2c.hw,
+++ ++ [CLKID_SANA] = &g12a_sana.hw,
+++ ++ [CLKID_SD] = &g12a_sd.hw,
+++ ++ [CLKID_RNG0] = &g12a_rng0.hw,
+++ ++ [CLKID_UART0] = &g12a_uart0.hw,
+++ ++ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+++ ++ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+++ ++ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+++ ++ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+++ ++ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+++ ++ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+++ ++ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+++ ++ [CLKID_AUDIO] = &g12a_audio.hw,
+++ ++ [CLKID_ETH] = &g12a_eth_core.hw,
+++ ++ [CLKID_DEMUX] = &g12a_demux.hw,
+++ ++ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+++ ++ [CLKID_ADC] = &g12a_adc.hw,
+++ ++ [CLKID_UART1] = &g12a_uart1.hw,
+++ ++ [CLKID_G2D] = &g12a_g2d.hw,
+++ ++ [CLKID_RESET] = &g12a_reset.hw,
+++ ++ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+++ ++ [CLKID_PARSER] = &g12a_parser.hw,
+++ ++ [CLKID_USB] = &g12a_usb_general.hw,
+++ ++ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+++ ++ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+++ ++ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+++ ++ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+++ ++ [CLKID_BT656] = &g12a_bt656.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+++ ++ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+++ ++ [CLKID_UART2] = &g12a_uart2.hw,
+++ ++ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+++ ++ [CLKID_GIC] = &g12a_gic.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+++ ++ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+++ ++ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+++ ++ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+++ ++ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+++ ++ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+++ ++ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+++ ++ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+++ ++ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+++ ++ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+++ ++ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+++ ++ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+++ ++ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+++ ++ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+++ ++ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+++ ++ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+++ ++ [CLKID_ENC480P] = &g12a_enc480p.hw,
+++ ++ [CLKID_RNG1] = &g12a_rng1.hw,
+++ ++ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+++ ++ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+++ ++ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+++ ++ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+++ ++ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+++ ++ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+++ ++ [CLKID_DMA] = &g12a_dma.hw,
+++ ++ [CLKID_EFUSE] = &g12a_efuse.hw,
+++ ++ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+++ ++ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+++ ++ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+++ ++ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+++ ++ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+++ ++ [CLKID_VPU] = &g12a_vpu.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &g12a_vapb.hw,
+++ ++ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+++ ++ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+++ ++ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+++ ++ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+++ ++ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+++ ++ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+++ ++ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+++ ++ [CLKID_VCLK] = &g12a_vclk.hw,
+++ ++ [CLKID_VCLK2] = &g12a_vclk2.hw,
+++ ++ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+++ ++ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+++ ++ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+++ ++ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+++ ++ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+++ ++ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+++ ++ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+++ ++ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+++ ++ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+++ ++ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+++ ++ [CLKID_HDMI] = &g12a_hdmi.hw,
+++ ++ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+++ ++ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+++ ++ [CLKID_MALI_0] = &g12a_mali_0.hw,
+++ ++ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+++ ++ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+++ ++ [CLKID_MALI_1] = &g12a_mali_1.hw,
+++ ++ [CLKID_MALI] = &g12a_mali.hw,
+++ ++ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+++ ++ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+++ ++ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+++ ++ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+++ ++ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+++ ++ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+++ ++ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+++ ++ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+++ ++ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+++ ++ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+++ ++ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+++ ++ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+++ ++ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+++ ++ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+++ ++ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+++ ++ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+++ ++ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+++ ++ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+++ ++ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+++ ++ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+++ ++ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+++ ++ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+++ ++ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+++ ++ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+++ ++ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+++ ++ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+++ ++ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+++ ++ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+++ ++ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+++ ++ [CLKID_TS] = &g12a_ts.hw,
+++ ++ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+++ ++ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+++ ++ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+++ ++ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+++ ++ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+++ ++ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+++ ++};
+++ ++
+++ ++static struct clk_hw *g12b_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+++ ++ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+++ ++ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &g12a_clk81.hw,
+++ ++ [CLKID_MPLL0] = &g12a_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &g12a_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &g12a_mpll2.hw,
+++ ++ [CLKID_MPLL3] = &g12a_mpll3.hw,
+++ ++ [CLKID_DDR] = &g12a_ddr.hw,
+++ ++ [CLKID_DOS] = &g12a_dos.hw,
+++ ++ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+++ ++ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+++ ++ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+++ ++ [CLKID_ISA] = &g12a_isa.hw,
+++ ++ [CLKID_PL301] = &g12a_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &g12a_periphs.hw,
+++ ++ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+++ ++ [CLKID_I2C] = &g12a_i2c.hw,
+++ ++ [CLKID_SANA] = &g12a_sana.hw,
+++ ++ [CLKID_SD] = &g12a_sd.hw,
+++ ++ [CLKID_RNG0] = &g12a_rng0.hw,
+++ ++ [CLKID_UART0] = &g12a_uart0.hw,
+++ ++ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+++ ++ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+++ ++ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+++ ++ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+++ ++ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+++ ++ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+++ ++ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+++ ++ [CLKID_AUDIO] = &g12a_audio.hw,
+++ ++ [CLKID_ETH] = &g12a_eth_core.hw,
+++ ++ [CLKID_DEMUX] = &g12a_demux.hw,
+++ ++ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+++ ++ [CLKID_ADC] = &g12a_adc.hw,
+++ ++ [CLKID_UART1] = &g12a_uart1.hw,
+++ ++ [CLKID_G2D] = &g12a_g2d.hw,
+++ ++ [CLKID_RESET] = &g12a_reset.hw,
+++ ++ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+++ ++ [CLKID_PARSER] = &g12a_parser.hw,
+++ ++ [CLKID_USB] = &g12a_usb_general.hw,
+++ ++ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+++ ++ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+++ ++ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+++ ++ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+++ ++ [CLKID_BT656] = &g12a_bt656.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+++ ++ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+++ ++ [CLKID_UART2] = &g12a_uart2.hw,
+++ ++ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+++ ++ [CLKID_GIC] = &g12a_gic.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+++ ++ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+++ ++ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+++ ++ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+++ ++ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+++ ++ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+++ ++ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+++ ++ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+++ ++ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+++ ++ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+++ ++ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+++ ++ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+++ ++ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+++ ++ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+++ ++ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+++ ++ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+++ ++ [CLKID_ENC480P] = &g12a_enc480p.hw,
+++ ++ [CLKID_RNG1] = &g12a_rng1.hw,
+++ ++ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+++ ++ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+++ ++ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+++ ++ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+++ ++ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+++ ++ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+++ ++ [CLKID_DMA] = &g12a_dma.hw,
+++ ++ [CLKID_EFUSE] = &g12a_efuse.hw,
+++ ++ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+++ ++ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+++ ++ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+++ ++ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+++ ++ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+++ ++ [CLKID_VPU] = &g12a_vpu.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &g12a_vapb.hw,
+++ ++ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+++ ++ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+++ ++ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+++ ++ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+++ ++ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+++ ++ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+++ ++ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+++ ++ [CLKID_VCLK] = &g12a_vclk.hw,
+++ ++ [CLKID_VCLK2] = &g12a_vclk2.hw,
+++ ++ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+++ ++ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+++ ++ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+++ ++ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+++ ++ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+++ ++ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+++ ++ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+++ ++ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+++ ++ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+++ ++ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+++ ++ [CLKID_HDMI] = &g12a_hdmi.hw,
+++ ++ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+++ ++ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+++ ++ [CLKID_MALI_0] = &g12a_mali_0.hw,
+++ ++ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+++ ++ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+++ ++ [CLKID_MALI_1] = &g12a_mali_1.hw,
+++ ++ [CLKID_MALI] = &g12a_mali.hw,
+++ ++ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+++ ++ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+++ ++ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+++ ++ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+++ ++ [CLKID_CPU_CLK] = &g12b_cpu_clk.hw,
+++ ++ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+++ ++ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+++ ++ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+++ ++ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+++ ++ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+++ ++ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+++ ++ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+++ ++ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+++ ++ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+++ ++ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+++ ++ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+++ ++ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+++ ++ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+++ ++ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+++ ++ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+++ ++ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+++ ++ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+++ ++ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+++ ++ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+++ ++ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+++ ++ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+++ ++ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+++ ++ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+++ ++ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+++ ++ [CLKID_TS] = &g12a_ts.hw,
+++ ++ [CLKID_SYS1_PLL_DCO] = &g12b_sys1_pll_dco.hw,
+++ ++ [CLKID_SYS1_PLL] = &g12b_sys1_pll.hw,
+++ ++ [CLKID_SYS1_PLL_DIV16_EN] = &g12b_sys1_pll_div16_en.hw,
+++ ++ [CLKID_SYS1_PLL_DIV16] = &g12b_sys1_pll_div16.hw,
+++ ++ [CLKID_CPUB_CLK_DYN0_SEL] = &g12b_cpub_clk_premux0.hw,
+++ ++ [CLKID_CPUB_CLK_DYN0_DIV] = &g12b_cpub_clk_mux0_div.hw,
+++ ++ [CLKID_CPUB_CLK_DYN0] = &g12b_cpub_clk_postmux0.hw,
+++ ++ [CLKID_CPUB_CLK_DYN1_SEL] = &g12b_cpub_clk_premux1.hw,
+++ ++ [CLKID_CPUB_CLK_DYN1_DIV] = &g12b_cpub_clk_mux1_div.hw,
+++ ++ [CLKID_CPUB_CLK_DYN1] = &g12b_cpub_clk_postmux1.hw,
+++ ++ [CLKID_CPUB_CLK_DYN] = &g12b_cpub_clk_dyn.hw,
+++ ++ [CLKID_CPUB_CLK] = &g12b_cpub_clk.hw,
+++ ++ [CLKID_CPUB_CLK_DIV16_EN] = &g12b_cpub_clk_div16_en.hw,
+++ ++ [CLKID_CPUB_CLK_DIV16] = &g12b_cpub_clk_div16.hw,
+++ ++ [CLKID_CPUB_CLK_DIV2] = &g12b_cpub_clk_div2.hw,
+++ ++ [CLKID_CPUB_CLK_DIV3] = &g12b_cpub_clk_div3.hw,
+++ ++ [CLKID_CPUB_CLK_DIV4] = &g12b_cpub_clk_div4.hw,
+++ ++ [CLKID_CPUB_CLK_DIV5] = &g12b_cpub_clk_div5.hw,
+++ ++ [CLKID_CPUB_CLK_DIV6] = &g12b_cpub_clk_div6.hw,
+++ ++ [CLKID_CPUB_CLK_DIV7] = &g12b_cpub_clk_div7.hw,
+++ ++ [CLKID_CPUB_CLK_DIV8] = &g12b_cpub_clk_div8.hw,
+++ ++ [CLKID_CPUB_CLK_APB_SEL] = &g12b_cpub_clk_apb_sel.hw,
+++ ++ [CLKID_CPUB_CLK_APB] = &g12b_cpub_clk_apb.hw,
+++ ++ [CLKID_CPUB_CLK_ATB_SEL] = &g12b_cpub_clk_atb_sel.hw,
+++ ++ [CLKID_CPUB_CLK_ATB] = &g12b_cpub_clk_atb.hw,
+++ ++ [CLKID_CPUB_CLK_AXI_SEL] = &g12b_cpub_clk_axi_sel.hw,
+++ ++ [CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
+++ ++ [CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
+++ ++ [CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
+++ ++ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+++ ++ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+++ ++ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+++ ++ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+++ ++ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+++ ++ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+++ ++ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+++ ++ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+++ ++ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+++ ++ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+++ ++ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+++ ++ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
+++ ++};
+++ ++
+++ ++static struct clk_hw *sm1_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
+++ ++ [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
+++ ++ [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &g12a_clk81.hw,
+++ ++ [CLKID_MPLL0] = &g12a_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &g12a_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &g12a_mpll2.hw,
+++ ++ [CLKID_MPLL3] = &g12a_mpll3.hw,
+++ ++ [CLKID_DDR] = &g12a_ddr.hw,
+++ ++ [CLKID_DOS] = &g12a_dos.hw,
+++ ++ [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
+++ ++ [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
+++ ++ [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
+++ ++ [CLKID_ISA] = &g12a_isa.hw,
+++ ++ [CLKID_PL301] = &g12a_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &g12a_periphs.hw,
+++ ++ [CLKID_SPICC0] = &g12a_spicc_0.hw,
+++ ++ [CLKID_I2C] = &g12a_i2c.hw,
+++ ++ [CLKID_SANA] = &g12a_sana.hw,
+++ ++ [CLKID_SD] = &g12a_sd.hw,
+++ ++ [CLKID_RNG0] = &g12a_rng0.hw,
+++ ++ [CLKID_UART0] = &g12a_uart0.hw,
+++ ++ [CLKID_SPICC1] = &g12a_spicc_1.hw,
+++ ++ [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
+++ ++ [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
+++ ++ [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
+++ ++ [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
+++ ++ [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
+++ ++ [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
+++ ++ [CLKID_AUDIO] = &g12a_audio.hw,
+++ ++ [CLKID_ETH] = &g12a_eth_core.hw,
+++ ++ [CLKID_DEMUX] = &g12a_demux.hw,
+++ ++ [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
+++ ++ [CLKID_ADC] = &g12a_adc.hw,
+++ ++ [CLKID_UART1] = &g12a_uart1.hw,
+++ ++ [CLKID_G2D] = &g12a_g2d.hw,
+++ ++ [CLKID_RESET] = &g12a_reset.hw,
+++ ++ [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
+++ ++ [CLKID_PARSER] = &g12a_parser.hw,
+++ ++ [CLKID_USB] = &g12a_usb_general.hw,
+++ ++ [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
+++ ++ [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
+++ ++ [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
+++ ++ [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
+++ ++ [CLKID_BT656] = &g12a_bt656.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
+++ ++ [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
+++ ++ [CLKID_UART2] = &g12a_uart2.hw,
+++ ++ [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
+++ ++ [CLKID_GIC] = &g12a_gic.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
+++ ++ [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
+++ ++ [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
+++ ++ [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
+++ ++ [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
+++ ++ [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
+++ ++ [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
+++ ++ [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
+++ ++ [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
+++ ++ [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
+++ ++ [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
+++ ++ [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
+++ ++ [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
+++ ++ [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
+++ ++ [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
+++ ++ [CLKID_IEC958] = &g12a_iec958_gate.hw,
+++ ++ [CLKID_ENC480P] = &g12a_enc480p.hw,
+++ ++ [CLKID_RNG1] = &g12a_rng1.hw,
+++ ++ [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
+++ ++ [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
+++ ++ [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
+++ ++ [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
+++ ++ [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
+++ ++ [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
+++ ++ [CLKID_DMA] = &g12a_dma.hw,
+++ ++ [CLKID_EFUSE] = &g12a_efuse.hw,
+++ ++ [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
+++ ++ [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
+++ ++ [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
+++ ++ [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0] = &g12a_vpu_0.hw,
+++ ++ [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1] = &g12a_vpu_1.hw,
+++ ++ [CLKID_VPU] = &g12a_vpu.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0] = &g12a_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1] = &g12a_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &g12a_vapb.hw,
+++ ++ [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
+++ ++ [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
+++ ++ [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
+++ ++ [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
+++ ++ [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
+++ ++ [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
+++ ++ [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
+++ ++ [CLKID_VCLK] = &g12a_vclk.hw,
+++ ++ [CLKID_VCLK2] = &g12a_vclk2.hw,
+++ ++ [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
+++ ++ [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
+++ ++ [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
+++ ++ [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
+++ ++ [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
+++ ++ [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
+++ ++ [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
+++ ++ [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
+++ ++ [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
+++ ++ [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
+++ ++ [CLKID_HDMI] = &g12a_hdmi.hw,
+++ ++ [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
+++ ++ [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
+++ ++ [CLKID_MALI_0] = &g12a_mali_0.hw,
+++ ++ [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
+++ ++ [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
+++ ++ [CLKID_MALI_1] = &g12a_mali_1.hw,
+++ ++ [CLKID_MALI] = &g12a_mali.hw,
+++ ++ [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
+++ ++ [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
+++ ++ [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
+++ ++ [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
+++ ++ [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
+++ ++ [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
+++ ++ [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
+++ ++ [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
+++ ++ [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
+++ ++ [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
+++ ++ [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
+++ ++ [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
+++ ++ [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
+++ ++ [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
+++ ++ [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
+++ ++ [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
+++ ++ [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
+++ ++ [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
+++ ++ [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
+++ ++ [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
+++ ++ [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
+++ ++ [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
+++ ++ [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
+++ ++ [CLKID_VDEC_1] = &g12a_vdec_1.hw,
+++ ++ [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
+++ ++ [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
+++ ++ [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
+++ ++ [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
+++ ++ [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
+++ ++ [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
+++ ++ [CLKID_TS_DIV] = &g12a_ts_div.hw,
+++ ++ [CLKID_TS] = &g12a_ts.hw,
+++ ++ [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
+++ ++ [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
+++ ++ [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
+++ ++ [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
+++ ++ [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
+++ ++ [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
+++ ++ [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
+++ ++ [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
+++ ++ [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
+++ ++ [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
+++ ++ [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
+++ ++ [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
+++ ++ [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
+++ ++ [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
+++ ++ [CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
+++ ++ [CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
+++ ++ [CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
+++ ++ [CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
+++ ++ [CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
+++ ++ [CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
+++ ++ [CLKID_NNA_AXI_CLK_SEL] = &sm1_nna_axi_clk_sel.hw,
+++ ++ [CLKID_NNA_AXI_CLK_DIV] = &sm1_nna_axi_clk_div.hw,
+++ ++ [CLKID_NNA_AXI_CLK] = &sm1_nna_axi_clk.hw,
+++ ++ [CLKID_NNA_CORE_CLK_SEL] = &sm1_nna_core_clk_sel.hw,
+++ ++ [CLKID_NNA_CORE_CLK_DIV] = &sm1_nna_core_clk_div.hw,
+++ ++ [CLKID_NNA_CORE_CLK] = &sm1_nna_core_clk.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_SEL] = &g12a_mipi_dsi_pxclk_sel.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK_DIV] = &g12a_mipi_dsi_pxclk_div.hw,
+++ ++ [CLKID_MIPI_DSI_PXCLK] = &g12a_mipi_dsi_pxclk.hw,
};
/* Convenience table to populate regmap in .probe */
static int meson_g12b_dvfs_setup(struct platform_device *pdev)
{
--- -- struct clk_hw **hws = g12b_hw_onecell_data.hws;
+++ ++ struct clk_hw **hws = g12b_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
struct clk_hw *xtal;
static int meson_g12a_dvfs_setup(struct platform_device *pdev)
{
--- -- struct clk_hw **hws = g12a_hw_onecell_data.hws;
+++ ++ struct clk_hw **hws = g12a_hw_clks;
struct device *dev = &pdev->dev;
struct clk *notifier_clk;
int ret;
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
--- -- .hw_onecell_data = &g12a_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = g12a_hw_clks,
+++ ++ .num = ARRAY_SIZE(g12a_hw_clks),
+++ ++ },
.init_regs = g12a_init_regs,
.init_count = ARRAY_SIZE(g12a_init_regs),
},
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
--- -- .hw_onecell_data = &g12b_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = g12b_hw_clks,
+++ ++ .num = ARRAY_SIZE(g12b_hw_clks),
+++ ++ },
},
.dvfs_setup = meson_g12b_dvfs_setup,
};
.eeclkc_data = {
.regmap_clks = g12a_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
--- -- .hw_onecell_data = &sm1_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = sm1_hw_clks,
+++ ++ .num = ARRAY_SIZE(sm1_hw_clks),
+++ ++ },
},
.dvfs_setup = meson_g12a_dvfs_setup,
};
#include <linux/clk-provider.h>
#include <linux/init.h>
-----#include <linux/of_device.h>
+++++#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include "meson-eeclk.h"
#include "vid-pll-div.h"
+++ ++#include <dt-bindings/clock/gxbb-clkc.h>
+++ ++
static DEFINE_SPINLOCK(meson_clk_lock);
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
/* Array of all clocks provided by this provider */
--- --static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
--- -- [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
--- -- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
--- -- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &gxbb_clk81.hw,
--- -- [CLKID_MPLL0] = &gxbb_mpll0.hw,
--- -- [CLKID_MPLL1] = &gxbb_mpll1.hw,
--- -- [CLKID_MPLL2] = &gxbb_mpll2.hw,
--- -- [CLKID_DDR] = &gxbb_ddr.hw,
--- -- [CLKID_DOS] = &gxbb_dos.hw,
--- -- [CLKID_ISA] = &gxbb_isa.hw,
--- -- [CLKID_PL301] = &gxbb_pl301.hw,
--- -- [CLKID_PERIPHS] = &gxbb_periphs.hw,
--- -- [CLKID_SPICC] = &gxbb_spicc.hw,
--- -- [CLKID_I2C] = &gxbb_i2c.hw,
--- -- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
--- -- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
--- -- [CLKID_RNG0] = &gxbb_rng0.hw,
--- -- [CLKID_UART0] = &gxbb_uart0.hw,
--- -- [CLKID_SDHC] = &gxbb_sdhc.hw,
--- -- [CLKID_STREAM] = &gxbb_stream.hw,
--- -- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
--- -- [CLKID_SDIO] = &gxbb_sdio.hw,
--- -- [CLKID_ABUF] = &gxbb_abuf.hw,
--- -- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
--- -- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
--- -- [CLKID_SPI] = &gxbb_spi.hw,
--- -- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
--- -- [CLKID_ETH] = &gxbb_eth.hw,
--- -- [CLKID_DEMUX] = &gxbb_demux.hw,
--- -- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
--- -- [CLKID_IEC958] = &gxbb_iec958.hw,
--- -- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
--- -- [CLKID_AMCLK] = &gxbb_amclk.hw,
--- -- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
--- -- [CLKID_MIXER] = &gxbb_mixer.hw,
--- -- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
--- -- [CLKID_ADC] = &gxbb_adc.hw,
--- -- [CLKID_BLKMV] = &gxbb_blkmv.hw,
--- -- [CLKID_AIU] = &gxbb_aiu.hw,
--- -- [CLKID_UART1] = &gxbb_uart1.hw,
--- -- [CLKID_G2D] = &gxbb_g2d.hw,
--- -- [CLKID_USB0] = &gxbb_usb0.hw,
--- -- [CLKID_USB1] = &gxbb_usb1.hw,
--- -- [CLKID_RESET] = &gxbb_reset.hw,
--- -- [CLKID_NAND] = &gxbb_nand.hw,
--- -- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
--- -- [CLKID_USB] = &gxbb_usb.hw,
--- -- [CLKID_VDIN1] = &gxbb_vdin1.hw,
--- -- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
--- -- [CLKID_EFUSE] = &gxbb_efuse.hw,
--- -- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
--- -- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
--- -- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
--- -- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
--- -- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
--- -- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
--- -- [CLKID_DVIN] = &gxbb_dvin.hw,
--- -- [CLKID_UART2] = &gxbb_uart2.hw,
--- -- [CLKID_SANA] = &gxbb_sana.hw,
--- -- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
--- -- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
--- -- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
--- -- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
--- -- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
--- -- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
--- -- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
--- -- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
--- -- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
--- -- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
--- -- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
--- -- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
--- -- [CLKID_ENC480P] = &gxbb_enc480p.hw,
--- -- [CLKID_RNG1] = &gxbb_rng1.hw,
--- -- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
--- -- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
--- -- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
--- -- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
--- -- [CLKID_EDP] = &gxbb_edp.hw,
--- -- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
--- -- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
--- -- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
--- -- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
--- -- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
--- -- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
--- -- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
--- -- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
--- -- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
--- -- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
--- -- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
--- -- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
--- -- [CLKID_MALI_0] = &gxbb_mali_0.hw,
--- -- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
--- -- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
--- -- [CLKID_MALI_1] = &gxbb_mali_1.hw,
--- -- [CLKID_MALI] = &gxbb_mali.hw,
--- -- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
--- -- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
--- -- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
--- -- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
--- -- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
--- -- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
--- -- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
--- -- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
--- -- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
--- -- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
--- -- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
--- -- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
--- -- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
--- -- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
--- -- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
--- -- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
--- -- [CLKID_VPU] = &gxbb_vpu.hw,
--- -- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
--- -- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
--- -- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
--- -- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
--- -- [CLKID_VAPB] = &gxbb_vapb.hw,
--- -- [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
--- -- [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
--- -- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
--- -- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
--- -- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
--- -- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
--- -- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
--- -- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
--- -- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
--- -- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
--- -- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
--- -- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
--- -- [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
--- -- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
--- -- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
--- -- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
--- -- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
--- -- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
--- -- [CLKID_VCLK] = &gxbb_vclk.hw,
--- -- [CLKID_VCLK2] = &gxbb_vclk2.hw,
--- -- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
--- -- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
--- -- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
--- -- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
--- -- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
--- -- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
--- -- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
--- -- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
--- -- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
--- -- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
--- -- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
--- -- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
--- -- [CLKID_HDMI] = &gxbb_hdmi.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
--- --};
--- --
--- --static struct clk_hw_onecell_data gxl_hw_onecell_data = {
--- -- .hws = {
--- -- [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
--- -- [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
--- -- [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
--- -- [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
--- -- [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
--- -- [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
--- -- [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
--- -- [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
--- -- [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
--- -- [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
--- -- [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
--- -- [CLKID_CLK81] = &gxbb_clk81.hw,
--- -- [CLKID_MPLL0] = &gxbb_mpll0.hw,
--- -- [CLKID_MPLL1] = &gxbb_mpll1.hw,
--- -- [CLKID_MPLL2] = &gxbb_mpll2.hw,
--- -- [CLKID_DDR] = &gxbb_ddr.hw,
--- -- [CLKID_DOS] = &gxbb_dos.hw,
--- -- [CLKID_ISA] = &gxbb_isa.hw,
--- -- [CLKID_PL301] = &gxbb_pl301.hw,
--- -- [CLKID_PERIPHS] = &gxbb_periphs.hw,
--- -- [CLKID_SPICC] = &gxbb_spicc.hw,
--- -- [CLKID_I2C] = &gxbb_i2c.hw,
--- -- [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
--- -- [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
--- -- [CLKID_RNG0] = &gxbb_rng0.hw,
--- -- [CLKID_UART0] = &gxbb_uart0.hw,
--- -- [CLKID_SDHC] = &gxbb_sdhc.hw,
--- -- [CLKID_STREAM] = &gxbb_stream.hw,
--- -- [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
--- -- [CLKID_SDIO] = &gxbb_sdio.hw,
--- -- [CLKID_ABUF] = &gxbb_abuf.hw,
--- -- [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
--- -- [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
--- -- [CLKID_SPI] = &gxbb_spi.hw,
--- -- [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
--- -- [CLKID_ETH] = &gxbb_eth.hw,
--- -- [CLKID_DEMUX] = &gxbb_demux.hw,
--- -- [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
--- -- [CLKID_IEC958] = &gxbb_iec958.hw,
--- -- [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
--- -- [CLKID_AMCLK] = &gxbb_amclk.hw,
--- -- [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
--- -- [CLKID_MIXER] = &gxbb_mixer.hw,
--- -- [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
--- -- [CLKID_ADC] = &gxbb_adc.hw,
--- -- [CLKID_BLKMV] = &gxbb_blkmv.hw,
--- -- [CLKID_AIU] = &gxbb_aiu.hw,
--- -- [CLKID_UART1] = &gxbb_uart1.hw,
--- -- [CLKID_G2D] = &gxbb_g2d.hw,
--- -- [CLKID_USB0] = &gxbb_usb0.hw,
--- -- [CLKID_USB1] = &gxbb_usb1.hw,
--- -- [CLKID_RESET] = &gxbb_reset.hw,
--- -- [CLKID_NAND] = &gxbb_nand.hw,
--- -- [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
--- -- [CLKID_USB] = &gxbb_usb.hw,
--- -- [CLKID_VDIN1] = &gxbb_vdin1.hw,
--- -- [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
--- -- [CLKID_EFUSE] = &gxbb_efuse.hw,
--- -- [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
--- -- [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
--- -- [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
--- -- [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
--- -- [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
--- -- [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
--- -- [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
--- -- [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
--- -- [CLKID_DVIN] = &gxbb_dvin.hw,
--- -- [CLKID_UART2] = &gxbb_uart2.hw,
--- -- [CLKID_SANA] = &gxbb_sana.hw,
--- -- [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
--- -- [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
--- -- [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
--- -- [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
--- -- [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
--- -- [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
--- -- [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
--- -- [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
--- -- [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
--- -- [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
--- -- [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
--- -- [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
--- -- [CLKID_ENC480P] = &gxbb_enc480p.hw,
--- -- [CLKID_RNG1] = &gxbb_rng1.hw,
--- -- [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
--- -- [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
--- -- [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
--- -- [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
--- -- [CLKID_EDP] = &gxbb_edp.hw,
--- -- [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
--- -- [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
--- -- [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
--- -- [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
--- -- [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
--- -- [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
--- -- [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
--- -- [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
--- -- [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
--- -- [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
--- -- [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
--- -- [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
--- -- [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
--- -- [CLKID_MALI_0] = &gxbb_mali_0.hw,
--- -- [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
--- -- [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
--- -- [CLKID_MALI_1] = &gxbb_mali_1.hw,
--- -- [CLKID_MALI] = &gxbb_mali.hw,
--- -- [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
--- -- [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
--- -- [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
--- -- [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
--- -- [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
--- -- [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
--- -- [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
--- -- [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
--- -- [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
--- -- [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
--- -- [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
--- -- [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
--- -- [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
--- -- [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
--- -- [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
--- -- [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
--- -- [CLKID_VPU_0] = &gxbb_vpu_0.hw,
--- -- [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
--- -- [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
--- -- [CLKID_VPU_1] = &gxbb_vpu_1.hw,
--- -- [CLKID_VPU] = &gxbb_vpu.hw,
--- -- [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
--- -- [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
--- -- [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
--- -- [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
--- -- [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
--- -- [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
--- -- [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
--- -- [CLKID_VAPB] = &gxbb_vapb.hw,
--- -- [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
--- -- [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
--- -- [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
--- -- [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
--- -- [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
--- -- [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
--- -- [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
--- -- [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
--- -- [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
--- -- [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
--- -- [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
--- -- [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
--- -- [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
--- -- [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
--- -- [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
--- -- [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
--- -- [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
--- -- [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
--- -- [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
--- -- [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
--- -- [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
--- -- [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
--- -- [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
--- -- [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
--- -- [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
--- -- [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
--- -- [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
--- -- [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
--- -- [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
--- -- [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
--- -- [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
--- -- [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
--- -- [CLKID_VCLK] = &gxbb_vclk.hw,
--- -- [CLKID_VCLK2] = &gxbb_vclk2.hw,
--- -- [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
--- -- [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
--- -- [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
--- -- [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
--- -- [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
--- -- [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
--- -- [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
--- -- [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
--- -- [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
--- -- [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
--- -- [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
--- -- [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
--- -- [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
--- -- [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
--- -- [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
--- -- [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
--- -- [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
--- -- [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
--- -- [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
--- -- [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
--- -- [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
--- -- [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
--- -- [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
--- -- [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
--- -- [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
--- -- [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
--- -- [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
--- -- [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
--- -- [CLKID_HDMI] = &gxbb_hdmi.hw,
--- -- [CLKID_ACODEC] = &gxl_acodec.hw,
--- -- [NR_CLKS] = NULL,
--- -- },
--- -- .num = NR_CLKS,
+++ ++static struct clk_hw *gxbb_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+++ ++ [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+++ ++ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &gxbb_clk81.hw,
+++ ++ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+++ ++ [CLKID_DDR] = &gxbb_ddr.hw,
+++ ++ [CLKID_DOS] = &gxbb_dos.hw,
+++ ++ [CLKID_ISA] = &gxbb_isa.hw,
+++ ++ [CLKID_PL301] = &gxbb_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+++ ++ [CLKID_SPICC] = &gxbb_spicc.hw,
+++ ++ [CLKID_I2C] = &gxbb_i2c.hw,
+++ ++ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+++ ++ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+++ ++ [CLKID_RNG0] = &gxbb_rng0.hw,
+++ ++ [CLKID_UART0] = &gxbb_uart0.hw,
+++ ++ [CLKID_SDHC] = &gxbb_sdhc.hw,
+++ ++ [CLKID_STREAM] = &gxbb_stream.hw,
+++ ++ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+++ ++ [CLKID_SDIO] = &gxbb_sdio.hw,
+++ ++ [CLKID_ABUF] = &gxbb_abuf.hw,
+++ ++ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+++ ++ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+++ ++ [CLKID_SPI] = &gxbb_spi.hw,
+++ ++ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+++ ++ [CLKID_ETH] = &gxbb_eth.hw,
+++ ++ [CLKID_DEMUX] = &gxbb_demux.hw,
+++ ++ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+++ ++ [CLKID_IEC958] = &gxbb_iec958.hw,
+++ ++ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+++ ++ [CLKID_AMCLK] = &gxbb_amclk.hw,
+++ ++ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+++ ++ [CLKID_MIXER] = &gxbb_mixer.hw,
+++ ++ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+++ ++ [CLKID_ADC] = &gxbb_adc.hw,
+++ ++ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+++ ++ [CLKID_AIU] = &gxbb_aiu.hw,
+++ ++ [CLKID_UART1] = &gxbb_uart1.hw,
+++ ++ [CLKID_G2D] = &gxbb_g2d.hw,
+++ ++ [CLKID_USB0] = &gxbb_usb0.hw,
+++ ++ [CLKID_USB1] = &gxbb_usb1.hw,
+++ ++ [CLKID_RESET] = &gxbb_reset.hw,
+++ ++ [CLKID_NAND] = &gxbb_nand.hw,
+++ ++ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+++ ++ [CLKID_USB] = &gxbb_usb.hw,
+++ ++ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+++ ++ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+++ ++ [CLKID_EFUSE] = &gxbb_efuse.hw,
+++ ++ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+++ ++ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+++ ++ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+++ ++ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+++ ++ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+++ ++ [CLKID_DVIN] = &gxbb_dvin.hw,
+++ ++ [CLKID_UART2] = &gxbb_uart2.hw,
+++ ++ [CLKID_SANA] = &gxbb_sana.hw,
+++ ++ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+++ ++ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+++ ++ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+++ ++ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+++ ++ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+++ ++ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+++ ++ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+++ ++ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+++ ++ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+++ ++ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+++ ++ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+++ ++ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+++ ++ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+++ ++ [CLKID_RNG1] = &gxbb_rng1.hw,
+++ ++ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+++ ++ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+++ ++ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+++ ++ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+++ ++ [CLKID_EDP] = &gxbb_edp.hw,
+++ ++ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+++ ++ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+++ ++ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+++ ++ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+++ ++ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+++ ++ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+++ ++ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+++ ++ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+++ ++ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+++ ++ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+++ ++ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+++ ++ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+++ ++ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+++ ++ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+++ ++ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+++ ++ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+++ ++ [CLKID_MALI] = &gxbb_mali.hw,
+++ ++ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+++ ++ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+++ ++ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+++ ++ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+++ ++ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+++ ++ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+++ ++ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+++ ++ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+++ ++ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+++ ++ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+++ ++ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+++ ++ [CLKID_VPU] = &gxbb_vpu.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &gxbb_vapb.hw,
+++ ++ [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
+++ ++ [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+++ ++ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+++ ++ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+++ ++ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+++ ++ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+++ ++ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+++ ++ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+++ ++ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+++ ++ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+++ ++ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
+++ ++ [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
+++ ++ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+++ ++ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+++ ++ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+++ ++ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+++ ++ [CLKID_VCLK] = &gxbb_vclk.hw,
+++ ++ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+++ ++ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+++ ++ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+++ ++ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+++ ++ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+++ ++ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+++ ++ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+++ ++ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+++ ++ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+++ ++ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+++ ++ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+++ ++ [CLKID_HDMI] = &gxbb_hdmi.hw,
+++ ++};
+++ ++
+++ ++static struct clk_hw *gxl_hw_clks[] = {
+++ ++ [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
+++ ++ [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
+++ ++ [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
+++ ++ [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
+++ ++ [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
+++ ++ [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
+++ ++ [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
+++ ++ [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
+++ ++ [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
+++ ++ [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
+++ ++ [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
+++ ++ [CLKID_CLK81] = &gxbb_clk81.hw,
+++ ++ [CLKID_MPLL0] = &gxbb_mpll0.hw,
+++ ++ [CLKID_MPLL1] = &gxbb_mpll1.hw,
+++ ++ [CLKID_MPLL2] = &gxbb_mpll2.hw,
+++ ++ [CLKID_DDR] = &gxbb_ddr.hw,
+++ ++ [CLKID_DOS] = &gxbb_dos.hw,
+++ ++ [CLKID_ISA] = &gxbb_isa.hw,
+++ ++ [CLKID_PL301] = &gxbb_pl301.hw,
+++ ++ [CLKID_PERIPHS] = &gxbb_periphs.hw,
+++ ++ [CLKID_SPICC] = &gxbb_spicc.hw,
+++ ++ [CLKID_I2C] = &gxbb_i2c.hw,
+++ ++ [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
+++ ++ [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
+++ ++ [CLKID_RNG0] = &gxbb_rng0.hw,
+++ ++ [CLKID_UART0] = &gxbb_uart0.hw,
+++ ++ [CLKID_SDHC] = &gxbb_sdhc.hw,
+++ ++ [CLKID_STREAM] = &gxbb_stream.hw,
+++ ++ [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
+++ ++ [CLKID_SDIO] = &gxbb_sdio.hw,
+++ ++ [CLKID_ABUF] = &gxbb_abuf.hw,
+++ ++ [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
+++ ++ [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
+++ ++ [CLKID_SPI] = &gxbb_spi.hw,
+++ ++ [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
+++ ++ [CLKID_ETH] = &gxbb_eth.hw,
+++ ++ [CLKID_DEMUX] = &gxbb_demux.hw,
+++ ++ [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
+++ ++ [CLKID_IEC958] = &gxbb_iec958.hw,
+++ ++ [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
+++ ++ [CLKID_AMCLK] = &gxbb_amclk.hw,
+++ ++ [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
+++ ++ [CLKID_MIXER] = &gxbb_mixer.hw,
+++ ++ [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
+++ ++ [CLKID_ADC] = &gxbb_adc.hw,
+++ ++ [CLKID_BLKMV] = &gxbb_blkmv.hw,
+++ ++ [CLKID_AIU] = &gxbb_aiu.hw,
+++ ++ [CLKID_UART1] = &gxbb_uart1.hw,
+++ ++ [CLKID_G2D] = &gxbb_g2d.hw,
+++ ++ [CLKID_USB0] = &gxbb_usb0.hw,
+++ ++ [CLKID_USB1] = &gxbb_usb1.hw,
+++ ++ [CLKID_RESET] = &gxbb_reset.hw,
+++ ++ [CLKID_NAND] = &gxbb_nand.hw,
+++ ++ [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
+++ ++ [CLKID_USB] = &gxbb_usb.hw,
+++ ++ [CLKID_VDIN1] = &gxbb_vdin1.hw,
+++ ++ [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
+++ ++ [CLKID_EFUSE] = &gxbb_efuse.hw,
+++ ++ [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
+++ ++ [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
+++ ++ [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
+++ ++ [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
+++ ++ [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
+++ ++ [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
+++ ++ [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
+++ ++ [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
+++ ++ [CLKID_DVIN] = &gxbb_dvin.hw,
+++ ++ [CLKID_UART2] = &gxbb_uart2.hw,
+++ ++ [CLKID_SANA] = &gxbb_sana.hw,
+++ ++ [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
+++ ++ [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
+++ ++ [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
+++ ++ [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
+++ ++ [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
+++ ++ [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
+++ ++ [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
+++ ++ [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
+++ ++ [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
+++ ++ [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
+++ ++ [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
+++ ++ [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
+++ ++ [CLKID_ENC480P] = &gxbb_enc480p.hw,
+++ ++ [CLKID_RNG1] = &gxbb_rng1.hw,
+++ ++ [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
+++ ++ [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
+++ ++ [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
+++ ++ [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
+++ ++ [CLKID_EDP] = &gxbb_edp.hw,
+++ ++ [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
+++ ++ [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
+++ ++ [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
+++ ++ [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
+++ ++ [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
+++ ++ [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
+++ ++ [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
+++ ++ [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
+++ ++ [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
+++ ++ [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
+++ ++ [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
+++ ++ [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
+++ ++ [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
+++ ++ [CLKID_MALI_0] = &gxbb_mali_0.hw,
+++ ++ [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
+++ ++ [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
+++ ++ [CLKID_MALI_1] = &gxbb_mali_1.hw,
+++ ++ [CLKID_MALI] = &gxbb_mali.hw,
+++ ++ [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
+++ ++ [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
+++ ++ [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
+++ ++ [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
+++ ++ [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
+++ ++ [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
+++ ++ [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
+++ ++ [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
+++ ++ [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
+++ ++ [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
+++ ++ [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
+++ ++ [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
+++ ++ [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
+++ ++ [CLKID_VPU_0] = &gxbb_vpu_0.hw,
+++ ++ [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
+++ ++ [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
+++ ++ [CLKID_VPU_1] = &gxbb_vpu_1.hw,
+++ ++ [CLKID_VPU] = &gxbb_vpu.hw,
+++ ++ [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
+++ ++ [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
+++ ++ [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
+++ ++ [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
+++ ++ [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
+++ ++ [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
+++ ++ [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
+++ ++ [CLKID_VAPB] = &gxbb_vapb.hw,
+++ ++ [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
+++ ++ [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
+++ ++ [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
+++ ++ [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
+++ ++ [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
+++ ++ [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
+++ ++ [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
+++ ++ [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
+++ ++ [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
+++ ++ [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
+++ ++ [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
+++ ++ [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
+++ ++ [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
+++ ++ [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
+++ ++ [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+++ ++ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+++ ++ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+++ ++ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
+++ ++ [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
+++ ++ [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
+++ ++ [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
+++ ++ [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
+++ ++ [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
+++ ++ [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
+++ ++ [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
+++ ++ [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
+++ ++ [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
+++ ++ [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
+++ ++ [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
+++ ++ [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
+++ ++ [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
+++ ++ [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
+++ ++ [CLKID_VCLK] = &gxbb_vclk.hw,
+++ ++ [CLKID_VCLK2] = &gxbb_vclk2.hw,
+++ ++ [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
+++ ++ [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
+++ ++ [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
+++ ++ [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
+++ ++ [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
+++ ++ [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
+++ ++ [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
+++ ++ [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
+++ ++ [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
+++ ++ [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
+++ ++ [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
+++ ++ [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
+++ ++ [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
+++ ++ [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
+++ ++ [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
+++ ++ [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
+++ ++ [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
+++ ++ [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
+++ ++ [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
+++ ++ [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
+++ ++ [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
+++ ++ [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
+++ ++ [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
+++ ++ [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
+++ ++ [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
+++ ++ [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
+++ ++ [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
+++ ++ [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
+++ ++ [CLKID_HDMI] = &gxbb_hdmi.hw,
+++ ++ [CLKID_ACODEC] = &gxl_acodec.hw,
};
static struct clk_regmap *const gxbb_clk_regmaps[] = {
static const struct meson_eeclkc_data gxbb_clkc_data = {
.regmap_clks = gxbb_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
--- -- .hw_onecell_data = &gxbb_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = gxbb_hw_clks,
+++ ++ .num = ARRAY_SIZE(gxbb_hw_clks),
+++ ++ },
};
static const struct meson_eeclkc_data gxl_clkc_data = {
.regmap_clks = gxl_clk_regmaps,
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
--- -- .hw_onecell_data = &gxl_hw_onecell_data,
+++ ++ .hw_clks = {
+++ ++ .hws = gxl_hw_clks,
+++ ++ .num = ARRAY_SIZE(gxl_hw_clks),
+++ ++ },
};
static const struct of_device_id clkc_match_table[] = {
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/mfd/syscon.h>
-----#include <linux/of_device.h>
+++++#include <linux/of.h>
#include <linux/module.h>
#include <linux/slab.h>
data->clks[clkid]->map = regmap;
/* Register all clks */
--- -- for (clkid = 0; clkid < data->hw_data->num; clkid++) {
--- -- if (!data->hw_data->hws[clkid])
+++ ++ for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
+++ ++ if (!data->hw_clks.hws[clkid])
continue;
--- -- ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
+++ ++ ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
--- -- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
--- -- (void *) data->hw_data);
+++ ++ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
MODULE_LICENSE("GPL v2");
*/
#include <linux/clk-provider.h>
-----#include <linux/of_device.h>
+++++#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
for (i = 0; i < data->regmap_clk_num; i++)
data->regmap_clks[i]->map = map;
--- -- for (i = 0; i < data->hw_onecell_data->num; i++) {
+++ ++ for (i = 0; i < data->hw_clks.num; i++) {
/* array might be sparse */
--- -- if (!data->hw_onecell_data->hws[i])
+++ ++ if (!data->hw_clks.hws[i])
continue;
--- -- ret = devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]);
+++ ++ ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
--- -- return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
--- -- data->hw_onecell_data);
+++ ++ return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
MODULE_LICENSE("GPL v2");
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/of.h>
-----#include <linux/of_device.h>
#include <linux/of_address.h>
+++++#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk3568-cru.h>
#include "clk.h"
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
+++++ RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
----- RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
+++++ RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
{ /* sentinel */ },
};
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-----#include <linux/of_device.h>
+++++#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rockchip,rv1126-cru.h>
#include "clk.h"
PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+++++ PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+++++ static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
+++++ MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
+++++ RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
+++++
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
/*
* Clock-Architecture Diagram 2
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
RV1126_CLKGATE_CON(11), 1, GFLAGS),
+++++ /*
+++++ * Clock-Architecture Diagram 9
+++++ */
+++++ /* PD_VO */
+++++ COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
+++++ RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
+++++ RV1126_CLKGATE_CON(14), 0, GFLAGS),
+++++ COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
+++++ RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
+++++ RV1126_CLKGATE_CON(14), 1, GFLAGS),
+++++ COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
+++++ RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
+++++ RV1126_CLKGATE_CON(14), 2, GFLAGS),
+++++ GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(14), 6, GFLAGS),
+++++ GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(14), 7, GFLAGS),
+++++ COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
+++++ RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
+++++ RV1126_CLKGATE_CON(14), 8, GFLAGS),
+++++ GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(14), 9, GFLAGS),
+++++ GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(14), 10, GFLAGS),
+++++ COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
+++++ RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
+++++ RV1126_CLKGATE_CON(14), 11, GFLAGS),
+++++ COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
+++++ CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
+++++ RV1126_CLKGATE_CON(14), 12, GFLAGS,
+++++ &rv1126_dclk_vop_fracmux),
+++++ GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
+++++ RV1126_CLKGATE_CON(14), 13, GFLAGS),
+++++ GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(14), 14, GFLAGS),
+++++ GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(12), 7, GFLAGS),
+++++ GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
+++++ RV1126_CLKGATE_CON(12), 8, GFLAGS),
+++++ COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
+++++ RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
+++++ RV1126_CLKGATE_CON(12), 9, GFLAGS),
+++++
/*
* Clock-Architecture Diagram 12
*/
GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
RV1126_CLKGATE_CON(9), 3, GFLAGS),
+++++ /*
+++++ * Clock-Architecture Diagram 9
+++++ */
+++++ /* PD_VO */
+++++ GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
+++++ RV1126_CLKGATE_CON(14), 3, GFLAGS),
+++++ GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
+++++ RV1126_CLKGATE_CON(14), 4, GFLAGS),
+++++ GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
+++++ RV1126_CLKGATE_CON(14), 5, GFLAGS),
+++++
/*
* Clock-Architecture Diagram 12
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of.h>
-----#include <linux/of_device.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
spin_lock_init(&data->lock);
---- - r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
---- - if (!r)
---- - return -EINVAL;
---- - /* one clock/reset pair per word */
---- - count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
---- - data->membase = devm_ioremap_resource(&pdev->dev, r);
++++ + data->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
if (IS_ERR(data->membase))
return PTR_ERR(data->membase);
++++ + /* one clock/reset pair per word */
++++ + count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
++++ +
clk_data = &data->clk_data;
clk_data->clk_num = count;
clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
-----#include <linux/of_device.h>
+++++#include <linux/of_platform.h>
#include <linux/clk/tegra.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset-controller.h>
-- ---#include <linux/string.h>
++ +++#include <linux/string_helpers.h>
#include <soc/tegra/fuse.h>
struct device_node *np;
char *node_name;
-- --- node_name = kstrdup(hw->init->name, GFP_KERNEL);
++ +++ node_name = kstrdup_and_replace(hw->init->name, '_', '-', GFP_KERNEL);
if (!node_name)
return NULL;
-- --- strreplace(node_name, '_', '-');
-- ---
for_each_child_of_node(tegra_car_np, np) {
if (!strcmp(np->name, node_name))
break;
projects / J-linux.git / commitdiff