include/linux/nvme.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Definitions for the NVM Express interface
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #ifndef _LINUX_NVME_H
   8 #define _LINUX_NVME_H
   9
  10 #include <linux/bits.h>
  11 #include <linux/types.h>
  12 #include <linux/uuid.h>
  13
  14 /* NQN names in commands fields specified one size */
  15 #define NVMF_NQN_FIELD_LEN      256
  16
  17 /* However the max length of a qualified name is another size */
  18 #define NVMF_NQN_SIZE           223
  19
  20 #define NVMF_TRSVCID_SIZE       32
  21 #define NVMF_TRADDR_SIZE        256
  22 #define NVMF_TSAS_SIZE          256
  23
  24 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
  25
  26 #define NVME_NSID_ALL           0xffffffff
  27
  28 /* Special NSSR value, 'NVMe' */
  29 #define NVME_SUBSYS_RESET       0x4E564D65
  30
  31 enum nvme_subsys_type {
  32         /* Referral to another discovery type target subsystem */
  33         NVME_NQN_DISC   = 1,
  34
  35         /* NVME type target subsystem */
  36         NVME_NQN_NVME   = 2,
  37
  38         /* Current discovery type target subsystem */
  39         NVME_NQN_CURR   = 3,
  40 };
  41
  42 enum nvme_ctrl_type {
  43         NVME_CTRL_IO    = 1,            /* I/O controller */
  44         NVME_CTRL_DISC  = 2,            /* Discovery controller */
  45         NVME_CTRL_ADMIN = 3,            /* Administrative controller */
  46 };
  47
  48 enum nvme_dctype {
  49         NVME_DCTYPE_NOT_REPORTED        = 0,
  50         NVME_DCTYPE_DDC                 = 1, /* Direct Discovery Controller */
  51         NVME_DCTYPE_CDC                 = 2, /* Central Discovery Controller */
  52 };
  53
  54 /* Address Family codes for Discovery Log Page entry ADRFAM field */
  55 enum {
  56         NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
  57         NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
  58         NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
  59         NVMF_ADDR_FAMILY_IB     = 3,    /* InfiniBand */
  60         NVMF_ADDR_FAMILY_FC     = 4,    /* Fibre Channel */
  61         NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
  62         NVMF_ADDR_FAMILY_MAX,
  63 };
  64
  65 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
  66 enum {
  67         NVMF_TRTYPE_RDMA        = 1,    /* RDMA */
  68         NVMF_TRTYPE_FC          = 2,    /* Fibre Channel */
  69         NVMF_TRTYPE_TCP         = 3,    /* TCP/IP */
  70         NVMF_TRTYPE_LOOP        = 254,  /* Reserved for host usage */
  71         NVMF_TRTYPE_MAX,
  72 };
  73
  74 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
  75 enum {
  76         NVMF_TREQ_NOT_SPECIFIED = 0,            /* Not specified */
  77         NVMF_TREQ_REQUIRED      = 1,            /* Required */
  78         NVMF_TREQ_NOT_REQUIRED  = 2,            /* Not Required */
  79 #define NVME_TREQ_SECURE_CHANNEL_MASK \
  80         (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
  81
  82         NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
  83 };
  84
  85 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
  86  * RDMA_QPTYPE field
  87  */
  88 enum {
  89         NVMF_RDMA_QPTYPE_CONNECTED      = 1, /* Reliable Connected */
  90         NVMF_RDMA_QPTYPE_DATAGRAM       = 2, /* Reliable Datagram */
  91         NVMF_RDMA_QPTYPE_INVALID        = 0xff,
  92 };
  93
  94 /* RDMA Provider Type codes for Discovery Log Page entry TSAS
  95  * RDMA_PRTYPE field
  96  */
  97 enum {
  98         NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
  99         NVMF_RDMA_PRTYPE_IB             = 2, /* InfiniBand */
 100         NVMF_RDMA_PRTYPE_ROCE           = 3, /* InfiniBand RoCE */
 101         NVMF_RDMA_PRTYPE_ROCEV2         = 4, /* InfiniBand RoCEV2 */
 102         NVMF_RDMA_PRTYPE_IWARP          = 5, /* IWARP */
 103 };
 104
 105 /* RDMA Connection Management Service Type codes for Discovery Log Page
 106  * entry TSAS RDMA_CMS field
 107  */
 108 enum {
 109         NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
 110 };
 111
 112 /* TSAS SECTYPE for TCP transport */
 113 enum {
 114         NVMF_TCP_SECTYPE_NONE = 0, /* No Security */
 115         NVMF_TCP_SECTYPE_TLS12 = 1, /* TLSv1.2, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
 116         NVMF_TCP_SECTYPE_TLS13 = 2, /* TLSv1.3, NVMe-oF 1.1 and NVMe-TCP 3.6.1.1 */
 117         NVMF_TCP_SECTYPE_INVALID = 0xff,
 118 };
 119
 120 #define NVME_AQ_DEPTH           32
 121 #define NVME_NR_AEN_COMMANDS    1
 122 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
 123
 124 /*
 125  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
 126  * NVM-Express 1.2 specification, section 4.1.2.
 127  */
 128 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
 129
 130 enum {
 131         NVME_REG_CAP    = 0x0000,       /* Controller Capabilities */
 132         NVME_REG_VS     = 0x0008,       /* Version */
 133         NVME_REG_INTMS  = 0x000c,       /* Interrupt Mask Set */
 134         NVME_REG_INTMC  = 0x0010,       /* Interrupt Mask Clear */
 135         NVME_REG_CC     = 0x0014,       /* Controller Configuration */
 136         NVME_REG_CSTS   = 0x001c,       /* Controller Status */
 137         NVME_REG_NSSR   = 0x0020,       /* NVM Subsystem Reset */
 138         NVME_REG_AQA    = 0x0024,       /* Admin Queue Attributes */
 139         NVME_REG_ASQ    = 0x0028,       /* Admin SQ Base Address */
 140         NVME_REG_ACQ    = 0x0030,       /* Admin CQ Base Address */
 141         NVME_REG_CMBLOC = 0x0038,       /* Controller Memory Buffer Location */
 142         NVME_REG_CMBSZ  = 0x003c,       /* Controller Memory Buffer Size */
 143         NVME_REG_BPINFO = 0x0040,       /* Boot Partition Information */
 144         NVME_REG_BPRSEL = 0x0044,       /* Boot Partition Read Select */
 145         NVME_REG_BPMBL  = 0x0048,       /* Boot Partition Memory Buffer
 146                                          * Location
 147                                          */
 148         NVME_REG_CMBMSC = 0x0050,       /* Controller Memory Buffer Memory
 149                                          * Space Control
 150                                          */
 151         NVME_REG_CRTO   = 0x0068,       /* Controller Ready Timeouts */
 152         NVME_REG_PMRCAP = 0x0e00,       /* Persistent Memory Capabilities */
 153         NVME_REG_PMRCTL = 0x0e04,       /* Persistent Memory Region Control */
 154         NVME_REG_PMRSTS = 0x0e08,       /* Persistent Memory Region Status */
 155         NVME_REG_PMREBS = 0x0e0c,       /* Persistent Memory Region Elasticity
 156                                          * Buffer Size
 157                                          */
 158         NVME_REG_PMRSWTP = 0x0e10,      /* Persistent Memory Region Sustained
 159                                          * Write Throughput
 160                                          */
 161         NVME_REG_DBS    = 0x1000,       /* SQ 0 Tail Doorbell */
 162 };
 163
 164 #define NVME_CAP_MQES(cap)      ((cap) & 0xffff)
 165 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
 166 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
 167 #define NVME_CAP_NSSRC(cap)     (((cap) >> 36) & 0x1)
 168 #define NVME_CAP_CSS(cap)       (((cap) >> 37) & 0xff)
 169 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
 170 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
 171 #define NVME_CAP_CMBS(cap)      (((cap) >> 57) & 0x1)
 172
 173 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
 174 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
 175
 176 #define NVME_CRTO_CRIMT(crto)   ((crto) >> 16)
 177 #define NVME_CRTO_CRWMT(crto)   ((crto) & 0xffff)
 178
 179 enum {
 180         NVME_CMBSZ_SQS          = 1 << 0,
 181         NVME_CMBSZ_CQS          = 1 << 1,
 182         NVME_CMBSZ_LISTS        = 1 << 2,
 183         NVME_CMBSZ_RDS          = 1 << 3,
 184         NVME_CMBSZ_WDS          = 1 << 4,
 185
 186         NVME_CMBSZ_SZ_SHIFT     = 12,
 187         NVME_CMBSZ_SZ_MASK      = 0xfffff,
 188
 189         NVME_CMBSZ_SZU_SHIFT    = 8,
 190         NVME_CMBSZ_SZU_MASK     = 0xf,
 191 };
 192
 193 /*
 194  * Submission and Completion Queue Entry Sizes for the NVM command set.
 195  * (In bytes and specified as a power of two (2^n)).
 196  */
 197 #define NVME_ADM_SQES       6
 198 #define NVME_NVM_IOSQES         6
 199 #define NVME_NVM_IOCQES         4
 200
 201 enum {
 202         NVME_CC_ENABLE          = 1 << 0,
 203         NVME_CC_EN_SHIFT        = 0,
 204         NVME_CC_CSS_SHIFT       = 4,
 205         NVME_CC_MPS_SHIFT       = 7,
 206         NVME_CC_AMS_SHIFT       = 11,
 207         NVME_CC_SHN_SHIFT       = 14,
 208         NVME_CC_IOSQES_SHIFT    = 16,
 209         NVME_CC_IOCQES_SHIFT    = 20,
 210         NVME_CC_CSS_NVM         = 0 << NVME_CC_CSS_SHIFT,
 211         NVME_CC_CSS_CSI         = 6 << NVME_CC_CSS_SHIFT,
 212         NVME_CC_CSS_MASK        = 7 << NVME_CC_CSS_SHIFT,
 213         NVME_CC_AMS_RR          = 0 << NVME_CC_AMS_SHIFT,
 214         NVME_CC_AMS_WRRU        = 1 << NVME_CC_AMS_SHIFT,
 215         NVME_CC_AMS_VS          = 7 << NVME_CC_AMS_SHIFT,
 216         NVME_CC_SHN_NONE        = 0 << NVME_CC_SHN_SHIFT,
 217         NVME_CC_SHN_NORMAL      = 1 << NVME_CC_SHN_SHIFT,
 218         NVME_CC_SHN_ABRUPT      = 2 << NVME_CC_SHN_SHIFT,
 219         NVME_CC_SHN_MASK        = 3 << NVME_CC_SHN_SHIFT,
 220         NVME_CC_IOSQES          = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
 221         NVME_CC_IOCQES          = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
 222         NVME_CC_CRIME           = 1 << 24,
 223 };
 224
 225 enum {
 226         NVME_CSTS_RDY           = 1 << 0,
 227         NVME_CSTS_CFS           = 1 << 1,
 228         NVME_CSTS_NSSRO         = 1 << 4,
 229         NVME_CSTS_PP            = 1 << 5,
 230         NVME_CSTS_SHST_NORMAL   = 0 << 2,
 231         NVME_CSTS_SHST_OCCUR    = 1 << 2,
 232         NVME_CSTS_SHST_CMPLT    = 2 << 2,
 233         NVME_CSTS_SHST_MASK     = 3 << 2,
 234 };
 235
 236 enum {
 237         NVME_CMBMSC_CRE         = 1 << 0,
 238         NVME_CMBMSC_CMSE        = 1 << 1,
 239 };
 240
 241 enum {
 242         NVME_CAP_CSS_NVM        = 1 << 0,
 243         NVME_CAP_CSS_CSI        = 1 << 6,
 244 };
 245
 246 enum {
 247         NVME_CAP_CRMS_CRWMS     = 1ULL << 59,
 248         NVME_CAP_CRMS_CRIMS     = 1ULL << 60,
 249 };
 250
 251 struct nvme_id_power_state {
 252         __le16                  max_power;      /* centiwatts */
 253         __u8                    rsvd2;
 254         __u8                    flags;
 255         __le32                  entry_lat;      /* microseconds */
 256         __le32                  exit_lat;       /* microseconds */
 257         __u8                    read_tput;
 258         __u8                    read_lat;
 259         __u8                    write_tput;
 260         __u8                    write_lat;
 261         __le16                  idle_power;
 262         __u8                    idle_scale;
 263         __u8                    rsvd19;
 264         __le16                  active_power;
 265         __u8                    active_work_scale;
 266         __u8                    rsvd23[9];
 267 };
 268
 269 enum {
 270         NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
 271         NVME_PS_FLAGS_NON_OP_STATE      = 1 << 1,
 272 };
 273
 274 enum nvme_ctrl_attr {
 275         NVME_CTRL_ATTR_HID_128_BIT      = (1 << 0),
 276         NVME_CTRL_ATTR_TBKAS            = (1 << 6),
 277         NVME_CTRL_ATTR_ELBAS            = (1 << 15),
 278 };
 279
 280 struct nvme_id_ctrl {
 281         __le16                  vid;
 282         __le16                  ssvid;
 283         char                    sn[20];
 284         char                    mn[40];
 285         char                    fr[8];
 286         __u8                    rab;
 287         __u8                    ieee[3];
 288         __u8                    cmic;
 289         __u8                    mdts;
 290         __le16                  cntlid;
 291         __le32                  ver;
 292         __le32                  rtd3r;
 293         __le32                  rtd3e;
 294         __le32                  oaes;
 295         __le32                  ctratt;
 296         __u8                    rsvd100[11];
 297         __u8                    cntrltype;
 298         __u8                    fguid[16];
 299         __le16                  crdt1;
 300         __le16                  crdt2;
 301         __le16                  crdt3;
 302         __u8                    rsvd134[122];
 303         __le16                  oacs;
 304         __u8                    acl;
 305         __u8                    aerl;
 306         __u8                    frmw;
 307         __u8                    lpa;
 308         __u8                    elpe;
 309         __u8                    npss;
 310         __u8                    avscc;
 311         __u8                    apsta;
 312         __le16                  wctemp;
 313         __le16                  cctemp;
 314         __le16                  mtfa;
 315         __le32                  hmpre;
 316         __le32                  hmmin;
 317         __u8                    tnvmcap[16];
 318         __u8                    unvmcap[16];
 319         __le32                  rpmbs;
 320         __le16                  edstt;
 321         __u8                    dsto;
 322         __u8                    fwug;
 323         __le16                  kas;
 324         __le16                  hctma;
 325         __le16                  mntmt;
 326         __le16                  mxtmt;
 327         __le32                  sanicap;
 328         __le32                  hmminds;
 329         __le16                  hmmaxd;
 330         __u8                    rsvd338[4];
 331         __u8                    anatt;
 332         __u8                    anacap;
 333         __le32                  anagrpmax;
 334         __le32                  nanagrpid;
 335         __u8                    rsvd352[160];
 336         __u8                    sqes;
 337         __u8                    cqes;
 338         __le16                  maxcmd;
 339         __le32                  nn;
 340         __le16                  oncs;
 341         __le16                  fuses;
 342         __u8                    fna;
 343         __u8                    vwc;
 344         __le16                  awun;
 345         __le16                  awupf;
 346         __u8                    nvscc;
 347         __u8                    nwpc;
 348         __le16                  acwu;
 349         __u8                    rsvd534[2];
 350         __le32                  sgls;
 351         __le32                  mnan;
 352         __u8                    rsvd544[224];
 353         char                    subnqn[256];
 354         __u8                    rsvd1024[768];
 355         __le32                  ioccsz;
 356         __le32                  iorcsz;
 357         __le16                  icdoff;
 358         __u8                    ctrattr;
 359         __u8                    msdbd;
 360         __u8                    rsvd1804[2];
 361         __u8                    dctype;
 362         __u8                    rsvd1807[241];
 363         struct nvme_id_power_state      psd[32];
 364         __u8                    vs[1024];
 365 };
 366
 367 enum {
 368         NVME_CTRL_CMIC_MULTI_PORT               = 1 << 0,
 369         NVME_CTRL_CMIC_MULTI_CTRL               = 1 << 1,
 370         NVME_CTRL_CMIC_ANA                      = 1 << 3,
 371         NVME_CTRL_ONCS_COMPARE                  = 1 << 0,
 372         NVME_CTRL_ONCS_WRITE_UNCORRECTABLE      = 1 << 1,
 373         NVME_CTRL_ONCS_DSM                      = 1 << 2,
 374         NVME_CTRL_ONCS_WRITE_ZEROES             = 1 << 3,
 375         NVME_CTRL_ONCS_RESERVATIONS             = 1 << 5,
 376         NVME_CTRL_ONCS_TIMESTAMP                = 1 << 6,
 377         NVME_CTRL_VWC_PRESENT                   = 1 << 0,
 378         NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
 379         NVME_CTRL_OACS_NS_MNGT_SUPP             = 1 << 3,
 380         NVME_CTRL_OACS_DIRECTIVES               = 1 << 5,
 381         NVME_CTRL_OACS_DBBUF_SUPP               = 1 << 8,
 382         NVME_CTRL_LPA_CMD_EFFECTS_LOG           = 1 << 1,
 383         NVME_CTRL_CTRATT_128_ID                 = 1 << 0,
 384         NVME_CTRL_CTRATT_NON_OP_PSP             = 1 << 1,
 385         NVME_CTRL_CTRATT_NVM_SETS               = 1 << 2,
 386         NVME_CTRL_CTRATT_READ_RECV_LVLS         = 1 << 3,
 387         NVME_CTRL_CTRATT_ENDURANCE_GROUPS       = 1 << 4,
 388         NVME_CTRL_CTRATT_PREDICTABLE_LAT        = 1 << 5,
 389         NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
 390         NVME_CTRL_CTRATT_UUID_LIST              = 1 << 9,
 391 };
 392
 393 struct nvme_lbaf {
 394         __le16                  ms;
 395         __u8                    ds;
 396         __u8                    rp;
 397 };
 398
 399 struct nvme_id_ns {
 400         __le64                  nsze;
 401         __le64                  ncap;
 402         __le64                  nuse;
 403         __u8                    nsfeat;
 404         __u8                    nlbaf;
 405         __u8                    flbas;
 406         __u8                    mc;
 407         __u8                    dpc;
 408         __u8                    dps;
 409         __u8                    nmic;
 410         __u8                    rescap;
 411         __u8                    fpi;
 412         __u8                    dlfeat;
 413         __le16                  nawun;
 414         __le16                  nawupf;
 415         __le16                  nacwu;
 416         __le16                  nabsn;
 417         __le16                  nabo;
 418         __le16                  nabspf;
 419         __le16                  noiob;
 420         __u8                    nvmcap[16];
 421         __le16                  npwg;
 422         __le16                  npwa;
 423         __le16                  npdg;
 424         __le16                  npda;
 425         __le16                  nows;
 426         __u8                    rsvd74[18];
 427         __le32                  anagrpid;
 428         __u8                    rsvd96[3];
 429         __u8                    nsattr;
 430         __le16                  nvmsetid;
 431         __le16                  endgid;
 432         __u8                    nguid[16];
 433         __u8                    eui64[8];
 434         struct nvme_lbaf        lbaf[64];
 435         __u8                    vs[3712];
 436 };
 437
 438 /* I/O Command Set Independent Identify Namespace Data Structure */
 439 struct nvme_id_ns_cs_indep {
 440         __u8                    nsfeat;
 441         __u8                    nmic;
 442         __u8                    rescap;
 443         __u8                    fpi;
 444         __le32                  anagrpid;
 445         __u8                    nsattr;
 446         __u8                    rsvd9;
 447         __le16                  nvmsetid;
 448         __le16                  endgid;
 449         __u8                    nstat;
 450         __u8                    rsvd15[4081];
 451 };
 452
 453 struct nvme_zns_lbafe {
 454         __le64                  zsze;
 455         __u8                    zdes;
 456         __u8                    rsvd9[7];
 457 };
 458
 459 struct nvme_id_ns_zns {
 460         __le16                  zoc;
 461         __le16                  ozcs;
 462         __le32                  mar;
 463         __le32                  mor;
 464         __le32                  rrl;
 465         __le32                  frl;
 466         __u8                    rsvd20[2796];
 467         struct nvme_zns_lbafe   lbafe[64];
 468         __u8                    vs[256];
 469 };
 470
 471 struct nvme_id_ctrl_zns {
 472         __u8    zasl;
 473         __u8    rsvd1[4095];
 474 };
 475
 476 struct nvme_id_ns_nvm {
 477         __le64  lbstm;
 478         __u8    pic;
 479         __u8    rsvd9[3];
 480         __le32  elbaf[64];
 481         __u8    rsvd268[3828];
 482 };
 483
 484 enum {
 485         NVME_ID_NS_NVM_STS_MASK         = 0x7f,
 486         NVME_ID_NS_NVM_GUARD_SHIFT      = 7,
 487         NVME_ID_NS_NVM_GUARD_MASK       = 0x3,
 488 };
 489
 490 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
 491 {
 492         return elbaf & NVME_ID_NS_NVM_STS_MASK;
 493 }
 494
 495 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
 496 {
 497         return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
 498 }
 499
 500 struct nvme_id_ctrl_nvm {
 501         __u8    vsl;
 502         __u8    wzsl;
 503         __u8    wusl;
 504         __u8    dmrl;
 505         __le32  dmrsl;
 506         __le64  dmsl;
 507         __u8    rsvd16[4080];
 508 };
 509
 510 enum {
 511         NVME_ID_CNS_NS                  = 0x00,
 512         NVME_ID_CNS_CTRL                = 0x01,
 513         NVME_ID_CNS_NS_ACTIVE_LIST      = 0x02,
 514         NVME_ID_CNS_NS_DESC_LIST        = 0x03,
 515         NVME_ID_CNS_CS_NS               = 0x05,
 516         NVME_ID_CNS_CS_CTRL             = 0x06,
 517         NVME_ID_CNS_NS_CS_INDEP         = 0x08,
 518         NVME_ID_CNS_NS_PRESENT_LIST     = 0x10,
 519         NVME_ID_CNS_NS_PRESENT          = 0x11,
 520         NVME_ID_CNS_CTRL_NS_LIST        = 0x12,
 521         NVME_ID_CNS_CTRL_LIST           = 0x13,
 522         NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
 523         NVME_ID_CNS_NS_GRANULARITY      = 0x16,
 524         NVME_ID_CNS_UUID_LIST           = 0x17,
 525 };
 526
 527 enum {
 528         NVME_CSI_NVM                    = 0,
 529         NVME_CSI_ZNS                    = 2,
 530 };
 531
 532 enum {
 533         NVME_DIR_IDENTIFY               = 0x00,
 534         NVME_DIR_STREAMS                = 0x01,
 535         NVME_DIR_SND_ID_OP_ENABLE       = 0x01,
 536         NVME_DIR_SND_ST_OP_REL_ID       = 0x01,
 537         NVME_DIR_SND_ST_OP_REL_RSC      = 0x02,
 538         NVME_DIR_RCV_ID_OP_PARAM        = 0x01,
 539         NVME_DIR_RCV_ST_OP_PARAM        = 0x01,
 540         NVME_DIR_RCV_ST_OP_STATUS       = 0x02,
 541         NVME_DIR_RCV_ST_OP_RESOURCE     = 0x03,
 542         NVME_DIR_ENDIR                  = 0x01,
 543 };
 544
 545 enum {
 546         NVME_NS_FEAT_THIN       = 1 << 0,
 547         NVME_NS_FEAT_ATOMICS    = 1 << 1,
 548         NVME_NS_FEAT_IO_OPT     = 1 << 4,
 549         NVME_NS_ATTR_RO         = 1 << 0,
 550         NVME_NS_FLBAS_LBA_MASK  = 0xf,
 551         NVME_NS_FLBAS_LBA_UMASK = 0x60,
 552         NVME_NS_FLBAS_LBA_SHIFT = 1,
 553         NVME_NS_FLBAS_META_EXT  = 0x10,
 554         NVME_NS_NMIC_SHARED     = 1 << 0,
 555         NVME_LBAF_RP_BEST       = 0,
 556         NVME_LBAF_RP_BETTER     = 1,
 557         NVME_LBAF_RP_GOOD       = 2,
 558         NVME_LBAF_RP_DEGRADED   = 3,
 559         NVME_NS_DPC_PI_LAST     = 1 << 4,
 560         NVME_NS_DPC_PI_FIRST    = 1 << 3,
 561         NVME_NS_DPC_PI_TYPE3    = 1 << 2,
 562         NVME_NS_DPC_PI_TYPE2    = 1 << 1,
 563         NVME_NS_DPC_PI_TYPE1    = 1 << 0,
 564         NVME_NS_DPS_PI_FIRST    = 1 << 3,
 565         NVME_NS_DPS_PI_MASK     = 0x7,
 566         NVME_NS_DPS_PI_TYPE1    = 1,
 567         NVME_NS_DPS_PI_TYPE2    = 2,
 568         NVME_NS_DPS_PI_TYPE3    = 3,
 569 };
 570
 571 enum {
 572         NVME_NSTAT_NRDY         = 1 << 0,
 573 };
 574
 575 enum {
 576         NVME_NVM_NS_16B_GUARD   = 0,
 577         NVME_NVM_NS_32B_GUARD   = 1,
 578         NVME_NVM_NS_64B_GUARD   = 2,
 579 };
 580
 581 static inline __u8 nvme_lbaf_index(__u8 flbas)
 582 {
 583         return (flbas & NVME_NS_FLBAS_LBA_MASK) |
 584                 ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
 585 }
 586
 587 /* Identify Namespace Metadata Capabilities (MC): */
 588 enum {
 589         NVME_MC_EXTENDED_LBA    = (1 << 0),
 590         NVME_MC_METADATA_PTR    = (1 << 1),
 591 };
 592
 593 struct nvme_ns_id_desc {
 594         __u8 nidt;
 595         __u8 nidl;
 596         __le16 reserved;
 597 };
 598
 599 #define NVME_NIDT_EUI64_LEN     8
 600 #define NVME_NIDT_NGUID_LEN     16
 601 #define NVME_NIDT_UUID_LEN      16
 602 #define NVME_NIDT_CSI_LEN       1
 603
 604 enum {
 605         NVME_NIDT_EUI64         = 0x01,
 606         NVME_NIDT_NGUID         = 0x02,
 607         NVME_NIDT_UUID          = 0x03,
 608         NVME_NIDT_CSI           = 0x04,
 609 };
 610
 611 struct nvme_smart_log {
 612         __u8                    critical_warning;
 613         __u8                    temperature[2];
 614         __u8                    avail_spare;
 615         __u8                    spare_thresh;
 616         __u8                    percent_used;
 617         __u8                    endu_grp_crit_warn_sumry;
 618         __u8                    rsvd7[25];
 619         __u8                    data_units_read[16];
 620         __u8                    data_units_written[16];
 621         __u8                    host_reads[16];
 622         __u8                    host_writes[16];
 623         __u8                    ctrl_busy_time[16];
 624         __u8                    power_cycles[16];
 625         __u8                    power_on_hours[16];
 626         __u8                    unsafe_shutdowns[16];
 627         __u8                    media_errors[16];
 628         __u8                    num_err_log_entries[16];
 629         __le32                  warning_temp_time;
 630         __le32                  critical_comp_time;
 631         __le16                  temp_sensor[8];
 632         __le32                  thm_temp1_trans_count;
 633         __le32                  thm_temp2_trans_count;
 634         __le32                  thm_temp1_total_time;
 635         __le32                  thm_temp2_total_time;
 636         __u8                    rsvd232[280];
 637 };
 638
 639 struct nvme_fw_slot_info_log {
 640         __u8                    afi;
 641         __u8                    rsvd1[7];
 642         __le64                  frs[7];
 643         __u8                    rsvd64[448];
 644 };
 645
 646 enum {
 647         NVME_CMD_EFFECTS_CSUPP          = 1 << 0,
 648         NVME_CMD_EFFECTS_LBCC           = 1 << 1,
 649         NVME_CMD_EFFECTS_NCC            = 1 << 2,
 650         NVME_CMD_EFFECTS_NIC            = 1 << 3,
 651         NVME_CMD_EFFECTS_CCC            = 1 << 4,
 652         NVME_CMD_EFFECTS_CSER_MASK      = GENMASK(15, 14),
 653         NVME_CMD_EFFECTS_CSE_MASK       = GENMASK(18, 16),
 654         NVME_CMD_EFFECTS_UUID_SEL       = 1 << 19,
 655         NVME_CMD_EFFECTS_SCOPE_MASK     = GENMASK(31, 20),
 656 };
 657
 658 struct nvme_effects_log {
 659         __le32 acs[256];
 660         __le32 iocs[256];
 661         __u8   resv[2048];
 662 };
 663
 664 enum nvme_ana_state {
 665         NVME_ANA_OPTIMIZED              = 0x01,
 666         NVME_ANA_NONOPTIMIZED           = 0x02,
 667         NVME_ANA_INACCESSIBLE           = 0x03,
 668         NVME_ANA_PERSISTENT_LOSS        = 0x04,
 669         NVME_ANA_CHANGE                 = 0x0f,
 670 };
 671
 672 struct nvme_ana_group_desc {
 673         __le32  grpid;
 674         __le32  nnsids;
 675         __le64  chgcnt;
 676         __u8    state;
 677         __u8    rsvd17[15];
 678         __le32  nsids[];
 679 };
 680
 681 /* flag for the log specific field of the ANA log */
 682 #define NVME_ANA_LOG_RGO        (1 << 0)
 683
 684 struct nvme_ana_rsp_hdr {
 685         __le64  chgcnt;
 686         __le16  ngrps;
 687         __le16  rsvd10[3];
 688 };
 689
 690 struct nvme_zone_descriptor {
 691         __u8            zt;
 692         __u8            zs;
 693         __u8            za;
 694         __u8            rsvd3[5];
 695         __le64          zcap;
 696         __le64          zslba;
 697         __le64          wp;
 698         __u8            rsvd32[32];
 699 };
 700
 701 enum {
 702         NVME_ZONE_TYPE_SEQWRITE_REQ     = 0x2,
 703 };
 704
 705 struct nvme_zone_report {
 706         __le64          nr_zones;
 707         __u8            resv8[56];
 708         struct nvme_zone_descriptor entries[];
 709 };
 710
 711 enum {
 712         NVME_SMART_CRIT_SPARE           = 1 << 0,
 713         NVME_SMART_CRIT_TEMPERATURE     = 1 << 1,
 714         NVME_SMART_CRIT_RELIABILITY     = 1 << 2,
 715         NVME_SMART_CRIT_MEDIA           = 1 << 3,
 716         NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
 717 };
 718
 719 enum {
 720         NVME_AER_ERROR                  = 0,
 721         NVME_AER_SMART                  = 1,
 722         NVME_AER_NOTICE                 = 2,
 723         NVME_AER_CSS                    = 6,
 724         NVME_AER_VS                     = 7,
 725 };
 726
 727 enum {
 728         NVME_AER_ERROR_PERSIST_INT_ERR  = 0x03,
 729 };
 730
 731 enum {
 732         NVME_AER_NOTICE_NS_CHANGED      = 0x00,
 733         NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
 734         NVME_AER_NOTICE_ANA             = 0x03,
 735         NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
 736 };
 737
 738 enum {
 739         NVME_AEN_BIT_NS_ATTR            = 8,
 740         NVME_AEN_BIT_FW_ACT             = 9,
 741         NVME_AEN_BIT_ANA_CHANGE         = 11,
 742         NVME_AEN_BIT_DISC_CHANGE        = 31,
 743 };
 744
 745 enum {
 746         NVME_AEN_CFG_NS_ATTR            = 1 << NVME_AEN_BIT_NS_ATTR,
 747         NVME_AEN_CFG_FW_ACT             = 1 << NVME_AEN_BIT_FW_ACT,
 748         NVME_AEN_CFG_ANA_CHANGE         = 1 << NVME_AEN_BIT_ANA_CHANGE,
 749         NVME_AEN_CFG_DISC_CHANGE        = 1 << NVME_AEN_BIT_DISC_CHANGE,
 750 };
 751
 752 struct nvme_lba_range_type {
 753         __u8                    type;
 754         __u8                    attributes;
 755         __u8                    rsvd2[14];
 756         __le64                  slba;
 757         __le64                  nlb;
 758         __u8                    guid[16];
 759         __u8                    rsvd48[16];
 760 };
 761
 762 enum {
 763         NVME_LBART_TYPE_FS      = 0x01,
 764         NVME_LBART_TYPE_RAID    = 0x02,
 765         NVME_LBART_TYPE_CACHE   = 0x03,
 766         NVME_LBART_TYPE_SWAP    = 0x04,
 767
 768         NVME_LBART_ATTRIB_TEMP  = 1 << 0,
 769         NVME_LBART_ATTRIB_HIDE  = 1 << 1,
 770 };
 771
 772 enum nvme_pr_type {
 773         NVME_PR_WRITE_EXCLUSIVE                 = 1,
 774         NVME_PR_EXCLUSIVE_ACCESS                = 2,
 775         NVME_PR_WRITE_EXCLUSIVE_REG_ONLY        = 3,
 776         NVME_PR_EXCLUSIVE_ACCESS_REG_ONLY       = 4,
 777         NVME_PR_WRITE_EXCLUSIVE_ALL_REGS        = 5,
 778         NVME_PR_EXCLUSIVE_ACCESS_ALL_REGS       = 6,
 779 };
 780
 781 enum nvme_eds {
 782         NVME_EXTENDED_DATA_STRUCT       = 0x1,
 783 };
 784
 785 struct nvme_registered_ctrl {
 786         __le16  cntlid;
 787         __u8    rcsts;
 788         __u8    rsvd3[5];
 789         __le64  hostid;
 790         __le64  rkey;
 791 };
 792
 793 struct nvme_reservation_status {
 794         __le32  gen;
 795         __u8    rtype;
 796         __u8    regctl[2];
 797         __u8    resv5[2];
 798         __u8    ptpls;
 799         __u8    resv10[14];
 800         struct nvme_registered_ctrl regctl_ds[];
 801 };
 802
 803 struct nvme_registered_ctrl_ext {
 804         __le16  cntlid;
 805         __u8    rcsts;
 806         __u8    rsvd3[5];
 807         __le64  rkey;
 808         __u8    hostid[16];
 809         __u8    rsvd32[32];
 810 };
 811
 812 struct nvme_reservation_status_ext {
 813         __le32  gen;
 814         __u8    rtype;
 815         __u8    regctl[2];
 816         __u8    resv5[2];
 817         __u8    ptpls;
 818         __u8    resv10[14];
 819         __u8    rsvd24[40];
 820         struct nvme_registered_ctrl_ext regctl_eds[];
 821 };
 822
 823 /* I/O commands */
 824
 825 enum nvme_opcode {
 826         nvme_cmd_flush          = 0x00,
 827         nvme_cmd_write          = 0x01,
 828         nvme_cmd_read           = 0x02,
 829         nvme_cmd_write_uncor    = 0x04,
 830         nvme_cmd_compare        = 0x05,
 831         nvme_cmd_write_zeroes   = 0x08,
 832         nvme_cmd_dsm            = 0x09,
 833         nvme_cmd_verify         = 0x0c,
 834         nvme_cmd_resv_register  = 0x0d,
 835         nvme_cmd_resv_report    = 0x0e,
 836         nvme_cmd_resv_acquire   = 0x11,
 837         nvme_cmd_resv_release   = 0x15,
 838         nvme_cmd_zone_mgmt_send = 0x79,
 839         nvme_cmd_zone_mgmt_recv = 0x7a,
 840         nvme_cmd_zone_append    = 0x7d,
 841         nvme_cmd_vendor_start   = 0x80,
 842 };
 843
 844 #define nvme_opcode_name(opcode)        { opcode, #opcode }
 845 #define show_nvm_opcode_name(val)                               \
 846         __print_symbolic(val,                                   \
 847                 nvme_opcode_name(nvme_cmd_flush),               \
 848                 nvme_opcode_name(nvme_cmd_write),               \
 849                 nvme_opcode_name(nvme_cmd_read),                \
 850                 nvme_opcode_name(nvme_cmd_write_uncor),         \
 851                 nvme_opcode_name(nvme_cmd_compare),             \
 852                 nvme_opcode_name(nvme_cmd_write_zeroes),        \
 853                 nvme_opcode_name(nvme_cmd_dsm),                 \
 854                 nvme_opcode_name(nvme_cmd_verify),              \
 855                 nvme_opcode_name(nvme_cmd_resv_register),       \
 856                 nvme_opcode_name(nvme_cmd_resv_report),         \
 857                 nvme_opcode_name(nvme_cmd_resv_acquire),        \
 858                 nvme_opcode_name(nvme_cmd_resv_release),        \
 859                 nvme_opcode_name(nvme_cmd_zone_mgmt_send),      \
 860                 nvme_opcode_name(nvme_cmd_zone_mgmt_recv),      \
 861                 nvme_opcode_name(nvme_cmd_zone_append))
 862
 863
 864
 865 /*
 866  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
 867  *
 868  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
 869  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
 870  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
 871  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
 872  *                            request subtype
 873  */
 874 enum {
 875         NVME_SGL_FMT_ADDRESS            = 0x00,
 876         NVME_SGL_FMT_OFFSET             = 0x01,
 877         NVME_SGL_FMT_TRANSPORT_A        = 0x0A,
 878         NVME_SGL_FMT_INVALIDATE         = 0x0f,
 879 };
 880
 881 /*
 882  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
 883  *
 884  * For struct nvme_sgl_desc:
 885  *   @NVME_SGL_FMT_DATA_DESC:           data block descriptor
 886  *   @NVME_SGL_FMT_SEG_DESC:            sgl segment descriptor
 887  *   @NVME_SGL_FMT_LAST_SEG_DESC:       last sgl segment descriptor
 888  *
 889  * For struct nvme_keyed_sgl_desc:
 890  *   @NVME_KEY_SGL_FMT_DATA_DESC:       keyed data block descriptor
 891  *
 892  * Transport-specific SGL types:
 893  *   @NVME_TRANSPORT_SGL_DATA_DESC:     Transport SGL data dlock descriptor
 894  */
 895 enum {
 896         NVME_SGL_FMT_DATA_DESC          = 0x00,
 897         NVME_SGL_FMT_SEG_DESC           = 0x02,
 898         NVME_SGL_FMT_LAST_SEG_DESC      = 0x03,
 899         NVME_KEY_SGL_FMT_DATA_DESC      = 0x04,
 900         NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
 901 };
 902
 903 struct nvme_sgl_desc {
 904         __le64  addr;
 905         __le32  length;
 906         __u8    rsvd[3];
 907         __u8    type;
 908 };
 909
 910 struct nvme_keyed_sgl_desc {
 911         __le64  addr;
 912         __u8    length[3];
 913         __u8    key[4];
 914         __u8    type;
 915 };
 916
 917 union nvme_data_ptr {
 918         struct {
 919                 __le64  prp1;
 920                 __le64  prp2;
 921         };
 922         struct nvme_sgl_desc    sgl;
 923         struct nvme_keyed_sgl_desc ksgl;
 924 };
 925
 926 /*
 927  * Lowest two bits of our flags field (FUSE field in the spec):
 928  *
 929  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
 930  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
 931  *
 932  * Highest two bits in our flags field (PSDT field in the spec):
 933  *
 934  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
 935  *      If used, MPTR contains addr of single physical buffer (byte aligned).
 936  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
 937  *      If used, MPTR contains an address of an SGL segment containing
 938  *      exactly 1 SGL descriptor (qword aligned).
 939  */
 940 enum {
 941         NVME_CMD_FUSE_FIRST     = (1 << 0),
 942         NVME_CMD_FUSE_SECOND    = (1 << 1),
 943
 944         NVME_CMD_SGL_METABUF    = (1 << 6),
 945         NVME_CMD_SGL_METASEG    = (1 << 7),
 946         NVME_CMD_SGL_ALL        = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
 947 };
 948
 949 struct nvme_common_command {
 950         __u8                    opcode;
 951         __u8                    flags;
 952         __u16                   command_id;
 953         __le32                  nsid;
 954         __le32                  cdw2[2];
 955         __le64                  metadata;
 956         union nvme_data_ptr     dptr;
 957         struct_group(cdws,
 958         __le32                  cdw10;
 959         __le32                  cdw11;
 960         __le32                  cdw12;
 961         __le32                  cdw13;
 962         __le32                  cdw14;
 963         __le32                  cdw15;
 964         );
 965 };
 966
 967 struct nvme_rw_command {
 968         __u8                    opcode;
 969         __u8                    flags;
 970         __u16                   command_id;
 971         __le32                  nsid;
 972         __le32                  cdw2;
 973         __le32                  cdw3;
 974         __le64                  metadata;
 975         union nvme_data_ptr     dptr;
 976         __le64                  slba;
 977         __le16                  length;
 978         __le16                  control;
 979         __le32                  dsmgmt;
 980         __le32                  reftag;
 981         __le16                  apptag;
 982         __le16                  appmask;
 983 };
 984
 985 enum {
 986         NVME_RW_LR                      = 1 << 15,
 987         NVME_RW_FUA                     = 1 << 14,
 988         NVME_RW_APPEND_PIREMAP          = 1 << 9,
 989         NVME_RW_DSM_FREQ_UNSPEC         = 0,
 990         NVME_RW_DSM_FREQ_TYPICAL        = 1,
 991         NVME_RW_DSM_FREQ_RARE           = 2,
 992         NVME_RW_DSM_FREQ_READS          = 3,
 993         NVME_RW_DSM_FREQ_WRITES         = 4,
 994         NVME_RW_DSM_FREQ_RW             = 5,
 995         NVME_RW_DSM_FREQ_ONCE           = 6,
 996         NVME_RW_DSM_FREQ_PREFETCH       = 7,
 997         NVME_RW_DSM_FREQ_TEMP           = 8,
 998         NVME_RW_DSM_LATENCY_NONE        = 0 << 4,
 999         NVME_RW_DSM_LATENCY_IDLE        = 1 << 4,
1000         NVME_RW_DSM_LATENCY_NORM        = 2 << 4,
1001         NVME_RW_DSM_LATENCY_LOW         = 3 << 4,
1002         NVME_RW_DSM_SEQ_REQ             = 1 << 6,
1003         NVME_RW_DSM_COMPRESSED          = 1 << 7,
1004         NVME_RW_PRINFO_PRCHK_REF        = 1 << 10,
1005         NVME_RW_PRINFO_PRCHK_APP        = 1 << 11,
1006         NVME_RW_PRINFO_PRCHK_GUARD      = 1 << 12,
1007         NVME_RW_PRINFO_PRACT            = 1 << 13,
1008         NVME_RW_DTYPE_STREAMS           = 1 << 4,
1009         NVME_WZ_DEAC                    = 1 << 9,
1010 };
1011
1012 struct nvme_dsm_cmd {
1013         __u8                    opcode;
1014         __u8                    flags;
1015         __u16                   command_id;
1016         __le32                  nsid;
1017         __u64                   rsvd2[2];
1018         union nvme_data_ptr     dptr;
1019         __le32                  nr;
1020         __le32                  attributes;
1021         __u32                   rsvd12[4];
1022 };
1023
1024 enum {
1025         NVME_DSMGMT_IDR         = 1 << 0,
1026         NVME_DSMGMT_IDW         = 1 << 1,
1027         NVME_DSMGMT_AD          = 1 << 2,
1028 };
1029
1030 #define NVME_DSM_MAX_RANGES     256
1031
1032 struct nvme_dsm_range {
1033         __le32                  cattr;
1034         __le32                  nlb;
1035         __le64                  slba;
1036 };
1037
1038 struct nvme_write_zeroes_cmd {
1039         __u8                    opcode;
1040         __u8                    flags;
1041         __u16                   command_id;
1042         __le32                  nsid;
1043         __u64                   rsvd2;
1044         __le64                  metadata;
1045         union nvme_data_ptr     dptr;
1046         __le64                  slba;
1047         __le16                  length;
1048         __le16                  control;
1049         __le32                  dsmgmt;
1050         __le32                  reftag;
1051         __le16                  apptag;
1052         __le16                  appmask;
1053 };
1054
1055 enum nvme_zone_mgmt_action {
1056         NVME_ZONE_CLOSE         = 0x1,
1057         NVME_ZONE_FINISH        = 0x2,
1058         NVME_ZONE_OPEN          = 0x3,
1059         NVME_ZONE_RESET         = 0x4,
1060         NVME_ZONE_OFFLINE       = 0x5,
1061         NVME_ZONE_SET_DESC_EXT  = 0x10,
1062 };
1063
1064 struct nvme_zone_mgmt_send_cmd {
1065         __u8                    opcode;
1066         __u8                    flags;
1067         __u16                   command_id;
1068         __le32                  nsid;
1069         __le32                  cdw2[2];
1070         __le64                  metadata;
1071         union nvme_data_ptr     dptr;
1072         __le64                  slba;
1073         __le32                  cdw12;
1074         __u8                    zsa;
1075         __u8                    select_all;
1076         __u8                    rsvd13[2];
1077         __le32                  cdw14[2];
1078 };
1079
1080 struct nvme_zone_mgmt_recv_cmd {
1081         __u8                    opcode;
1082         __u8                    flags;
1083         __u16                   command_id;
1084         __le32                  nsid;
1085         __le64                  rsvd2[2];
1086         union nvme_data_ptr     dptr;
1087         __le64                  slba;
1088         __le32                  numd;
1089         __u8                    zra;
1090         __u8                    zrasf;
1091         __u8                    pr;
1092         __u8                    rsvd13;
1093         __le32                  cdw14[2];
1094 };
1095
1096 enum {
1097         NVME_ZRA_ZONE_REPORT            = 0,
1098         NVME_ZRASF_ZONE_REPORT_ALL      = 0,
1099         NVME_ZRASF_ZONE_STATE_EMPTY     = 0x01,
1100         NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
1101         NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
1102         NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
1103         NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
1104         NVME_ZRASF_ZONE_STATE_FULL      = 0x06,
1105         NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
1106         NVME_REPORT_ZONE_PARTIAL        = 1,
1107 };
1108
1109 /* Features */
1110
1111 enum {
1112         NVME_TEMP_THRESH_MASK           = 0xffff,
1113         NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
1114         NVME_TEMP_THRESH_TYPE_UNDER     = 0x100000,
1115 };
1116
1117 struct nvme_feat_auto_pst {
1118         __le64 entries[32];
1119 };
1120
1121 enum {
1122         NVME_HOST_MEM_ENABLE    = (1 << 0),
1123         NVME_HOST_MEM_RETURN    = (1 << 1),
1124 };
1125
1126 struct nvme_feat_host_behavior {
1127         __u8 acre;
1128         __u8 etdas;
1129         __u8 lbafee;
1130         __u8 resv1[509];
1131 };
1132
1133 enum {
1134         NVME_ENABLE_ACRE        = 1,
1135         NVME_ENABLE_LBAFEE      = 1,
1136 };
1137
1138 /* Admin commands */
1139
1140 enum nvme_admin_opcode {
1141         nvme_admin_delete_sq            = 0x00,
1142         nvme_admin_create_sq            = 0x01,
1143         nvme_admin_get_log_page         = 0x02,
1144         nvme_admin_delete_cq            = 0x04,
1145         nvme_admin_create_cq            = 0x05,
1146         nvme_admin_identify             = 0x06,
1147         nvme_admin_abort_cmd            = 0x08,
1148         nvme_admin_set_features         = 0x09,
1149         nvme_admin_get_features         = 0x0a,
1150         nvme_admin_async_event          = 0x0c,
1151         nvme_admin_ns_mgmt              = 0x0d,
1152         nvme_admin_activate_fw          = 0x10,
1153         nvme_admin_download_fw          = 0x11,
1154         nvme_admin_dev_self_test        = 0x14,
1155         nvme_admin_ns_attach            = 0x15,
1156         nvme_admin_keep_alive           = 0x18,
1157         nvme_admin_directive_send       = 0x19,
1158         nvme_admin_directive_recv       = 0x1a,
1159         nvme_admin_virtual_mgmt         = 0x1c,
1160         nvme_admin_nvme_mi_send         = 0x1d,
1161         nvme_admin_nvme_mi_recv         = 0x1e,
1162         nvme_admin_dbbuf                = 0x7C,
1163         nvme_admin_format_nvm           = 0x80,
1164         nvme_admin_security_send        = 0x81,
1165         nvme_admin_security_recv        = 0x82,
1166         nvme_admin_sanitize_nvm         = 0x84,
1167         nvme_admin_get_lba_status       = 0x86,
1168         nvme_admin_vendor_start         = 0xC0,
1169 };
1170
1171 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1172 #define show_admin_opcode_name(val)                                     \
1173         __print_symbolic(val,                                           \
1174                 nvme_admin_opcode_name(nvme_admin_delete_sq),           \
1175                 nvme_admin_opcode_name(nvme_admin_create_sq),           \
1176                 nvme_admin_opcode_name(nvme_admin_get_log_page),        \
1177                 nvme_admin_opcode_name(nvme_admin_delete_cq),           \
1178                 nvme_admin_opcode_name(nvme_admin_create_cq),           \
1179                 nvme_admin_opcode_name(nvme_admin_identify),            \
1180                 nvme_admin_opcode_name(nvme_admin_abort_cmd),           \
1181                 nvme_admin_opcode_name(nvme_admin_set_features),        \
1182                 nvme_admin_opcode_name(nvme_admin_get_features),        \
1183                 nvme_admin_opcode_name(nvme_admin_async_event),         \
1184                 nvme_admin_opcode_name(nvme_admin_ns_mgmt),             \
1185                 nvme_admin_opcode_name(nvme_admin_activate_fw),         \
1186                 nvme_admin_opcode_name(nvme_admin_download_fw),         \
1187                 nvme_admin_opcode_name(nvme_admin_dev_self_test),       \
1188                 nvme_admin_opcode_name(nvme_admin_ns_attach),           \
1189                 nvme_admin_opcode_name(nvme_admin_keep_alive),          \
1190                 nvme_admin_opcode_name(nvme_admin_directive_send),      \
1191                 nvme_admin_opcode_name(nvme_admin_directive_recv),      \
1192                 nvme_admin_opcode_name(nvme_admin_virtual_mgmt),        \
1193                 nvme_admin_opcode_name(nvme_admin_nvme_mi_send),        \
1194                 nvme_admin_opcode_name(nvme_admin_nvme_mi_recv),        \
1195                 nvme_admin_opcode_name(nvme_admin_dbbuf),               \
1196                 nvme_admin_opcode_name(nvme_admin_format_nvm),          \
1197                 nvme_admin_opcode_name(nvme_admin_security_send),       \
1198                 nvme_admin_opcode_name(nvme_admin_security_recv),       \
1199                 nvme_admin_opcode_name(nvme_admin_sanitize_nvm),        \
1200                 nvme_admin_opcode_name(nvme_admin_get_lba_status))
1201
1202 enum {
1203         NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1204         NVME_CQ_IRQ_ENABLED     = (1 << 1),
1205         NVME_SQ_PRIO_URGENT     = (0 << 1),
1206         NVME_SQ_PRIO_HIGH       = (1 << 1),
1207         NVME_SQ_PRIO_MEDIUM     = (2 << 1),
1208         NVME_SQ_PRIO_LOW        = (3 << 1),
1209         NVME_FEAT_ARBITRATION   = 0x01,
1210         NVME_FEAT_POWER_MGMT    = 0x02,
1211         NVME_FEAT_LBA_RANGE     = 0x03,
1212         NVME_FEAT_TEMP_THRESH   = 0x04,
1213         NVME_FEAT_ERR_RECOVERY  = 0x05,
1214         NVME_FEAT_VOLATILE_WC   = 0x06,
1215         NVME_FEAT_NUM_QUEUES    = 0x07,
1216         NVME_FEAT_IRQ_COALESCE  = 0x08,
1217         NVME_FEAT_IRQ_CONFIG    = 0x09,
1218         NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1219         NVME_FEAT_ASYNC_EVENT   = 0x0b,
1220         NVME_FEAT_AUTO_PST      = 0x0c,
1221         NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1222         NVME_FEAT_TIMESTAMP     = 0x0e,
1223         NVME_FEAT_KATO          = 0x0f,
1224         NVME_FEAT_HCTM          = 0x10,
1225         NVME_FEAT_NOPSC         = 0x11,
1226         NVME_FEAT_RRL           = 0x12,
1227         NVME_FEAT_PLM_CONFIG    = 0x13,
1228         NVME_FEAT_PLM_WINDOW    = 0x14,
1229         NVME_FEAT_HOST_BEHAVIOR = 0x16,
1230         NVME_FEAT_SANITIZE      = 0x17,
1231         NVME_FEAT_SW_PROGRESS   = 0x80,
1232         NVME_FEAT_HOST_ID       = 0x81,
1233         NVME_FEAT_RESV_MASK     = 0x82,
1234         NVME_FEAT_RESV_PERSIST  = 0x83,
1235         NVME_FEAT_WRITE_PROTECT = 0x84,
1236         NVME_FEAT_VENDOR_START  = 0xC0,
1237         NVME_FEAT_VENDOR_END    = 0xFF,
1238         NVME_LOG_ERROR          = 0x01,
1239         NVME_LOG_SMART          = 0x02,
1240         NVME_LOG_FW_SLOT        = 0x03,
1241         NVME_LOG_CHANGED_NS     = 0x04,
1242         NVME_LOG_CMD_EFFECTS    = 0x05,
1243         NVME_LOG_DEVICE_SELF_TEST = 0x06,
1244         NVME_LOG_TELEMETRY_HOST = 0x07,
1245         NVME_LOG_TELEMETRY_CTRL = 0x08,
1246         NVME_LOG_ENDURANCE_GROUP = 0x09,
1247         NVME_LOG_ANA            = 0x0c,
1248         NVME_LOG_DISC           = 0x70,
1249         NVME_LOG_RESERVATION    = 0x80,
1250         NVME_FWACT_REPL         = (0 << 3),
1251         NVME_FWACT_REPL_ACTV    = (1 << 3),
1252         NVME_FWACT_ACTV         = (2 << 3),
1253 };
1254
1255 /* NVMe Namespace Write Protect State */
1256 enum {
1257         NVME_NS_NO_WRITE_PROTECT = 0,
1258         NVME_NS_WRITE_PROTECT,
1259         NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1260         NVME_NS_WRITE_PROTECT_PERMANENT,
1261 };
1262
1263 #define NVME_MAX_CHANGED_NAMESPACES     1024
1264
1265 struct nvme_identify {
1266         __u8                    opcode;
1267         __u8                    flags;
1268         __u16                   command_id;
1269         __le32                  nsid;
1270         __u64                   rsvd2[2];
1271         union nvme_data_ptr     dptr;
1272         __u8                    cns;
1273         __u8                    rsvd3;
1274         __le16                  ctrlid;
1275         __u8                    rsvd11[3];
1276         __u8                    csi;
1277         __u32                   rsvd12[4];
1278 };
1279
1280 #define NVME_IDENTIFY_DATA_SIZE 4096
1281
1282 struct nvme_features {
1283         __u8                    opcode;
1284         __u8                    flags;
1285         __u16                   command_id;
1286         __le32                  nsid;
1287         __u64                   rsvd2[2];
1288         union nvme_data_ptr     dptr;
1289         __le32                  fid;
1290         __le32                  dword11;
1291         __le32                  dword12;
1292         __le32                  dword13;
1293         __le32                  dword14;
1294         __le32                  dword15;
1295 };
1296
1297 struct nvme_host_mem_buf_desc {
1298         __le64                  addr;
1299         __le32                  size;
1300         __u32                   rsvd;
1301 };
1302
1303 struct nvme_create_cq {
1304         __u8                    opcode;
1305         __u8                    flags;
1306         __u16                   command_id;
1307         __u32                   rsvd1[5];
1308         __le64                  prp1;
1309         __u64                   rsvd8;
1310         __le16                  cqid;
1311         __le16                  qsize;
1312         __le16                  cq_flags;
1313         __le16                  irq_vector;
1314         __u32                   rsvd12[4];
1315 };
1316
1317 struct nvme_create_sq {
1318         __u8                    opcode;
1319         __u8                    flags;
1320         __u16                   command_id;
1321         __u32                   rsvd1[5];
1322         __le64                  prp1;
1323         __u64                   rsvd8;
1324         __le16                  sqid;
1325         __le16                  qsize;
1326         __le16                  sq_flags;
1327         __le16                  cqid;
1328         __u32                   rsvd12[4];
1329 };
1330
1331 struct nvme_delete_queue {
1332         __u8                    opcode;
1333         __u8                    flags;
1334         __u16                   command_id;
1335         __u32                   rsvd1[9];
1336         __le16                  qid;
1337         __u16                   rsvd10;
1338         __u32                   rsvd11[5];
1339 };
1340
1341 struct nvme_abort_cmd {
1342         __u8                    opcode;
1343         __u8                    flags;
1344         __u16                   command_id;
1345         __u32                   rsvd1[9];
1346         __le16                  sqid;
1347         __u16                   cid;
1348         __u32                   rsvd11[5];
1349 };
1350
1351 struct nvme_download_firmware {
1352         __u8                    opcode;
1353         __u8                    flags;
1354         __u16                   command_id;
1355         __u32                   rsvd1[5];
1356         union nvme_data_ptr     dptr;
1357         __le32                  numd;
1358         __le32                  offset;
1359         __u32                   rsvd12[4];
1360 };
1361
1362 struct nvme_format_cmd {
1363         __u8                    opcode;
1364         __u8                    flags;
1365         __u16                   command_id;
1366         __le32                  nsid;
1367         __u64                   rsvd2[4];
1368         __le32                  cdw10;
1369         __u32                   rsvd11[5];
1370 };
1371
1372 struct nvme_get_log_page_command {
1373         __u8                    opcode;
1374         __u8                    flags;
1375         __u16                   command_id;
1376         __le32                  nsid;
1377         __u64                   rsvd2[2];
1378         union nvme_data_ptr     dptr;
1379         __u8                    lid;
1380         __u8                    lsp; /* upper 4 bits reserved */
1381         __le16                  numdl;
1382         __le16                  numdu;
1383         __u16                   rsvd11;
1384         union {
1385                 struct {
1386                         __le32 lpol;
1387                         __le32 lpou;
1388                 };
1389                 __le64 lpo;
1390         };
1391         __u8                    rsvd14[3];
1392         __u8                    csi;
1393         __u32                   rsvd15;
1394 };
1395
1396 struct nvme_directive_cmd {
1397         __u8                    opcode;
1398         __u8                    flags;
1399         __u16                   command_id;
1400         __le32                  nsid;
1401         __u64                   rsvd2[2];
1402         union nvme_data_ptr     dptr;
1403         __le32                  numd;
1404         __u8                    doper;
1405         __u8                    dtype;
1406         __le16                  dspec;
1407         __u8                    endir;
1408         __u8                    tdtype;
1409         __u16                   rsvd15;
1410
1411         __u32                   rsvd16[3];
1412 };
1413
1414 /*
1415  * Fabrics subcommands.
1416  */
1417 enum nvmf_fabrics_opcode {
1418         nvme_fabrics_command            = 0x7f,
1419 };
1420
1421 enum nvmf_capsule_command {
1422         nvme_fabrics_type_property_set  = 0x00,
1423         nvme_fabrics_type_connect       = 0x01,
1424         nvme_fabrics_type_property_get  = 0x04,
1425         nvme_fabrics_type_auth_send     = 0x05,
1426         nvme_fabrics_type_auth_receive  = 0x06,
1427 };
1428
1429 #define nvme_fabrics_type_name(type)   { type, #type }
1430 #define show_fabrics_type_name(type)                                    \
1431         __print_symbolic(type,                                          \
1432                 nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1433                 nvme_fabrics_type_name(nvme_fabrics_type_connect),      \
1434                 nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1435                 nvme_fabrics_type_name(nvme_fabrics_type_auth_send),    \
1436                 nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1437
1438 /*
1439  * If not fabrics command, fctype will be ignored.
1440  */
1441 #define show_opcode_name(qid, opcode, fctype)                   \
1442         ((opcode) == nvme_fabrics_command ?                     \
1443          show_fabrics_type_name(fctype) :                       \
1444         ((qid) ?                                                \
1445          show_nvm_opcode_name(opcode) :                         \
1446          show_admin_opcode_name(opcode)))
1447
1448 struct nvmf_common_command {
1449         __u8    opcode;
1450         __u8    resv1;
1451         __u16   command_id;
1452         __u8    fctype;
1453         __u8    resv2[35];
1454         __u8    ts[24];
1455 };
1456
1457 /*
1458  * The legal cntlid range a NVMe Target will provide.
1459  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1460  * Devices based on earlier specs did not have the subsystem concept;
1461  * therefore, those devices had their cntlid value set to 0 as a result.
1462  */
1463 #define NVME_CNTLID_MIN         1
1464 #define NVME_CNTLID_MAX         0xffef
1465 #define NVME_CNTLID_DYNAMIC     0xffff
1466
1467 #define MAX_DISC_LOGS   255
1468
1469 /* Discovery log page entry flags (EFLAGS): */
1470 enum {
1471         NVME_DISC_EFLAGS_EPCSD          = (1 << 1),
1472         NVME_DISC_EFLAGS_DUPRETINFO     = (1 << 0),
1473 };
1474
1475 /* Discovery log page entry */
1476 struct nvmf_disc_rsp_page_entry {
1477         __u8            trtype;
1478         __u8            adrfam;
1479         __u8            subtype;
1480         __u8            treq;
1481         __le16          portid;
1482         __le16          cntlid;
1483         __le16          asqsz;
1484         __le16          eflags;
1485         __u8            resv10[20];
1486         char            trsvcid[NVMF_TRSVCID_SIZE];
1487         __u8            resv64[192];
1488         char            subnqn[NVMF_NQN_FIELD_LEN];
1489         char            traddr[NVMF_TRADDR_SIZE];
1490         union tsas {
1491                 char            common[NVMF_TSAS_SIZE];
1492                 struct rdma {
1493                         __u8    qptype;
1494                         __u8    prtype;
1495                         __u8    cms;
1496                         __u8    resv3[5];
1497                         __u16   pkey;
1498                         __u8    resv10[246];
1499                 } rdma;
1500                 struct tcp {
1501                         __u8    sectype;
1502                 } tcp;
1503         } tsas;
1504 };
1505
1506 /* Discovery log page header */
1507 struct nvmf_disc_rsp_page_hdr {
1508         __le64          genctr;
1509         __le64          numrec;
1510         __le16          recfmt;
1511         __u8            resv14[1006];
1512         struct nvmf_disc_rsp_page_entry entries[];
1513 };
1514
1515 enum {
1516         NVME_CONNECT_DISABLE_SQFLOW     = (1 << 2),
1517 };
1518
1519 struct nvmf_connect_command {
1520         __u8            opcode;
1521         __u8            resv1;
1522         __u16           command_id;
1523         __u8            fctype;
1524         __u8            resv2[19];
1525         union nvme_data_ptr dptr;
1526         __le16          recfmt;
1527         __le16          qid;
1528         __le16          sqsize;
1529         __u8            cattr;
1530         __u8            resv3;
1531         __le32          kato;
1532         __u8            resv4[12];
1533 };
1534
1535 enum {
1536         NVME_CONNECT_AUTHREQ_ASCR       = (1U << 18),
1537         NVME_CONNECT_AUTHREQ_ATR        = (1U << 17),
1538 };
1539
1540 struct nvmf_connect_data {
1541         uuid_t          hostid;
1542         __le16          cntlid;
1543         char            resv4[238];
1544         char            subsysnqn[NVMF_NQN_FIELD_LEN];
1545         char            hostnqn[NVMF_NQN_FIELD_LEN];
1546         char            resv5[256];
1547 };
1548
1549 struct nvmf_property_set_command {
1550         __u8            opcode;
1551         __u8            resv1;
1552         __u16           command_id;
1553         __u8            fctype;
1554         __u8            resv2[35];
1555         __u8            attrib;
1556         __u8            resv3[3];
1557         __le32          offset;
1558         __le64          value;
1559         __u8            resv4[8];
1560 };
1561
1562 struct nvmf_property_get_command {
1563         __u8            opcode;
1564         __u8            resv1;
1565         __u16           command_id;
1566         __u8            fctype;
1567         __u8            resv2[35];
1568         __u8            attrib;
1569         __u8            resv3[3];
1570         __le32          offset;
1571         __u8            resv4[16];
1572 };
1573
1574 struct nvmf_auth_common_command {
1575         __u8            opcode;
1576         __u8            resv1;
1577         __u16           command_id;
1578         __u8            fctype;
1579         __u8            resv2[19];
1580         union nvme_data_ptr dptr;
1581         __u8            resv3;
1582         __u8            spsp0;
1583         __u8            spsp1;
1584         __u8            secp;
1585         __le32          al_tl;
1586         __u8            resv4[16];
1587 };
1588
1589 struct nvmf_auth_send_command {
1590         __u8            opcode;
1591         __u8            resv1;
1592         __u16           command_id;
1593         __u8            fctype;
1594         __u8            resv2[19];
1595         union nvme_data_ptr dptr;
1596         __u8            resv3;
1597         __u8            spsp0;
1598         __u8            spsp1;
1599         __u8            secp;
1600         __le32          tl;
1601         __u8            resv4[16];
1602 };
1603
1604 struct nvmf_auth_receive_command {
1605         __u8            opcode;
1606         __u8            resv1;
1607         __u16           command_id;
1608         __u8            fctype;
1609         __u8            resv2[19];
1610         union nvme_data_ptr dptr;
1611         __u8            resv3;
1612         __u8            spsp0;
1613         __u8            spsp1;
1614         __u8            secp;
1615         __le32          al;
1616         __u8            resv4[16];
1617 };
1618
1619 /* Value for secp */
1620 enum {
1621         NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER    = 0xe9,
1622 };
1623
1624 /* Defined value for auth_type */
1625 enum {
1626         NVME_AUTH_COMMON_MESSAGES       = 0x00,
1627         NVME_AUTH_DHCHAP_MESSAGES       = 0x01,
1628 };
1629
1630 /* Defined messages for auth_id */
1631 enum {
1632         NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE      = 0x00,
1633         NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE      = 0x01,
1634         NVME_AUTH_DHCHAP_MESSAGE_REPLY          = 0x02,
1635         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1       = 0x03,
1636         NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2       = 0x04,
1637         NVME_AUTH_DHCHAP_MESSAGE_FAILURE2       = 0xf0,
1638         NVME_AUTH_DHCHAP_MESSAGE_FAILURE1       = 0xf1,
1639 };
1640
1641 struct nvmf_auth_dhchap_protocol_descriptor {
1642         __u8            authid;
1643         __u8            rsvd;
1644         __u8            halen;
1645         __u8            dhlen;
1646         __u8            idlist[60];
1647 };
1648
1649 enum {
1650         NVME_AUTH_DHCHAP_AUTH_ID        = 0x01,
1651 };
1652
1653 /* Defined hash functions for DH-HMAC-CHAP authentication */
1654 enum {
1655         NVME_AUTH_HASH_SHA256   = 0x01,
1656         NVME_AUTH_HASH_SHA384   = 0x02,
1657         NVME_AUTH_HASH_SHA512   = 0x03,
1658         NVME_AUTH_HASH_INVALID  = 0xff,
1659 };
1660
1661 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1662 enum {
1663         NVME_AUTH_DHGROUP_NULL          = 0x00,
1664         NVME_AUTH_DHGROUP_2048          = 0x01,
1665         NVME_AUTH_DHGROUP_3072          = 0x02,
1666         NVME_AUTH_DHGROUP_4096          = 0x03,
1667         NVME_AUTH_DHGROUP_6144          = 0x04,
1668         NVME_AUTH_DHGROUP_8192          = 0x05,
1669         NVME_AUTH_DHGROUP_INVALID       = 0xff,
1670 };
1671
1672 union nvmf_auth_protocol {
1673         struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1674 };
1675
1676 struct nvmf_auth_dhchap_negotiate_data {
1677         __u8            auth_type;
1678         __u8            auth_id;
1679         __le16          rsvd;
1680         __le16          t_id;
1681         __u8            sc_c;
1682         __u8            napd;
1683         union nvmf_auth_protocol auth_protocol[];
1684 };
1685
1686 struct nvmf_auth_dhchap_challenge_data {
1687         __u8            auth_type;
1688         __u8            auth_id;
1689         __u16           rsvd1;
1690         __le16          t_id;
1691         __u8            hl;
1692         __u8            rsvd2;
1693         __u8            hashid;
1694         __u8            dhgid;
1695         __le16          dhvlen;
1696         __le32          seqnum;
1697         /* 'hl' bytes of challenge value */
1698         __u8            cval[];
1699         /* followed by 'dhvlen' bytes of DH value */
1700 };
1701
1702 struct nvmf_auth_dhchap_reply_data {
1703         __u8            auth_type;
1704         __u8            auth_id;
1705         __le16          rsvd1;
1706         __le16          t_id;
1707         __u8            hl;
1708         __u8            rsvd2;
1709         __u8            cvalid;
1710         __u8            rsvd3;
1711         __le16          dhvlen;
1712         __le32          seqnum;
1713         /* 'hl' bytes of response data */
1714         __u8            rval[];
1715         /* followed by 'hl' bytes of Challenge value */
1716         /* followed by 'dhvlen' bytes of DH value */
1717 };
1718
1719 enum {
1720         NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1721 };
1722
1723 struct nvmf_auth_dhchap_success1_data {
1724         __u8            auth_type;
1725         __u8            auth_id;
1726         __le16          rsvd1;
1727         __le16          t_id;
1728         __u8            hl;
1729         __u8            rsvd2;
1730         __u8            rvalid;
1731         __u8            rsvd3[7];
1732         /* 'hl' bytes of response value */
1733         __u8            rval[];
1734 };
1735
1736 struct nvmf_auth_dhchap_success2_data {
1737         __u8            auth_type;
1738         __u8            auth_id;
1739         __le16          rsvd1;
1740         __le16          t_id;
1741         __u8            rsvd2[10];
1742 };
1743
1744 struct nvmf_auth_dhchap_failure_data {
1745         __u8            auth_type;
1746         __u8            auth_id;
1747         __le16          rsvd1;
1748         __le16          t_id;
1749         __u8            rescode;
1750         __u8            rescode_exp;
1751 };
1752
1753 enum {
1754         NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED  = 0x01,
1755 };
1756
1757 enum {
1758         NVME_AUTH_DHCHAP_FAILURE_FAILED                 = 0x01,
1759         NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE             = 0x02,
1760         NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH        = 0x03,
1761         NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE          = 0x04,
1762         NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE       = 0x05,
1763         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD      = 0x06,
1764         NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE      = 0x07,
1765 };
1766
1767
1768 struct nvme_dbbuf {
1769         __u8                    opcode;
1770         __u8                    flags;
1771         __u16                   command_id;
1772         __u32                   rsvd1[5];
1773         __le64                  prp1;
1774         __le64                  prp2;
1775         __u32                   rsvd12[6];
1776 };
1777
1778 struct streams_directive_params {
1779         __le16  msl;
1780         __le16  nssa;
1781         __le16  nsso;
1782         __u8    rsvd[10];
1783         __le32  sws;
1784         __le16  sgs;
1785         __le16  nsa;
1786         __le16  nso;
1787         __u8    rsvd2[6];
1788 };
1789
1790 struct nvme_command {
1791         union {
1792                 struct nvme_common_command common;
1793                 struct nvme_rw_command rw;
1794                 struct nvme_identify identify;
1795                 struct nvme_features features;
1796                 struct nvme_create_cq create_cq;
1797                 struct nvme_create_sq create_sq;
1798                 struct nvme_delete_queue delete_queue;
1799                 struct nvme_download_firmware dlfw;
1800                 struct nvme_format_cmd format;
1801                 struct nvme_dsm_cmd dsm;
1802                 struct nvme_write_zeroes_cmd write_zeroes;
1803                 struct nvme_zone_mgmt_send_cmd zms;
1804                 struct nvme_zone_mgmt_recv_cmd zmr;
1805                 struct nvme_abort_cmd abort;
1806                 struct nvme_get_log_page_command get_log_page;
1807                 struct nvmf_common_command fabrics;
1808                 struct nvmf_connect_command connect;
1809                 struct nvmf_property_set_command prop_set;
1810                 struct nvmf_property_get_command prop_get;
1811                 struct nvmf_auth_common_command auth_common;
1812                 struct nvmf_auth_send_command auth_send;
1813                 struct nvmf_auth_receive_command auth_receive;
1814                 struct nvme_dbbuf dbbuf;
1815                 struct nvme_directive_cmd directive;
1816         };
1817 };
1818
1819 static inline bool nvme_is_fabrics(const struct nvme_command *cmd)
1820 {
1821         return cmd->common.opcode == nvme_fabrics_command;
1822 }
1823
1824 struct nvme_error_slot {
1825         __le64          error_count;
1826         __le16          sqid;
1827         __le16          cmdid;
1828         __le16          status_field;
1829         __le16          param_error_location;
1830         __le64          lba;
1831         __le32          nsid;
1832         __u8            vs;
1833         __u8            resv[3];
1834         __le64          cs;
1835         __u8            resv2[24];
1836 };
1837
1838 static inline bool nvme_is_write(const struct nvme_command *cmd)
1839 {
1840         /*
1841          * What a mess...
1842          *
1843          * Why can't we simply have a Fabrics In and Fabrics out command?
1844          */
1845         if (unlikely(nvme_is_fabrics(cmd)))
1846                 return cmd->fabrics.fctype & 1;
1847         return cmd->common.opcode & 1;
1848 }
1849
1850 enum {
1851         /*
1852          * Generic Command Status:
1853          */
1854         NVME_SCT_GENERIC                = 0x0,
1855         NVME_SC_SUCCESS                 = 0x0,
1856         NVME_SC_INVALID_OPCODE          = 0x1,
1857         NVME_SC_INVALID_FIELD           = 0x2,
1858         NVME_SC_CMDID_CONFLICT          = 0x3,
1859         NVME_SC_DATA_XFER_ERROR         = 0x4,
1860         NVME_SC_POWER_LOSS              = 0x5,
1861         NVME_SC_INTERNAL                = 0x6,
1862         NVME_SC_ABORT_REQ               = 0x7,
1863         NVME_SC_ABORT_QUEUE             = 0x8,
1864         NVME_SC_FUSED_FAIL              = 0x9,
1865         NVME_SC_FUSED_MISSING           = 0xa,
1866         NVME_SC_INVALID_NS              = 0xb,
1867         NVME_SC_CMD_SEQ_ERROR           = 0xc,
1868         NVME_SC_SGL_INVALID_LAST        = 0xd,
1869         NVME_SC_SGL_INVALID_COUNT       = 0xe,
1870         NVME_SC_SGL_INVALID_DATA        = 0xf,
1871         NVME_SC_SGL_INVALID_METADATA    = 0x10,
1872         NVME_SC_SGL_INVALID_TYPE        = 0x11,
1873         NVME_SC_CMB_INVALID_USE         = 0x12,
1874         NVME_SC_PRP_INVALID_OFFSET      = 0x13,
1875         NVME_SC_ATOMIC_WU_EXCEEDED      = 0x14,
1876         NVME_SC_OP_DENIED               = 0x15,
1877         NVME_SC_SGL_INVALID_OFFSET      = 0x16,
1878         NVME_SC_RESERVED                = 0x17,
1879         NVME_SC_HOST_ID_INCONSIST       = 0x18,
1880         NVME_SC_KA_TIMEOUT_EXPIRED      = 0x19,
1881         NVME_SC_KA_TIMEOUT_INVALID      = 0x1A,
1882         NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1883         NVME_SC_SANITIZE_FAILED         = 0x1C,
1884         NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1885         NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1886         NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1887         NVME_SC_NS_WRITE_PROTECTED      = 0x20,
1888         NVME_SC_CMD_INTERRUPTED         = 0x21,
1889         NVME_SC_TRANSIENT_TR_ERR        = 0x22,
1890         NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1891         NVME_SC_INVALID_IO_CMD_SET      = 0x2C,
1892
1893         NVME_SC_LBA_RANGE               = 0x80,
1894         NVME_SC_CAP_EXCEEDED            = 0x81,
1895         NVME_SC_NS_NOT_READY            = 0x82,
1896         NVME_SC_RESERVATION_CONFLICT    = 0x83,
1897         NVME_SC_FORMAT_IN_PROGRESS      = 0x84,
1898
1899         /*
1900          * Command Specific Status:
1901          */
1902         NVME_SCT_COMMAND_SPECIFIC       = 0x100,
1903         NVME_SC_CQ_INVALID              = 0x100,
1904         NVME_SC_QID_INVALID             = 0x101,
1905         NVME_SC_QUEUE_SIZE              = 0x102,
1906         NVME_SC_ABORT_LIMIT             = 0x103,
1907         NVME_SC_ABORT_MISSING           = 0x104,
1908         NVME_SC_ASYNC_LIMIT             = 0x105,
1909         NVME_SC_FIRMWARE_SLOT           = 0x106,
1910         NVME_SC_FIRMWARE_IMAGE          = 0x107,
1911         NVME_SC_INVALID_VECTOR          = 0x108,
1912         NVME_SC_INVALID_LOG_PAGE        = 0x109,
1913         NVME_SC_INVALID_FORMAT          = 0x10a,
1914         NVME_SC_FW_NEEDS_CONV_RESET     = 0x10b,
1915         NVME_SC_INVALID_QUEUE           = 0x10c,
1916         NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1917         NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1918         NVME_SC_FEATURE_NOT_PER_NS      = 0x10f,
1919         NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1920         NVME_SC_FW_NEEDS_RESET          = 0x111,
1921         NVME_SC_FW_NEEDS_MAX_TIME       = 0x112,
1922         NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1923         NVME_SC_OVERLAPPING_RANGE       = 0x114,
1924         NVME_SC_NS_INSUFFICIENT_CAP     = 0x115,
1925         NVME_SC_NS_ID_UNAVAILABLE       = 0x116,
1926         NVME_SC_NS_ALREADY_ATTACHED     = 0x118,
1927         NVME_SC_NS_IS_PRIVATE           = 0x119,
1928         NVME_SC_NS_NOT_ATTACHED         = 0x11a,
1929         NVME_SC_THIN_PROV_NOT_SUPP      = 0x11b,
1930         NVME_SC_CTRL_LIST_INVALID       = 0x11c,
1931         NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1932         NVME_SC_BP_WRITE_PROHIBITED     = 0x11e,
1933         NVME_SC_CTRL_ID_INVALID         = 0x11f,
1934         NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1935         NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1936         NVME_SC_RES_ID_INVALID          = 0x122,
1937         NVME_SC_PMR_SAN_PROHIBITED      = 0x123,
1938         NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1939         NVME_SC_ANA_ATTACH_FAILED       = 0x125,
1940
1941         /*
1942          * I/O Command Set Specific - NVM commands:
1943          */
1944         NVME_SC_BAD_ATTRIBUTES          = 0x180,
1945         NVME_SC_INVALID_PI              = 0x181,
1946         NVME_SC_READ_ONLY               = 0x182,
1947         NVME_SC_ONCS_NOT_SUPPORTED      = 0x183,
1948
1949         /*
1950          * I/O Command Set Specific - Fabrics commands:
1951          */
1952         NVME_SC_CONNECT_FORMAT          = 0x180,
1953         NVME_SC_CONNECT_CTRL_BUSY       = 0x181,
1954         NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1955         NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1956         NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1957
1958         NVME_SC_DISCOVERY_RESTART       = 0x190,
1959         NVME_SC_AUTH_REQUIRED           = 0x191,
1960
1961         /*
1962          * I/O Command Set Specific - Zoned commands:
1963          */
1964         NVME_SC_ZONE_BOUNDARY_ERROR     = 0x1b8,
1965         NVME_SC_ZONE_FULL               = 0x1b9,
1966         NVME_SC_ZONE_READ_ONLY          = 0x1ba,
1967         NVME_SC_ZONE_OFFLINE            = 0x1bb,
1968         NVME_SC_ZONE_INVALID_WRITE      = 0x1bc,
1969         NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1970         NVME_SC_ZONE_TOO_MANY_OPEN      = 0x1be,
1971         NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1972
1973         /*
1974          * Media and Data Integrity Errors:
1975          */
1976         NVME_SCT_MEDIA_ERROR            = 0x200,
1977         NVME_SC_WRITE_FAULT             = 0x280,
1978         NVME_SC_READ_ERROR              = 0x281,
1979         NVME_SC_GUARD_CHECK             = 0x282,
1980         NVME_SC_APPTAG_CHECK            = 0x283,
1981         NVME_SC_REFTAG_CHECK            = 0x284,
1982         NVME_SC_COMPARE_FAILED          = 0x285,
1983         NVME_SC_ACCESS_DENIED           = 0x286,
1984         NVME_SC_UNWRITTEN_BLOCK         = 0x287,
1985
1986         /*
1987          * Path-related Errors:
1988          */
1989         NVME_SCT_PATH                   = 0x300,
1990         NVME_SC_INTERNAL_PATH_ERROR     = 0x300,
1991         NVME_SC_ANA_PERSISTENT_LOSS     = 0x301,
1992         NVME_SC_ANA_INACCESSIBLE        = 0x302,
1993         NVME_SC_ANA_TRANSITION          = 0x303,
1994         NVME_SC_CTRL_PATH_ERROR         = 0x360,
1995         NVME_SC_HOST_PATH_ERROR         = 0x370,
1996         NVME_SC_HOST_ABORTED_CMD        = 0x371,
1997
1998         NVME_SC_MASK                    = 0x00ff, /* Status Code */
1999         NVME_SCT_MASK                   = 0x0700, /* Status Code Type */
2000         NVME_SCT_SC_MASK                = NVME_SCT_MASK | NVME_SC_MASK,
2001
2002         NVME_STATUS_CRD                 = 0x1800, /* Command Retry Delayed */
2003         NVME_STATUS_MORE                = 0x2000,
2004         NVME_STATUS_DNR                 = 0x4000, /* Do Not Retry */
2005 };
2006
2007 #define NVME_SCT(status) ((status) >> 8 & 7)
2008
2009 struct nvme_completion {
2010         /*
2011          * Used by Admin and Fabrics commands to return data:
2012          */
2013         union nvme_result {
2014                 __le16  u16;
2015                 __le32  u32;
2016                 __le64  u64;
2017         } result;
2018         __le16  sq_head;        /* how much of this queue may be reclaimed */
2019         __le16  sq_id;          /* submission queue that generated this entry */
2020         __u16   command_id;     /* of the command which completed */
2021         __le16  status;         /* did the command fail, and if so, why? */
2022 };
2023
2024 #define NVME_VS(major, minor, tertiary) \
2025         (((major) << 16) | ((minor) << 8) | (tertiary))
2026
2027 #define NVME_MAJOR(ver)         ((ver) >> 16)
2028 #define NVME_MINOR(ver)         (((ver) >> 8) & 0xff)
2029 #define NVME_TERTIARY(ver)      ((ver) & 0xff)
2030
2031 #endif /* _LINUX_NVME_H */