drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_xcp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_trace.h"
  33
  34 #include "sdma/sdma_4_4_2_offset.h"
  35 #include "sdma/sdma_4_4_2_sh_mask.h"
  36
  37 #include "soc15_common.h"
  38 #include "soc15.h"
  39 #include "vega10_sdma_pkt_open.h"
  40
  41 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
  42 #include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
  43
  44 #include "amdgpu_ras.h"
  45
  46 MODULE_FIRMWARE("amdgpu/sdma_4_4_2.bin");
  47 MODULE_FIRMWARE("amdgpu/sdma_4_4_5.bin");
  48
  49 #define mmSMNAID_AID0_MCA_SMU 0x03b30400
  50
  51 #define WREG32_SDMA(instance, offset, value) \
  52         WREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)), value)
  53 #define RREG32_SDMA(instance, offset) \
  54         RREG32(sdma_v4_4_2_get_reg_offset(adev, (instance), (offset)))
  55
  56 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev);
  57 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev);
  58 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  59 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev);
  60 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev);
  61
  62 static u32 sdma_v4_4_2_get_reg_offset(struct amdgpu_device *adev,
  63                 u32 instance, u32 offset)
  64 {
  65         u32 dev_inst = GET_INST(SDMA0, instance);
  66
  67         return (adev->reg_offset[SDMA0_HWIP][dev_inst][0] + offset);
  68 }
  69
  70 static unsigned sdma_v4_4_2_seq_to_irq_id(int seq_num)
  71 {
  72         switch (seq_num) {
  73         case 0:
  74                 return SOC15_IH_CLIENTID_SDMA0;
  75         case 1:
  76                 return SOC15_IH_CLIENTID_SDMA1;
  77         case 2:
  78                 return SOC15_IH_CLIENTID_SDMA2;
  79         case 3:
  80                 return SOC15_IH_CLIENTID_SDMA3;
  81         default:
  82                 return -EINVAL;
  83         }
  84 }
  85
  86 static int sdma_v4_4_2_irq_id_to_seq(struct amdgpu_device *adev, unsigned client_id)
  87 {
  88         switch (client_id) {
  89         case SOC15_IH_CLIENTID_SDMA0:
  90                 return 0;
  91         case SOC15_IH_CLIENTID_SDMA1:
  92                 return 1;
  93         case SOC15_IH_CLIENTID_SDMA2:
  94                 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
  95                         return 0;
  96                 else
  97                         return 2;
  98         case SOC15_IH_CLIENTID_SDMA3:
  99                 if (amdgpu_sriov_vf(adev) && (adev->gfx.xcc_mask == 0x1))
 100                         return 1;
 101                 else
 102                         return 3;
 103         default:
 104                 return -EINVAL;
 105         }
 106 }
 107
 108 static void sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev,
 109                                                    uint32_t inst_mask)
 110 {
 111         u32 val;
 112         int i;
 113
 114         for (i = 0; i < adev->sdma.num_instances; i++) {
 115                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG);
 116                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4);
 117                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG,
 118                                     PIPE_INTERLEAVE_SIZE, 0);
 119                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG, val);
 120
 121                 val = RREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ);
 122                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS,
 123                                     4);
 124                 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ,
 125                                     PIPE_INTERLEAVE_SIZE, 0);
 126                 WREG32_SDMA(i, regSDMA_GB_ADDR_CONFIG_READ, val);
 127         }
 128 }
 129
 130 /**
 131  * sdma_v4_4_2_init_microcode - load ucode images from disk
 132  *
 133  * @adev: amdgpu_device pointer
 134  *
 135  * Use the firmware interface to load the ucode images into
 136  * the driver (not loaded into hw).
 137  * Returns 0 on success, error on failure.
 138  */
 139 static int sdma_v4_4_2_init_microcode(struct amdgpu_device *adev)
 140 {
 141         int ret, i;
 142
 143         for (i = 0; i < adev->sdma.num_instances; i++) {
 144                 if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
 145                     amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) {
 146                         ret = amdgpu_sdma_init_microcode(adev, 0, true);
 147                         break;
 148                 } else {
 149                         ret = amdgpu_sdma_init_microcode(adev, i, false);
 150                         if (ret)
 151                                 return ret;
 152                 }
 153         }
 154
 155         return ret;
 156 }
 157
 158 /**
 159  * sdma_v4_4_2_ring_get_rptr - get the current read pointer
 160  *
 161  * @ring: amdgpu ring pointer
 162  *
 163  * Get the current rptr from the hardware.
 164  */
 165 static uint64_t sdma_v4_4_2_ring_get_rptr(struct amdgpu_ring *ring)
 166 {
 167         u64 rptr;
 168
 169         /* XXX check if swapping is necessary on BE */
 170         rptr = READ_ONCE(*((u64 *)&ring->adev->wb.wb[ring->rptr_offs]));
 171
 172         DRM_DEBUG("rptr before shift == 0x%016llx\n", rptr);
 173         return rptr >> 2;
 174 }
 175
 176 /**
 177  * sdma_v4_4_2_ring_get_wptr - get the current write pointer
 178  *
 179  * @ring: amdgpu ring pointer
 180  *
 181  * Get the current wptr from the hardware.
 182  */
 183 static uint64_t sdma_v4_4_2_ring_get_wptr(struct amdgpu_ring *ring)
 184 {
 185         struct amdgpu_device *adev = ring->adev;
 186         u64 wptr;
 187
 188         if (ring->use_doorbell) {
 189                 /* XXX check if swapping is necessary on BE */
 190                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 191                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 192         } else {
 193                 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI);
 194                 wptr = wptr << 32;
 195                 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR);
 196                 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n",
 197                                 ring->me, wptr);
 198         }
 199
 200         return wptr >> 2;
 201 }
 202
 203 /**
 204  * sdma_v4_4_2_ring_set_wptr - commit the write pointer
 205  *
 206  * @ring: amdgpu ring pointer
 207  *
 208  * Write the wptr back to the hardware.
 209  */
 210 static void sdma_v4_4_2_ring_set_wptr(struct amdgpu_ring *ring)
 211 {
 212         struct amdgpu_device *adev = ring->adev;
 213
 214         DRM_DEBUG("Setting write pointer\n");
 215         if (ring->use_doorbell) {
 216                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 217
 218                 DRM_DEBUG("Using doorbell -- "
 219                                 "wptr_offs == 0x%08x "
 220                                 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 221                                 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 222                                 ring->wptr_offs,
 223                                 lower_32_bits(ring->wptr << 2),
 224                                 upper_32_bits(ring->wptr << 2));
 225                 /* XXX check if swapping is necessary on BE */
 226                 WRITE_ONCE(*wb, (ring->wptr << 2));
 227                 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 228                                 ring->doorbell_index, ring->wptr << 2);
 229                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 230         } else {
 231                 DRM_DEBUG("Not using doorbell -- "
 232                                 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 233                                 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 234                                 ring->me,
 235                                 lower_32_bits(ring->wptr << 2),
 236                                 ring->me,
 237                                 upper_32_bits(ring->wptr << 2));
 238                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR,
 239                             lower_32_bits(ring->wptr << 2));
 240                 WREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI,
 241                             upper_32_bits(ring->wptr << 2));
 242         }
 243 }
 244
 245 /**
 246  * sdma_v4_4_2_page_ring_get_wptr - get the current write pointer
 247  *
 248  * @ring: amdgpu ring pointer
 249  *
 250  * Get the current wptr from the hardware.
 251  */
 252 static uint64_t sdma_v4_4_2_page_ring_get_wptr(struct amdgpu_ring *ring)
 253 {
 254         struct amdgpu_device *adev = ring->adev;
 255         u64 wptr;
 256
 257         if (ring->use_doorbell) {
 258                 /* XXX check if swapping is necessary on BE */
 259                 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 260         } else {
 261                 wptr = RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI);
 262                 wptr = wptr << 32;
 263                 wptr |= RREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR);
 264         }
 265
 266         return wptr >> 2;
 267 }
 268
 269 /**
 270  * sdma_v4_4_2_page_ring_set_wptr - commit the write pointer
 271  *
 272  * @ring: amdgpu ring pointer
 273  *
 274  * Write the wptr back to the hardware.
 275  */
 276 static void sdma_v4_4_2_page_ring_set_wptr(struct amdgpu_ring *ring)
 277 {
 278         struct amdgpu_device *adev = ring->adev;
 279
 280         if (ring->use_doorbell) {
 281                 u64 *wb = (u64 *)&adev->wb.wb[ring->wptr_offs];
 282
 283                 /* XXX check if swapping is necessary on BE */
 284                 WRITE_ONCE(*wb, (ring->wptr << 2));
 285                 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 286         } else {
 287                 uint64_t wptr = ring->wptr << 2;
 288
 289                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR,
 290                             lower_32_bits(wptr));
 291                 WREG32_SDMA(ring->me, regSDMA_PAGE_RB_WPTR_HI,
 292                             upper_32_bits(wptr));
 293         }
 294 }
 295
 296 static void sdma_v4_4_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 297 {
 298         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 299         int i;
 300
 301         for (i = 0; i < count; i++)
 302                 if (sdma && sdma->burst_nop && (i == 0))
 303                         amdgpu_ring_write(ring, ring->funcs->nop |
 304                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 305                 else
 306                         amdgpu_ring_write(ring, ring->funcs->nop);
 307 }
 308
 309 /**
 310  * sdma_v4_4_2_ring_emit_ib - Schedule an IB on the DMA engine
 311  *
 312  * @ring: amdgpu ring pointer
 313  * @job: job to retrieve vmid from
 314  * @ib: IB object to schedule
 315  * @flags: unused
 316  *
 317  * Schedule an IB in the DMA ring.
 318  */
 319 static void sdma_v4_4_2_ring_emit_ib(struct amdgpu_ring *ring,
 320                                    struct amdgpu_job *job,
 321                                    struct amdgpu_ib *ib,
 322                                    uint32_t flags)
 323 {
 324         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 325
 326         /* IB packet must end on a 8 DW boundary */
 327         sdma_v4_4_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 328
 329         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 330                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 331         /* base must be 32 byte aligned */
 332         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 333         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 334         amdgpu_ring_write(ring, ib->length_dw);
 335         amdgpu_ring_write(ring, 0);
 336         amdgpu_ring_write(ring, 0);
 337
 338 }
 339
 340 static void sdma_v4_4_2_wait_reg_mem(struct amdgpu_ring *ring,
 341                                    int mem_space, int hdp,
 342                                    uint32_t addr0, uint32_t addr1,
 343                                    uint32_t ref, uint32_t mask,
 344                                    uint32_t inv)
 345 {
 346         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 347                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(hdp) |
 348                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(mem_space) |
 349                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 350         if (mem_space) {
 351                 /* memory */
 352                 amdgpu_ring_write(ring, addr0);
 353                 amdgpu_ring_write(ring, addr1);
 354         } else {
 355                 /* registers */
 356                 amdgpu_ring_write(ring, addr0 << 2);
 357                 amdgpu_ring_write(ring, addr1 << 2);
 358         }
 359         amdgpu_ring_write(ring, ref); /* reference */
 360         amdgpu_ring_write(ring, mask); /* mask */
 361         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 362                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */
 363 }
 364
 365 /**
 366  * sdma_v4_4_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 367  *
 368  * @ring: amdgpu ring pointer
 369  *
 370  * Emit an hdp flush packet on the requested DMA ring.
 371  */
 372 static void sdma_v4_4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 373 {
 374         struct amdgpu_device *adev = ring->adev;
 375         u32 ref_and_mask = 0;
 376         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 377
 378         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0
 379                        << (ring->me % adev->sdma.num_inst_per_aid);
 380
 381         sdma_v4_4_2_wait_reg_mem(ring, 0, 1,
 382                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
 383                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
 384                                ref_and_mask, ref_and_mask, 10);
 385 }
 386
 387 /**
 388  * sdma_v4_4_2_ring_emit_fence - emit a fence on the DMA ring
 389  *
 390  * @ring: amdgpu ring pointer
 391  * @addr: address
 392  * @seq: sequence number
 393  * @flags: fence related flags
 394  *
 395  * Add a DMA fence packet to the ring to write
 396  * the fence seq number and DMA trap packet to generate
 397  * an interrupt if needed.
 398  */
 399 static void sdma_v4_4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 400                                       unsigned flags)
 401 {
 402         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 403         /* write the fence */
 404         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 405         /* zero in first two bits */
 406         BUG_ON(addr & 0x3);
 407         amdgpu_ring_write(ring, lower_32_bits(addr));
 408         amdgpu_ring_write(ring, upper_32_bits(addr));
 409         amdgpu_ring_write(ring, lower_32_bits(seq));
 410
 411         /* optionally write high bits as well */
 412         if (write64bit) {
 413                 addr += 4;
 414                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 415                 /* zero in first two bits */
 416                 BUG_ON(addr & 0x3);
 417                 amdgpu_ring_write(ring, lower_32_bits(addr));
 418                 amdgpu_ring_write(ring, upper_32_bits(addr));
 419                 amdgpu_ring_write(ring, upper_32_bits(seq));
 420         }
 421
 422         /* generate an interrupt */
 423         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 424         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 425 }
 426
 427
 428 /**
 429  * sdma_v4_4_2_inst_gfx_stop - stop the gfx async dma engines
 430  *
 431  * @adev: amdgpu_device pointer
 432  * @inst_mask: mask of dma engine instances to be disabled
 433  *
 434  * Stop the gfx async dma ring buffers.
 435  */
 436 static void sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev,
 437                                       uint32_t inst_mask)
 438 {
 439         struct amdgpu_ring *sdma[AMDGPU_MAX_SDMA_INSTANCES];
 440         u32 doorbell_offset, doorbell;
 441         u32 rb_cntl, ib_cntl;
 442         int i;
 443
 444         for_each_inst(i, inst_mask) {
 445                 sdma[i] = &adev->sdma.instance[i].ring;
 446
 447                 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 448                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0);
 449                 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 450                 ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 451                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 0);
 452                 WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 453
 454                 if (sdma[i]->use_doorbell) {
 455                         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 456                         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 457
 458                         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);
 459                         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 460                                         SDMA_GFX_DOORBELL_OFFSET,
 461                                         OFFSET, 0);
 462                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 463                         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 464                 }
 465         }
 466 }
 467
 468 /**
 469  * sdma_v4_4_2_inst_rlc_stop - stop the compute async dma engines
 470  *
 471  * @adev: amdgpu_device pointer
 472  * @inst_mask: mask of dma engine instances to be disabled
 473  *
 474  * Stop the compute async dma queues.
 475  */
 476 static void sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev,
 477                                       uint32_t inst_mask)
 478 {
 479         /* XXX todo */
 480 }
 481
 482 /**
 483  * sdma_v4_4_2_inst_page_stop - stop the page async dma engines
 484  *
 485  * @adev: amdgpu_device pointer
 486  * @inst_mask: mask of dma engine instances to be disabled
 487  *
 488  * Stop the page async dma ring buffers.
 489  */
 490 static void sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev,
 491                                        uint32_t inst_mask)
 492 {
 493         u32 rb_cntl, ib_cntl;
 494         int i;
 495
 496         for_each_inst(i, inst_mask) {
 497                 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 498                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 499                                         RB_ENABLE, 0);
 500                 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 501                 ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 502                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL,
 503                                         IB_ENABLE, 0);
 504                 WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 505         }
 506 }
 507
 508 /**
 509  * sdma_v4_4_2_inst_ctx_switch_enable - stop the async dma engines context switch
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @enable: enable/disable the DMA MEs context switch.
 513  * @inst_mask: mask of dma engine instances to be enabled
 514  *
 515  * Halt or unhalt the async dma engines context switch.
 516  */
 517 static void sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev,
 518                                                bool enable, uint32_t inst_mask)
 519 {
 520         u32 f32_cntl, phase_quantum = 0;
 521         int i;
 522
 523         if (amdgpu_sdma_phase_quantum) {
 524                 unsigned value = amdgpu_sdma_phase_quantum;
 525                 unsigned unit = 0;
 526
 527                 while (value > (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 528                                 SDMA_PHASE0_QUANTUM__VALUE__SHIFT)) {
 529                         value = (value + 1) >> 1;
 530                         unit++;
 531                 }
 532                 if (unit > (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 533                             SDMA_PHASE0_QUANTUM__UNIT__SHIFT)) {
 534                         value = (SDMA_PHASE0_QUANTUM__VALUE_MASK >>
 535                                  SDMA_PHASE0_QUANTUM__VALUE__SHIFT);
 536                         unit = (SDMA_PHASE0_QUANTUM__UNIT_MASK >>
 537                                 SDMA_PHASE0_QUANTUM__UNIT__SHIFT);
 538                         WARN_ONCE(1,
 539                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 540                                   value << unit);
 541                 }
 542                 phase_quantum =
 543                         value << SDMA_PHASE0_QUANTUM__VALUE__SHIFT |
 544                         unit  << SDMA_PHASE0_QUANTUM__UNIT__SHIFT;
 545         }
 546
 547         for_each_inst(i, inst_mask) {
 548                 f32_cntl = RREG32_SDMA(i, regSDMA_CNTL);
 549                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_CNTL,
 550                                 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 551                 if (enable && amdgpu_sdma_phase_quantum) {
 552                         WREG32_SDMA(i, regSDMA_PHASE0_QUANTUM, phase_quantum);
 553                         WREG32_SDMA(i, regSDMA_PHASE1_QUANTUM, phase_quantum);
 554                         WREG32_SDMA(i, regSDMA_PHASE2_QUANTUM, phase_quantum);
 555                 }
 556                 WREG32_SDMA(i, regSDMA_CNTL, f32_cntl);
 557
 558                 /* Extend page fault timeout to avoid interrupt storm */
 559                 WREG32_SDMA(i, regSDMA_UTCL1_TIMEOUT, 0x00800080);
 560         }
 561 }
 562
 563 /**
 564  * sdma_v4_4_2_inst_enable - stop the async dma engines
 565  *
 566  * @adev: amdgpu_device pointer
 567  * @enable: enable/disable the DMA MEs.
 568  * @inst_mask: mask of dma engine instances to be enabled
 569  *
 570  * Halt or unhalt the async dma engines.
 571  */
 572 static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable,
 573                                     uint32_t inst_mask)
 574 {
 575         u32 f32_cntl;
 576         int i;
 577
 578         if (!enable) {
 579                 sdma_v4_4_2_inst_gfx_stop(adev, inst_mask);
 580                 sdma_v4_4_2_inst_rlc_stop(adev, inst_mask);
 581                 if (adev->sdma.has_page_queue)
 582                         sdma_v4_4_2_inst_page_stop(adev, inst_mask);
 583
 584                 /* SDMA FW needs to respond to FREEZE requests during reset.
 585                  * Keep it running during reset */
 586                 if (!amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
 587                         return;
 588         }
 589
 590         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 591                 return;
 592
 593         for_each_inst(i, inst_mask) {
 594                 f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL);
 595                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1);
 596                 WREG32_SDMA(i, regSDMA_F32_CNTL, f32_cntl);
 597         }
 598 }
 599
 600 /*
 601  * sdma_v4_4_2_rb_cntl - get parameters for rb_cntl
 602  */
 603 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl)
 604 {
 605         /* Set ring buffer size in dwords */
 606         uint32_t rb_bufsz = order_base_2(ring->ring_size / 4);
 607
 608         barrier(); /* work around https://llvm.org/pr42576 */
 609         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 610 #ifdef __BIG_ENDIAN
 611         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 612         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 613                                 RPTR_WRITEBACK_SWAP_ENABLE, 1);
 614 #endif
 615         return rb_cntl;
 616 }
 617
 618 /**
 619  * sdma_v4_4_2_gfx_resume - setup and start the async dma engines
 620  *
 621  * @adev: amdgpu_device pointer
 622  * @i: instance to resume
 623  *
 624  * Set up the gfx DMA ring buffers and enable them.
 625  * Returns 0 for success, error for failure.
 626  */
 627 static void sdma_v4_4_2_gfx_resume(struct amdgpu_device *adev, unsigned int i)
 628 {
 629         struct amdgpu_ring *ring = &adev->sdma.instance[i].ring;
 630         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 631         u32 wb_offset;
 632         u32 doorbell;
 633         u32 doorbell_offset;
 634         u64 wptr_gpu_addr;
 635
 636         wb_offset = (ring->rptr_offs * 4);
 637
 638         rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL);
 639         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 640         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 641
 642         /* set the wb address whether it's enabled or not */
 643         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_HI,
 644                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 645         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_ADDR_LO,
 646                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 647
 648         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL,
 649                                 RPTR_WRITEBACK_ENABLE, 1);
 650
 651         WREG32_SDMA(i, regSDMA_GFX_RB_BASE, ring->gpu_addr >> 8);
 652         WREG32_SDMA(i, regSDMA_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
 653
 654         ring->wptr = 0;
 655
 656         /* before programing wptr to a less value, need set minor_ptr_update first */
 657         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 1);
 658
 659         /* Initialize the ring buffer's read and write pointers */
 660         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR, 0);
 661         WREG32_SDMA(i, regSDMA_GFX_RB_RPTR_HI, 0);
 662         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR, 0);
 663         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_HI, 0);
 664
 665         doorbell = RREG32_SDMA(i, regSDMA_GFX_DOORBELL);
 666         doorbell_offset = RREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET);
 667
 668         doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,
 669                                  ring->use_doorbell);
 670         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 671                                         SDMA_GFX_DOORBELL_OFFSET,
 672                                         OFFSET, ring->doorbell_index);
 673         WREG32_SDMA(i, regSDMA_GFX_DOORBELL, doorbell);
 674         WREG32_SDMA(i, regSDMA_GFX_DOORBELL_OFFSET, doorbell_offset);
 675
 676         sdma_v4_4_2_ring_set_wptr(ring);
 677
 678         /* set minor_ptr_update to 0 after wptr programed */
 679         WREG32_SDMA(i, regSDMA_GFX_MINOR_PTR_UPDATE, 0);
 680
 681         /* setup the wptr shadow polling */
 682         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 683         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_LO,
 684                     lower_32_bits(wptr_gpu_addr));
 685         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_ADDR_HI,
 686                     upper_32_bits(wptr_gpu_addr));
 687         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL);
 688         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 689                                        SDMA_GFX_RB_WPTR_POLL_CNTL,
 690                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 691         WREG32_SDMA(i, regSDMA_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 692
 693         /* enable DMA RB */
 694         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 1);
 695         WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl);
 696
 697         ib_cntl = RREG32_SDMA(i, regSDMA_GFX_IB_CNTL);
 698         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_ENABLE, 1);
 699 #ifdef __BIG_ENDIAN
 700         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 701 #endif
 702         /* enable DMA IBs */
 703         WREG32_SDMA(i, regSDMA_GFX_IB_CNTL, ib_cntl);
 704 }
 705
 706 /**
 707  * sdma_v4_4_2_page_resume - setup and start the async dma engines
 708  *
 709  * @adev: amdgpu_device pointer
 710  * @i: instance to resume
 711  *
 712  * Set up the page DMA ring buffers and enable them.
 713  * Returns 0 for success, error for failure.
 714  */
 715 static void sdma_v4_4_2_page_resume(struct amdgpu_device *adev, unsigned int i)
 716 {
 717         struct amdgpu_ring *ring = &adev->sdma.instance[i].page;
 718         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 719         u32 wb_offset;
 720         u32 doorbell;
 721         u32 doorbell_offset;
 722         u64 wptr_gpu_addr;
 723
 724         wb_offset = (ring->rptr_offs * 4);
 725
 726         rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL);
 727         rb_cntl = sdma_v4_4_2_rb_cntl(ring, rb_cntl);
 728         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 729
 730         /* Initialize the ring buffer's read and write pointers */
 731         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR, 0);
 732         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_HI, 0);
 733         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR, 0);
 734         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_HI, 0);
 735
 736         /* set the wb address whether it's enabled or not */
 737         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_HI,
 738                upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 739         WREG32_SDMA(i, regSDMA_PAGE_RB_RPTR_ADDR_LO,
 740                lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 741
 742         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL,
 743                                 RPTR_WRITEBACK_ENABLE, 1);
 744
 745         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE, ring->gpu_addr >> 8);
 746         WREG32_SDMA(i, regSDMA_PAGE_RB_BASE_HI, ring->gpu_addr >> 40);
 747
 748         ring->wptr = 0;
 749
 750         /* before programing wptr to a less value, need set minor_ptr_update first */
 751         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 1);
 752
 753         doorbell = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL);
 754         doorbell_offset = RREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET);
 755
 756         doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,
 757                                  ring->use_doorbell);
 758         doorbell_offset = REG_SET_FIELD(doorbell_offset,
 759                                         SDMA_PAGE_DOORBELL_OFFSET,
 760                                         OFFSET, ring->doorbell_index);
 761         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL, doorbell);
 762         WREG32_SDMA(i, regSDMA_PAGE_DOORBELL_OFFSET, doorbell_offset);
 763
 764         /* paging queue doorbell range is setup at sdma_v4_4_2_gfx_resume */
 765         sdma_v4_4_2_page_ring_set_wptr(ring);
 766
 767         /* set minor_ptr_update to 0 after wptr programed */
 768         WREG32_SDMA(i, regSDMA_PAGE_MINOR_PTR_UPDATE, 0);
 769
 770         /* setup the wptr shadow polling */
 771         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 772         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_LO,
 773                     lower_32_bits(wptr_gpu_addr));
 774         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_ADDR_HI,
 775                     upper_32_bits(wptr_gpu_addr));
 776         wptr_poll_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL);
 777         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 778                                        SDMA_PAGE_RB_WPTR_POLL_CNTL,
 779                                        F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
 780         WREG32_SDMA(i, regSDMA_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
 781
 782         /* enable DMA RB */
 783         rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, RB_ENABLE, 1);
 784         WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl);
 785
 786         ib_cntl = RREG32_SDMA(i, regSDMA_PAGE_IB_CNTL);
 787         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_ENABLE, 1);
 788 #ifdef __BIG_ENDIAN
 789         ib_cntl = REG_SET_FIELD(ib_cntl, SDMA_PAGE_IB_CNTL, IB_SWAP_ENABLE, 1);
 790 #endif
 791         /* enable DMA IBs */
 792         WREG32_SDMA(i, regSDMA_PAGE_IB_CNTL, ib_cntl);
 793 }
 794
 795 static void sdma_v4_4_2_init_pg(struct amdgpu_device *adev)
 796 {
 797
 798 }
 799
 800 /**
 801  * sdma_v4_4_2_inst_rlc_resume - setup and start the async dma engines
 802  *
 803  * @adev: amdgpu_device pointer
 804  * @inst_mask: mask of dma engine instances to be enabled
 805  *
 806  * Set up the compute DMA queues and enable them.
 807  * Returns 0 for success, error for failure.
 808  */
 809 static int sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev,
 810                                        uint32_t inst_mask)
 811 {
 812         sdma_v4_4_2_init_pg(adev);
 813
 814         return 0;
 815 }
 816
 817 /**
 818  * sdma_v4_4_2_inst_load_microcode - load the sDMA ME ucode
 819  *
 820  * @adev: amdgpu_device pointer
 821  * @inst_mask: mask of dma engine instances to be enabled
 822  *
 823  * Loads the sDMA0/1 ucode.
 824  * Returns 0 for success, -EINVAL if the ucode is not available.
 825  */
 826 static int sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev,
 827                                            uint32_t inst_mask)
 828 {
 829         const struct sdma_firmware_header_v1_0 *hdr;
 830         const __le32 *fw_data;
 831         u32 fw_size;
 832         int i, j;
 833
 834         /* halt the MEs */
 835         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 836
 837         for_each_inst(i, inst_mask) {
 838                 if (!adev->sdma.instance[i].fw)
 839                         return -EINVAL;
 840
 841                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 842                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 843                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 844
 845                 fw_data = (const __le32 *)
 846                         (adev->sdma.instance[i].fw->data +
 847                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 848
 849                 WREG32_SDMA(i, regSDMA_UCODE_ADDR, 0);
 850
 851                 for (j = 0; j < fw_size; j++)
 852                         WREG32_SDMA(i, regSDMA_UCODE_DATA,
 853                                     le32_to_cpup(fw_data++));
 854
 855                 WREG32_SDMA(i, regSDMA_UCODE_ADDR,
 856                             adev->sdma.instance[i].fw_version);
 857         }
 858
 859         return 0;
 860 }
 861
 862 /**
 863  * sdma_v4_4_2_inst_start - setup and start the async dma engines
 864  *
 865  * @adev: amdgpu_device pointer
 866  * @inst_mask: mask of dma engine instances to be enabled
 867  *
 868  * Set up the DMA engines and enable them.
 869  * Returns 0 for success, error for failure.
 870  */
 871 static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev,
 872                                   uint32_t inst_mask)
 873 {
 874         struct amdgpu_ring *ring;
 875         uint32_t tmp_mask;
 876         int i, r = 0;
 877
 878         if (amdgpu_sriov_vf(adev)) {
 879                 sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
 880                 sdma_v4_4_2_inst_enable(adev, false, inst_mask);
 881         } else {
 882                 /* bypass sdma microcode loading on Gopher */
 883                 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP &&
 884                     adev->sdma.instance[0].fw) {
 885                         r = sdma_v4_4_2_inst_load_microcode(adev, inst_mask);
 886                         if (r)
 887                                 return r;
 888                 }
 889
 890                 /* unhalt the MEs */
 891                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 892                 /* enable sdma ring preemption */
 893                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 894         }
 895
 896         /* start the gfx rings and rlc compute queues */
 897         tmp_mask = inst_mask;
 898         for_each_inst(i, tmp_mask) {
 899                 uint32_t temp;
 900
 901                 WREG32_SDMA(i, regSDMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
 902                 sdma_v4_4_2_gfx_resume(adev, i);
 903                 if (adev->sdma.has_page_queue)
 904                         sdma_v4_4_2_page_resume(adev, i);
 905
 906                 /* set utc l1 enable flag always to 1 */
 907                 temp = RREG32_SDMA(i, regSDMA_CNTL);
 908                 temp = REG_SET_FIELD(temp, SDMA_CNTL, UTC_L1_ENABLE, 1);
 909                 /* enable context empty interrupt during initialization */
 910                 temp = REG_SET_FIELD(temp, SDMA_CNTL, CTXEMPTY_INT_ENABLE, 1);
 911                 WREG32_SDMA(i, regSDMA_CNTL, temp);
 912
 913                 if (!amdgpu_sriov_vf(adev)) {
 914                         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 915                                 /* unhalt engine */
 916                                 temp = RREG32_SDMA(i, regSDMA_F32_CNTL);
 917                                 temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0);
 918                                 WREG32_SDMA(i, regSDMA_F32_CNTL, temp);
 919                         }
 920                 }
 921         }
 922
 923         if (amdgpu_sriov_vf(adev)) {
 924                 sdma_v4_4_2_inst_ctx_switch_enable(adev, true, inst_mask);
 925                 sdma_v4_4_2_inst_enable(adev, true, inst_mask);
 926         } else {
 927                 r = sdma_v4_4_2_inst_rlc_resume(adev, inst_mask);
 928                 if (r)
 929                         return r;
 930         }
 931
 932         tmp_mask = inst_mask;
 933         for_each_inst(i, tmp_mask) {
 934                 ring = &adev->sdma.instance[i].ring;
 935
 936                 r = amdgpu_ring_test_helper(ring);
 937                 if (r)
 938                         return r;
 939
 940                 if (adev->sdma.has_page_queue) {
 941                         struct amdgpu_ring *page = &adev->sdma.instance[i].page;
 942
 943                         r = amdgpu_ring_test_helper(page);
 944                         if (r)
 945                                 return r;
 946                 }
 947         }
 948
 949         return r;
 950 }
 951
 952 /**
 953  * sdma_v4_4_2_ring_test_ring - simple async dma engine test
 954  *
 955  * @ring: amdgpu_ring structure holding ring information
 956  *
 957  * Test the DMA engine by writing using it to write an
 958  * value to memory.
 959  * Returns 0 for success, error for failure.
 960  */
 961 static int sdma_v4_4_2_ring_test_ring(struct amdgpu_ring *ring)
 962 {
 963         struct amdgpu_device *adev = ring->adev;
 964         unsigned i;
 965         unsigned index;
 966         int r;
 967         u32 tmp;
 968         u64 gpu_addr;
 969
 970         r = amdgpu_device_wb_get(adev, &index);
 971         if (r)
 972                 return r;
 973
 974         gpu_addr = adev->wb.gpu_addr + (index * 4);
 975         tmp = 0xCAFEDEAD;
 976         adev->wb.wb[index] = cpu_to_le32(tmp);
 977
 978         r = amdgpu_ring_alloc(ring, 5);
 979         if (r)
 980                 goto error_free_wb;
 981
 982         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 983                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 984         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 985         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 986         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 987         amdgpu_ring_write(ring, 0xDEADBEEF);
 988         amdgpu_ring_commit(ring);
 989
 990         for (i = 0; i < adev->usec_timeout; i++) {
 991                 tmp = le32_to_cpu(adev->wb.wb[index]);
 992                 if (tmp == 0xDEADBEEF)
 993                         break;
 994                 udelay(1);
 995         }
 996
 997         if (i >= adev->usec_timeout)
 998                 r = -ETIMEDOUT;
 999
1000 error_free_wb:
1001         amdgpu_device_wb_free(adev, index);
1002         return r;
1003 }
1004
1005 /**
1006  * sdma_v4_4_2_ring_test_ib - test an IB on the DMA engine
1007  *
1008  * @ring: amdgpu_ring structure holding ring information
1009  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1010  *
1011  * Test a simple IB in the DMA ring.
1012  * Returns 0 on success, error on failure.
1013  */
1014 static int sdma_v4_4_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1015 {
1016         struct amdgpu_device *adev = ring->adev;
1017         struct amdgpu_ib ib;
1018         struct dma_fence *f = NULL;
1019         unsigned index;
1020         long r;
1021         u32 tmp = 0;
1022         u64 gpu_addr;
1023
1024         r = amdgpu_device_wb_get(adev, &index);
1025         if (r)
1026                 return r;
1027
1028         gpu_addr = adev->wb.gpu_addr + (index * 4);
1029         tmp = 0xCAFEDEAD;
1030         adev->wb.wb[index] = cpu_to_le32(tmp);
1031         memset(&ib, 0, sizeof(ib));
1032         r = amdgpu_ib_get(adev, NULL, 256,
1033                                         AMDGPU_IB_POOL_DIRECT, &ib);
1034         if (r)
1035                 goto err0;
1036
1037         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1038                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1039         ib.ptr[1] = lower_32_bits(gpu_addr);
1040         ib.ptr[2] = upper_32_bits(gpu_addr);
1041         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1042         ib.ptr[4] = 0xDEADBEEF;
1043         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1044         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1045         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1046         ib.length_dw = 8;
1047
1048         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1049         if (r)
1050                 goto err1;
1051
1052         r = dma_fence_wait_timeout(f, false, timeout);
1053         if (r == 0) {
1054                 r = -ETIMEDOUT;
1055                 goto err1;
1056         } else if (r < 0) {
1057                 goto err1;
1058         }
1059         tmp = le32_to_cpu(adev->wb.wb[index]);
1060         if (tmp == 0xDEADBEEF)
1061                 r = 0;
1062         else
1063                 r = -EINVAL;
1064
1065 err1:
1066         amdgpu_ib_free(adev, &ib, NULL);
1067         dma_fence_put(f);
1068 err0:
1069         amdgpu_device_wb_free(adev, index);
1070         return r;
1071 }
1072
1073
1074 /**
1075  * sdma_v4_4_2_vm_copy_pte - update PTEs by copying them from the GART
1076  *
1077  * @ib: indirect buffer to fill with commands
1078  * @pe: addr of the page entry
1079  * @src: src addr to copy from
1080  * @count: number of page entries to update
1081  *
1082  * Update PTEs by copying them from the GART using sDMA.
1083  */
1084 static void sdma_v4_4_2_vm_copy_pte(struct amdgpu_ib *ib,
1085                                   uint64_t pe, uint64_t src,
1086                                   unsigned count)
1087 {
1088         unsigned bytes = count * 8;
1089
1090         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1091                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1092         ib->ptr[ib->length_dw++] = bytes - 1;
1093         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1094         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1095         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1096         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1097         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1098
1099 }
1100
1101 /**
1102  * sdma_v4_4_2_vm_write_pte - update PTEs by writing them manually
1103  *
1104  * @ib: indirect buffer to fill with commands
1105  * @pe: addr of the page entry
1106  * @value: dst addr to write into pe
1107  * @count: number of page entries to update
1108  * @incr: increase next addr by incr bytes
1109  *
1110  * Update PTEs by writing them manually using sDMA.
1111  */
1112 static void sdma_v4_4_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1113                                    uint64_t value, unsigned count,
1114                                    uint32_t incr)
1115 {
1116         unsigned ndw = count * 2;
1117
1118         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1119                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1120         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1121         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1122         ib->ptr[ib->length_dw++] = ndw - 1;
1123         for (; ndw > 0; ndw -= 2) {
1124                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1125                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1126                 value += incr;
1127         }
1128 }
1129
1130 /**
1131  * sdma_v4_4_2_vm_set_pte_pde - update the page tables using sDMA
1132  *
1133  * @ib: indirect buffer to fill with commands
1134  * @pe: addr of the page entry
1135  * @addr: dst addr to write into pe
1136  * @count: number of page entries to update
1137  * @incr: increase next addr by incr bytes
1138  * @flags: access flags
1139  *
1140  * Update the page tables using sDMA.
1141  */
1142 static void sdma_v4_4_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1143                                      uint64_t pe,
1144                                      uint64_t addr, unsigned count,
1145                                      uint32_t incr, uint64_t flags)
1146 {
1147         /* for physically contiguous pages (vram) */
1148         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1149         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1150         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1151         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1152         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1153         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1154         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1155         ib->ptr[ib->length_dw++] = incr; /* increment size */
1156         ib->ptr[ib->length_dw++] = 0;
1157         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1158 }
1159
1160 /**
1161  * sdma_v4_4_2_ring_pad_ib - pad the IB to the required number of dw
1162  *
1163  * @ring: amdgpu_ring structure holding ring information
1164  * @ib: indirect buffer to fill with padding
1165  */
1166 static void sdma_v4_4_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1167 {
1168         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1169         u32 pad_count;
1170         int i;
1171
1172         pad_count = (-ib->length_dw) & 7;
1173         for (i = 0; i < pad_count; i++)
1174                 if (sdma && sdma->burst_nop && (i == 0))
1175                         ib->ptr[ib->length_dw++] =
1176                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1177                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1178                 else
1179                         ib->ptr[ib->length_dw++] =
1180                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1181 }
1182
1183
1184 /**
1185  * sdma_v4_4_2_ring_emit_pipeline_sync - sync the pipeline
1186  *
1187  * @ring: amdgpu_ring pointer
1188  *
1189  * Make sure all previous operations are completed (CIK).
1190  */
1191 static void sdma_v4_4_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1192 {
1193         uint32_t seq = ring->fence_drv.sync_seq;
1194         uint64_t addr = ring->fence_drv.gpu_addr;
1195
1196         /* wait for idle */
1197         sdma_v4_4_2_wait_reg_mem(ring, 1, 0,
1198                                addr & 0xfffffffc,
1199                                upper_32_bits(addr) & 0xffffffff,
1200                                seq, 0xffffffff, 4);
1201 }
1202
1203
1204 /**
1205  * sdma_v4_4_2_ring_emit_vm_flush - vm flush using sDMA
1206  *
1207  * @ring: amdgpu_ring pointer
1208  * @vmid: vmid number to use
1209  * @pd_addr: address
1210  *
1211  * Update the page table base and flush the VM TLB
1212  * using sDMA.
1213  */
1214 static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1215                                          unsigned vmid, uint64_t pd_addr)
1216 {
1217         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1218 }
1219
1220 static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,
1221                                      uint32_t reg, uint32_t val)
1222 {
1223         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1224                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1225         amdgpu_ring_write(ring, reg);
1226         amdgpu_ring_write(ring, val);
1227 }
1228
1229 static void sdma_v4_4_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1230                                          uint32_t val, uint32_t mask)
1231 {
1232         sdma_v4_4_2_wait_reg_mem(ring, 0, 0, reg, 0, val, mask, 10);
1233 }
1234
1235 static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev)
1236 {
1237         switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1238         case IP_VERSION(4, 4, 2):
1239         case IP_VERSION(4, 4, 5):
1240                 return false;
1241         default:
1242                 return false;
1243         }
1244 }
1245
1246 static int sdma_v4_4_2_early_init(void *handle)
1247 {
1248         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1249         int r;
1250
1251         r = sdma_v4_4_2_init_microcode(adev);
1252         if (r)
1253                 return r;
1254
1255         /* TODO: Page queue breaks driver reload under SRIOV */
1256         if (sdma_v4_4_2_fw_support_paging_queue(adev))
1257                 adev->sdma.has_page_queue = true;
1258
1259         sdma_v4_4_2_set_ring_funcs(adev);
1260         sdma_v4_4_2_set_buffer_funcs(adev);
1261         sdma_v4_4_2_set_vm_pte_funcs(adev);
1262         sdma_v4_4_2_set_irq_funcs(adev);
1263         sdma_v4_4_2_set_ras_funcs(adev);
1264
1265         return 0;
1266 }
1267
1268 #if 0
1269 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1270                 void *err_data,
1271                 struct amdgpu_iv_entry *entry);
1272 #endif
1273
1274 static int sdma_v4_4_2_late_init(void *handle)
1275 {
1276         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277 #if 0
1278         struct ras_ih_if ih_info = {
1279                 .cb = sdma_v4_4_2_process_ras_data_cb,
1280         };
1281 #endif
1282         if (!amdgpu_persistent_edc_harvesting_supported(adev))
1283                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__SDMA);
1284
1285         return 0;
1286 }
1287
1288 static int sdma_v4_4_2_sw_init(void *handle)
1289 {
1290         struct amdgpu_ring *ring;
1291         int r, i;
1292         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1293         u32 aid_id;
1294
1295         /* SDMA trap event */
1296         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1297                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1298                                       SDMA0_4_0__SRCID__SDMA_TRAP,
1299                                       &adev->sdma.trap_irq);
1300                 if (r)
1301                         return r;
1302         }
1303
1304         /* SDMA SRAM ECC event */
1305         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1306                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1307                                       SDMA0_4_0__SRCID__SDMA_SRAM_ECC,
1308                                       &adev->sdma.ecc_irq);
1309                 if (r)
1310                         return r;
1311         }
1312
1313         /* SDMA VM_HOLE/DOORBELL_INV/POLL_TIMEOUT/SRBM_WRITE_PROTECTION event*/
1314         for (i = 0; i < adev->sdma.num_inst_per_aid; i++) {
1315                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1316                                       SDMA0_4_0__SRCID__SDMA_VM_HOLE,
1317                                       &adev->sdma.vm_hole_irq);
1318                 if (r)
1319                         return r;
1320
1321                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1322                                       SDMA0_4_0__SRCID__SDMA_DOORBELL_INVALID,
1323                                       &adev->sdma.doorbell_invalid_irq);
1324                 if (r)
1325                         return r;
1326
1327                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1328                                       SDMA0_4_0__SRCID__SDMA_POLL_TIMEOUT,
1329                                       &adev->sdma.pool_timeout_irq);
1330                 if (r)
1331                         return r;
1332
1333                 r = amdgpu_irq_add_id(adev, sdma_v4_4_2_seq_to_irq_id(i),
1334                                       SDMA0_4_0__SRCID__SDMA_SRBMWRITE,
1335                                       &adev->sdma.srbm_write_irq);
1336                 if (r)
1337                         return r;
1338         }
1339
1340         for (i = 0; i < adev->sdma.num_instances; i++) {
1341                 ring = &adev->sdma.instance[i].ring;
1342                 ring->ring_obj = NULL;
1343                 ring->use_doorbell = true;
1344                 aid_id = adev->sdma.instance[i].aid_id;
1345
1346                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1347                                 ring->use_doorbell?"true":"false");
1348
1349                 /* doorbell size is 2 dwords, get DWORD offset */
1350                 ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
1351                 ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1352
1353                 sprintf(ring->name, "sdma%d.%d", aid_id,
1354                                 i % adev->sdma.num_inst_per_aid);
1355                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1356                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1357                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1358                 if (r)
1359                         return r;
1360
1361                 if (adev->sdma.has_page_queue) {
1362                         ring = &adev->sdma.instance[i].page;
1363                         ring->ring_obj = NULL;
1364                         ring->use_doorbell = true;
1365
1366                         /* doorbell index of page queue is assigned right after
1367                          * gfx queue on the same instance
1368                          */
1369                         ring->doorbell_index =
1370                                 (adev->doorbell_index.sdma_engine[i] + 1) << 1;
1371                         ring->vm_hub = AMDGPU_MMHUB0(aid_id);
1372
1373                         sprintf(ring->name, "page%d.%d", aid_id,
1374                                         i % adev->sdma.num_inst_per_aid);
1375                         r = amdgpu_ring_init(adev, ring, 1024,
1376                                              &adev->sdma.trap_irq,
1377                                              AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1378                                              AMDGPU_RING_PRIO_DEFAULT, NULL);
1379                         if (r)
1380                                 return r;
1381                 }
1382         }
1383
1384         if (amdgpu_sdma_ras_sw_init(adev)) {
1385                 dev_err(adev->dev, "fail to initialize sdma ras block\n");
1386                 return -EINVAL;
1387         }
1388
1389         return r;
1390 }
1391
1392 static int sdma_v4_4_2_sw_fini(void *handle)
1393 {
1394         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1395         int i;
1396
1397         for (i = 0; i < adev->sdma.num_instances; i++) {
1398                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1399                 if (adev->sdma.has_page_queue)
1400                         amdgpu_ring_fini(&adev->sdma.instance[i].page);
1401         }
1402
1403         if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2) ||
1404             amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5))
1405                 amdgpu_sdma_destroy_inst_ctx(adev, true);
1406         else
1407                 amdgpu_sdma_destroy_inst_ctx(adev, false);
1408
1409         return 0;
1410 }
1411
1412 static int sdma_v4_4_2_hw_init(void *handle)
1413 {
1414         int r;
1415         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1416         uint32_t inst_mask;
1417
1418         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1419         if (!amdgpu_sriov_vf(adev))
1420                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
1421
1422         r = sdma_v4_4_2_inst_start(adev, inst_mask);
1423
1424         return r;
1425 }
1426
1427 static int sdma_v4_4_2_hw_fini(void *handle)
1428 {
1429         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1430         uint32_t inst_mask;
1431         int i;
1432
1433         if (amdgpu_sriov_vf(adev))
1434                 return 0;
1435
1436         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1437         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
1438                 for (i = 0; i < adev->sdma.num_instances; i++) {
1439                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
1440                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
1441                 }
1442         }
1443
1444         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
1445         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
1446
1447         return 0;
1448 }
1449
1450 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1451                                              enum amd_clockgating_state state);
1452
1453 static int sdma_v4_4_2_suspend(void *handle)
1454 {
1455         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1456
1457         if (amdgpu_in_reset(adev))
1458                 sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
1459
1460         return sdma_v4_4_2_hw_fini(adev);
1461 }
1462
1463 static int sdma_v4_4_2_resume(void *handle)
1464 {
1465         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1466
1467         return sdma_v4_4_2_hw_init(adev);
1468 }
1469
1470 static bool sdma_v4_4_2_is_idle(void *handle)
1471 {
1472         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1473         u32 i;
1474
1475         for (i = 0; i < adev->sdma.num_instances; i++) {
1476                 u32 tmp = RREG32_SDMA(i, regSDMA_STATUS_REG);
1477
1478                 if (!(tmp & SDMA_STATUS_REG__IDLE_MASK))
1479                         return false;
1480         }
1481
1482         return true;
1483 }
1484
1485 static int sdma_v4_4_2_wait_for_idle(void *handle)
1486 {
1487         unsigned i, j;
1488         u32 sdma[AMDGPU_MAX_SDMA_INSTANCES];
1489         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1490
1491         for (i = 0; i < adev->usec_timeout; i++) {
1492                 for (j = 0; j < adev->sdma.num_instances; j++) {
1493                         sdma[j] = RREG32_SDMA(j, regSDMA_STATUS_REG);
1494                         if (!(sdma[j] & SDMA_STATUS_REG__IDLE_MASK))
1495                                 break;
1496                 }
1497                 if (j == adev->sdma.num_instances)
1498                         return 0;
1499                 udelay(1);
1500         }
1501         return -ETIMEDOUT;
1502 }
1503
1504 static int sdma_v4_4_2_soft_reset(void *handle)
1505 {
1506         /* todo */
1507
1508         return 0;
1509 }
1510
1511 static int sdma_v4_4_2_set_trap_irq_state(struct amdgpu_device *adev,
1512                                         struct amdgpu_irq_src *source,
1513                                         unsigned type,
1514                                         enum amdgpu_interrupt_state state)
1515 {
1516         u32 sdma_cntl;
1517
1518         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1519         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE,
1520                        state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1521         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1522
1523         return 0;
1524 }
1525
1526 static int sdma_v4_4_2_process_trap_irq(struct amdgpu_device *adev,
1527                                       struct amdgpu_irq_src *source,
1528                                       struct amdgpu_iv_entry *entry)
1529 {
1530         uint32_t instance, i;
1531
1532         DRM_DEBUG("IH: SDMA trap\n");
1533         instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1534
1535         /* Client id gives the SDMA instance in AID. To know the exact SDMA
1536          * instance, interrupt entry gives the node id which corresponds to the AID instance.
1537          * Match node id with the AID id associated with the SDMA instance. */
1538         for (i = instance; i < adev->sdma.num_instances;
1539              i += adev->sdma.num_inst_per_aid) {
1540                 if (adev->sdma.instance[i].aid_id ==
1541                     node_id_to_phys_map[entry->node_id])
1542                         break;
1543         }
1544
1545         if (i >= adev->sdma.num_instances) {
1546                 dev_WARN_ONCE(
1547                         adev->dev, 1,
1548                         "Couldn't find the right sdma instance in trap handler");
1549                 return 0;
1550         }
1551
1552         switch (entry->ring_id) {
1553         case 0:
1554                 amdgpu_fence_process(&adev->sdma.instance[i].ring);
1555                 break;
1556         default:
1557                 break;
1558         }
1559         return 0;
1560 }
1561
1562 #if 0
1563 static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev,
1564                 void *err_data,
1565                 struct amdgpu_iv_entry *entry)
1566 {
1567         int instance;
1568
1569         /* When “Full RAS” is enabled, the per-IP interrupt sources should
1570          * be disabled and the driver should only look for the aggregated
1571          * interrupt via sync flood
1572          */
1573         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA))
1574                 goto out;
1575
1576         instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1577         if (instance < 0)
1578                 goto out;
1579
1580         amdgpu_sdma_process_ras_data_cb(adev, err_data, entry);
1581
1582 out:
1583         return AMDGPU_RAS_SUCCESS;
1584 }
1585 #endif
1586
1587 static int sdma_v4_4_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1588                                               struct amdgpu_irq_src *source,
1589                                               struct amdgpu_iv_entry *entry)
1590 {
1591         int instance;
1592
1593         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1594
1595         instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1596         if (instance < 0)
1597                 return 0;
1598
1599         switch (entry->ring_id) {
1600         case 0:
1601                 drm_sched_fault(&adev->sdma.instance[instance].ring.sched);
1602                 break;
1603         }
1604         return 0;
1605 }
1606
1607 static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
1608                                         struct amdgpu_irq_src *source,
1609                                         unsigned type,
1610                                         enum amdgpu_interrupt_state state)
1611 {
1612         u32 sdma_cntl;
1613
1614         sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
1615         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
1616                                         state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1617         WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
1618
1619         return 0;
1620 }
1621
1622 static int sdma_v4_4_2_print_iv_entry(struct amdgpu_device *adev,
1623                                               struct amdgpu_iv_entry *entry)
1624 {
1625         int instance;
1626         struct amdgpu_task_info *task_info;
1627         u64 addr;
1628
1629         instance = sdma_v4_4_2_irq_id_to_seq(adev, entry->client_id);
1630         if (instance < 0 || instance >= adev->sdma.num_instances) {
1631                 dev_err(adev->dev, "sdma instance invalid %d\n", instance);
1632                 return -EINVAL;
1633         }
1634
1635         addr = (u64)entry->src_data[0] << 12;
1636         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
1637
1638         dev_dbg_ratelimited(adev->dev,
1639                             "[sdma%d] address:0x%016llx src_id:%u ring:%u vmid:%u pasid:%u\n",
1640                             instance, addr, entry->src_id, entry->ring_id, entry->vmid,
1641                             entry->pasid);
1642
1643         task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
1644         if (task_info) {
1645                 dev_dbg_ratelimited(adev->dev, " for process %s pid %d thread %s pid %d\n",
1646                                     task_info->process_name, task_info->tgid,
1647                                     task_info->task_name, task_info->pid);
1648                 amdgpu_vm_put_task_info(task_info);
1649         }
1650
1651         return 0;
1652 }
1653
1654 static int sdma_v4_4_2_process_vm_hole_irq(struct amdgpu_device *adev,
1655                                               struct amdgpu_irq_src *source,
1656                                               struct amdgpu_iv_entry *entry)
1657 {
1658         dev_dbg_ratelimited(adev->dev, "MC or SEM address in VM hole\n");
1659         sdma_v4_4_2_print_iv_entry(adev, entry);
1660         return 0;
1661 }
1662
1663 static int sdma_v4_4_2_process_doorbell_invalid_irq(struct amdgpu_device *adev,
1664                                               struct amdgpu_irq_src *source,
1665                                               struct amdgpu_iv_entry *entry)
1666 {
1667
1668         dev_dbg_ratelimited(adev->dev, "SDMA received a doorbell from BIF with byte_enable !=0xff\n");
1669         sdma_v4_4_2_print_iv_entry(adev, entry);
1670         return 0;
1671 }
1672
1673 static int sdma_v4_4_2_process_pool_timeout_irq(struct amdgpu_device *adev,
1674                                               struct amdgpu_irq_src *source,
1675                                               struct amdgpu_iv_entry *entry)
1676 {
1677         dev_dbg_ratelimited(adev->dev,
1678                 "Polling register/memory timeout executing POLL_REG/MEM with finite timer\n");
1679         sdma_v4_4_2_print_iv_entry(adev, entry);
1680         return 0;
1681 }
1682
1683 static int sdma_v4_4_2_process_srbm_write_irq(struct amdgpu_device *adev,
1684                                               struct amdgpu_irq_src *source,
1685                                               struct amdgpu_iv_entry *entry)
1686 {
1687         dev_dbg_ratelimited(adev->dev,
1688                 "SDMA gets an Register Write SRBM_WRITE command in non-privilege command buffer\n");
1689         sdma_v4_4_2_print_iv_entry(adev, entry);
1690         return 0;
1691 }
1692
1693 static void sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1694         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1695 {
1696         uint32_t data, def;
1697         int i;
1698
1699         /* leave as default if it is not driver controlled */
1700         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS))
1701                 return;
1702
1703         if (enable) {
1704                 for_each_inst(i, inst_mask) {
1705                         /* 1-not override: enable sdma mem light sleep */
1706                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1707                         data |= SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1708                         if (def != data)
1709                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1710                 }
1711         } else {
1712                 for_each_inst(i, inst_mask) {
1713                         /* 0-override:disable sdma mem light sleep */
1714                         def = data = RREG32_SDMA(i, regSDMA_POWER_CNTL);
1715                         data &= ~SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1716                         if (def != data)
1717                                 WREG32_SDMA(i, regSDMA_POWER_CNTL, data);
1718                 }
1719         }
1720 }
1721
1722 static void sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1723         struct amdgpu_device *adev, bool enable, uint32_t inst_mask)
1724 {
1725         uint32_t data, def;
1726         int i;
1727
1728         /* leave as default if it is not driver controlled */
1729         if (!(adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG))
1730                 return;
1731
1732         if (enable) {
1733                 for_each_inst(i, inst_mask) {
1734                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1735                         data &= ~(SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1736                                   SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1737                                   SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1738                                   SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1739                                   SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1740                                   SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1741                         if (def != data)
1742                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1743                 }
1744         } else {
1745                 for_each_inst(i, inst_mask) {
1746                         def = data = RREG32_SDMA(i, regSDMA_CLK_CTRL);
1747                         data |= (SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1748                                  SDMA_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1749                                  SDMA_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1750                                  SDMA_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1751                                  SDMA_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1752                                  SDMA_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1753                         if (def != data)
1754                                 WREG32_SDMA(i, regSDMA_CLK_CTRL, data);
1755                 }
1756         }
1757 }
1758
1759 static int sdma_v4_4_2_set_clockgating_state(void *handle,
1760                                           enum amd_clockgating_state state)
1761 {
1762         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1763         uint32_t inst_mask;
1764
1765         if (amdgpu_sriov_vf(adev))
1766                 return 0;
1767
1768         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
1769
1770         sdma_v4_4_2_inst_update_medium_grain_clock_gating(
1771                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1772         sdma_v4_4_2_inst_update_medium_grain_light_sleep(
1773                 adev, state == AMD_CG_STATE_GATE, inst_mask);
1774         return 0;
1775 }
1776
1777 static int sdma_v4_4_2_set_powergating_state(void *handle,
1778                                           enum amd_powergating_state state)
1779 {
1780         return 0;
1781 }
1782
1783 static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags)
1784 {
1785         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1786         int data;
1787
1788         if (amdgpu_sriov_vf(adev))
1789                 *flags = 0;
1790
1791         /* AMD_CG_SUPPORT_SDMA_MGCG */
1792         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL));
1793         if (!(data & SDMA_CLK_CTRL__SOFT_OVERRIDE5_MASK))
1794                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1795
1796         /* AMD_CG_SUPPORT_SDMA_LS */
1797         data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL));
1798         if (data & SDMA_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1799                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1800 }
1801
1802 const struct amd_ip_funcs sdma_v4_4_2_ip_funcs = {
1803         .name = "sdma_v4_4_2",
1804         .early_init = sdma_v4_4_2_early_init,
1805         .late_init = sdma_v4_4_2_late_init,
1806         .sw_init = sdma_v4_4_2_sw_init,
1807         .sw_fini = sdma_v4_4_2_sw_fini,
1808         .hw_init = sdma_v4_4_2_hw_init,
1809         .hw_fini = sdma_v4_4_2_hw_fini,
1810         .suspend = sdma_v4_4_2_suspend,
1811         .resume = sdma_v4_4_2_resume,
1812         .is_idle = sdma_v4_4_2_is_idle,
1813         .wait_for_idle = sdma_v4_4_2_wait_for_idle,
1814         .soft_reset = sdma_v4_4_2_soft_reset,
1815         .set_clockgating_state = sdma_v4_4_2_set_clockgating_state,
1816         .set_powergating_state = sdma_v4_4_2_set_powergating_state,
1817         .get_clockgating_state = sdma_v4_4_2_get_clockgating_state,
1818 };
1819
1820 static const struct amdgpu_ring_funcs sdma_v4_4_2_ring_funcs = {
1821         .type = AMDGPU_RING_TYPE_SDMA,
1822         .align_mask = 0xff,
1823         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1824         .support_64bit_ptrs = true,
1825         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1826         .get_wptr = sdma_v4_4_2_ring_get_wptr,
1827         .set_wptr = sdma_v4_4_2_ring_set_wptr,
1828         .emit_frame_size =
1829                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1830                 3 + /* hdp invalidate */
1831                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1832                 /* sdma_v4_4_2_ring_emit_vm_flush */
1833                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1834                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1835                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1836         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1837         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1838         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1839         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1840         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1841         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1842         .test_ring = sdma_v4_4_2_ring_test_ring,
1843         .test_ib = sdma_v4_4_2_ring_test_ib,
1844         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1845         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1846         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1847         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1848         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1849 };
1850
1851 static const struct amdgpu_ring_funcs sdma_v4_4_2_page_ring_funcs = {
1852         .type = AMDGPU_RING_TYPE_SDMA,
1853         .align_mask = 0xff,
1854         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1855         .support_64bit_ptrs = true,
1856         .get_rptr = sdma_v4_4_2_ring_get_rptr,
1857         .get_wptr = sdma_v4_4_2_page_ring_get_wptr,
1858         .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
1859         .emit_frame_size =
1860                 6 + /* sdma_v4_4_2_ring_emit_hdp_flush */
1861                 3 + /* hdp invalidate */
1862                 6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */
1863                 /* sdma_v4_4_2_ring_emit_vm_flush */
1864                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1865                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1866                 10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */
1867         .emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */
1868         .emit_ib = sdma_v4_4_2_ring_emit_ib,
1869         .emit_fence = sdma_v4_4_2_ring_emit_fence,
1870         .emit_pipeline_sync = sdma_v4_4_2_ring_emit_pipeline_sync,
1871         .emit_vm_flush = sdma_v4_4_2_ring_emit_vm_flush,
1872         .emit_hdp_flush = sdma_v4_4_2_ring_emit_hdp_flush,
1873         .test_ring = sdma_v4_4_2_ring_test_ring,
1874         .test_ib = sdma_v4_4_2_ring_test_ib,
1875         .insert_nop = sdma_v4_4_2_ring_insert_nop,
1876         .pad_ib = sdma_v4_4_2_ring_pad_ib,
1877         .emit_wreg = sdma_v4_4_2_ring_emit_wreg,
1878         .emit_reg_wait = sdma_v4_4_2_ring_emit_reg_wait,
1879         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1880 };
1881
1882 static void sdma_v4_4_2_set_ring_funcs(struct amdgpu_device *adev)
1883 {
1884         int i, dev_inst;
1885
1886         for (i = 0; i < adev->sdma.num_instances; i++) {
1887                 adev->sdma.instance[i].ring.funcs = &sdma_v4_4_2_ring_funcs;
1888                 adev->sdma.instance[i].ring.me = i;
1889                 if (adev->sdma.has_page_queue) {
1890                         adev->sdma.instance[i].page.funcs =
1891                                 &sdma_v4_4_2_page_ring_funcs;
1892                         adev->sdma.instance[i].page.me = i;
1893                 }
1894
1895                 dev_inst = GET_INST(SDMA0, i);
1896                 /* AID to which SDMA belongs depends on physical instance */
1897                 adev->sdma.instance[i].aid_id =
1898                         dev_inst / adev->sdma.num_inst_per_aid;
1899         }
1900 }
1901
1902 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_trap_irq_funcs = {
1903         .set = sdma_v4_4_2_set_trap_irq_state,
1904         .process = sdma_v4_4_2_process_trap_irq,
1905 };
1906
1907 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_illegal_inst_irq_funcs = {
1908         .process = sdma_v4_4_2_process_illegal_inst_irq,
1909 };
1910
1911 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_ecc_irq_funcs = {
1912         .set = sdma_v4_4_2_set_ecc_irq_state,
1913         .process = amdgpu_sdma_process_ecc_irq,
1914 };
1915
1916 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_vm_hole_irq_funcs = {
1917         .process = sdma_v4_4_2_process_vm_hole_irq,
1918 };
1919
1920 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_doorbell_invalid_irq_funcs = {
1921         .process = sdma_v4_4_2_process_doorbell_invalid_irq,
1922 };
1923
1924 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_pool_timeout_irq_funcs = {
1925         .process = sdma_v4_4_2_process_pool_timeout_irq,
1926 };
1927
1928 static const struct amdgpu_irq_src_funcs sdma_v4_4_2_srbm_write_irq_funcs = {
1929         .process = sdma_v4_4_2_process_srbm_write_irq,
1930 };
1931
1932 static void sdma_v4_4_2_set_irq_funcs(struct amdgpu_device *adev)
1933 {
1934         adev->sdma.trap_irq.num_types = adev->sdma.num_instances;
1935         adev->sdma.ecc_irq.num_types = adev->sdma.num_instances;
1936         adev->sdma.vm_hole_irq.num_types = adev->sdma.num_instances;
1937         adev->sdma.doorbell_invalid_irq.num_types = adev->sdma.num_instances;
1938         adev->sdma.pool_timeout_irq.num_types = adev->sdma.num_instances;
1939         adev->sdma.srbm_write_irq.num_types = adev->sdma.num_instances;
1940
1941         adev->sdma.trap_irq.funcs = &sdma_v4_4_2_trap_irq_funcs;
1942         adev->sdma.illegal_inst_irq.funcs = &sdma_v4_4_2_illegal_inst_irq_funcs;
1943         adev->sdma.ecc_irq.funcs = &sdma_v4_4_2_ecc_irq_funcs;
1944         adev->sdma.vm_hole_irq.funcs = &sdma_v4_4_2_vm_hole_irq_funcs;
1945         adev->sdma.doorbell_invalid_irq.funcs = &sdma_v4_4_2_doorbell_invalid_irq_funcs;
1946         adev->sdma.pool_timeout_irq.funcs = &sdma_v4_4_2_pool_timeout_irq_funcs;
1947         adev->sdma.srbm_write_irq.funcs = &sdma_v4_4_2_srbm_write_irq_funcs;
1948 }
1949
1950 /**
1951  * sdma_v4_4_2_emit_copy_buffer - copy buffer using the sDMA engine
1952  *
1953  * @ib: indirect buffer to copy to
1954  * @src_offset: src GPU address
1955  * @dst_offset: dst GPU address
1956  * @byte_count: number of bytes to xfer
1957  * @copy_flags: copy flags for the buffers
1958  *
1959  * Copy GPU buffers using the DMA engine.
1960  * Used by the amdgpu ttm implementation to move pages if
1961  * registered as the asic copy callback.
1962  */
1963 static void sdma_v4_4_2_emit_copy_buffer(struct amdgpu_ib *ib,
1964                                        uint64_t src_offset,
1965                                        uint64_t dst_offset,
1966                                        uint32_t byte_count,
1967                                        uint32_t copy_flags)
1968 {
1969         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1970                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1971                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1972         ib->ptr[ib->length_dw++] = byte_count - 1;
1973         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1974         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1975         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1976         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1977         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1978 }
1979
1980 /**
1981  * sdma_v4_4_2_emit_fill_buffer - fill buffer using the sDMA engine
1982  *
1983  * @ib: indirect buffer to copy to
1984  * @src_data: value to write to buffer
1985  * @dst_offset: dst GPU address
1986  * @byte_count: number of bytes to xfer
1987  *
1988  * Fill GPU buffers using the DMA engine.
1989  */
1990 static void sdma_v4_4_2_emit_fill_buffer(struct amdgpu_ib *ib,
1991                                        uint32_t src_data,
1992                                        uint64_t dst_offset,
1993                                        uint32_t byte_count)
1994 {
1995         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1996         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1997         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1998         ib->ptr[ib->length_dw++] = src_data;
1999         ib->ptr[ib->length_dw++] = byte_count - 1;
2000 }
2001
2002 static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
2003         .copy_max_bytes = 0x400000,
2004         .copy_num_dw = 7,
2005         .emit_copy_buffer = sdma_v4_4_2_emit_copy_buffer,
2006
2007         .fill_max_bytes = 0x400000,
2008         .fill_num_dw = 5,
2009         .emit_fill_buffer = sdma_v4_4_2_emit_fill_buffer,
2010 };
2011
2012 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
2013 {
2014         adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
2015         if (adev->sdma.has_page_queue)
2016                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
2017         else
2018                 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
2019 }
2020
2021 static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
2022         .copy_pte_num_dw = 7,
2023         .copy_pte = sdma_v4_4_2_vm_copy_pte,
2024
2025         .write_pte = sdma_v4_4_2_vm_write_pte,
2026         .set_pte_pde = sdma_v4_4_2_vm_set_pte_pde,
2027 };
2028
2029 static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
2030 {
2031         struct drm_gpu_scheduler *sched;
2032         unsigned i;
2033
2034         adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
2035         for (i = 0; i < adev->sdma.num_instances; i++) {
2036                 if (adev->sdma.has_page_queue)
2037                         sched = &adev->sdma.instance[i].page.sched;
2038                 else
2039                         sched = &adev->sdma.instance[i].ring.sched;
2040                 adev->vm_manager.vm_pte_scheds[i] = sched;
2041         }
2042         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
2043 }
2044
2045 const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block = {
2046         .type = AMD_IP_BLOCK_TYPE_SDMA,
2047         .major = 4,
2048         .minor = 4,
2049         .rev = 2,
2050         .funcs = &sdma_v4_4_2_ip_funcs,
2051 };
2052
2053 static int sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask)
2054 {
2055         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2056         int r;
2057
2058         if (!amdgpu_sriov_vf(adev))
2059                 sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
2060
2061         r = sdma_v4_4_2_inst_start(adev, inst_mask);
2062
2063         return r;
2064 }
2065
2066 static int sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask)
2067 {
2068         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2069         uint32_t tmp_mask = inst_mask;
2070         int i;
2071
2072         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2073                 for_each_inst(i, tmp_mask) {
2074                         amdgpu_irq_put(adev, &adev->sdma.ecc_irq,
2075                                        AMDGPU_SDMA_IRQ_INSTANCE0 + i);
2076                 }
2077         }
2078
2079         sdma_v4_4_2_inst_ctx_switch_enable(adev, false, inst_mask);
2080         sdma_v4_4_2_inst_enable(adev, false, inst_mask);
2081
2082         return 0;
2083 }
2084
2085 struct amdgpu_xcp_ip_funcs sdma_v4_4_2_xcp_funcs = {
2086         .suspend = &sdma_v4_4_2_xcp_suspend,
2087         .resume = &sdma_v4_4_2_xcp_resume
2088 };
2089
2090 static const struct amdgpu_ras_err_status_reg_entry sdma_v4_2_2_ue_reg_list[] = {
2091         {AMDGPU_RAS_REG_ENTRY(SDMA0, 0, regSDMA_UE_ERR_STATUS_LO, regSDMA_UE_ERR_STATUS_HI),
2092         1, (AMDGPU_RAS_ERR_INFO_VALID | AMDGPU_RAS_ERR_STATUS_VALID), "SDMA"},
2093 };
2094
2095 static const struct amdgpu_ras_memory_id_entry sdma_v4_4_2_ras_memory_list[] = {
2096         {AMDGPU_SDMA_MBANK_DATA_BUF0, "SDMA_MBANK_DATA_BUF0"},
2097         {AMDGPU_SDMA_MBANK_DATA_BUF1, "SDMA_MBANK_DATA_BUF1"},
2098         {AMDGPU_SDMA_MBANK_DATA_BUF2, "SDMA_MBANK_DATA_BUF2"},
2099         {AMDGPU_SDMA_MBANK_DATA_BUF3, "SDMA_MBANK_DATA_BUF3"},
2100         {AMDGPU_SDMA_MBANK_DATA_BUF4, "SDMA_MBANK_DATA_BUF4"},
2101         {AMDGPU_SDMA_MBANK_DATA_BUF5, "SDMA_MBANK_DATA_BUF5"},
2102         {AMDGPU_SDMA_MBANK_DATA_BUF6, "SDMA_MBANK_DATA_BUF6"},
2103         {AMDGPU_SDMA_MBANK_DATA_BUF7, "SDMA_MBANK_DATA_BUF7"},
2104         {AMDGPU_SDMA_MBANK_DATA_BUF8, "SDMA_MBANK_DATA_BUF8"},
2105         {AMDGPU_SDMA_MBANK_DATA_BUF9, "SDMA_MBANK_DATA_BUF9"},
2106         {AMDGPU_SDMA_MBANK_DATA_BUF10, "SDMA_MBANK_DATA_BUF10"},
2107         {AMDGPU_SDMA_MBANK_DATA_BUF11, "SDMA_MBANK_DATA_BUF11"},
2108         {AMDGPU_SDMA_MBANK_DATA_BUF12, "SDMA_MBANK_DATA_BUF12"},
2109         {AMDGPU_SDMA_MBANK_DATA_BUF13, "SDMA_MBANK_DATA_BUF13"},
2110         {AMDGPU_SDMA_MBANK_DATA_BUF14, "SDMA_MBANK_DATA_BUF14"},
2111         {AMDGPU_SDMA_MBANK_DATA_BUF15, "SDMA_MBANK_DATA_BUF15"},
2112         {AMDGPU_SDMA_UCODE_BUF, "SDMA_UCODE_BUF"},
2113         {AMDGPU_SDMA_RB_CMD_BUF, "SDMA_RB_CMD_BUF"},
2114         {AMDGPU_SDMA_IB_CMD_BUF, "SDMA_IB_CMD_BUF"},
2115         {AMDGPU_SDMA_UTCL1_RD_FIFO, "SDMA_UTCL1_RD_FIFO"},
2116         {AMDGPU_SDMA_UTCL1_RDBST_FIFO, "SDMA_UTCL1_RDBST_FIFO"},
2117         {AMDGPU_SDMA_UTCL1_WR_FIFO, "SDMA_UTCL1_WR_FIFO"},
2118         {AMDGPU_SDMA_DATA_LUT_FIFO, "SDMA_DATA_LUT_FIFO"},
2119         {AMDGPU_SDMA_SPLIT_DAT_BUF, "SDMA_SPLIT_DAT_BUF"},
2120 };
2121
2122 static void sdma_v4_4_2_inst_query_ras_error_count(struct amdgpu_device *adev,
2123                                                    uint32_t sdma_inst,
2124                                                    void *ras_err_status)
2125 {
2126         struct ras_err_data *err_data = (struct ras_err_data *)ras_err_status;
2127         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2128         unsigned long ue_count = 0;
2129         struct amdgpu_smuio_mcm_config_info mcm_info = {
2130                 .socket_id = adev->smuio.funcs->get_socket_id(adev),
2131                 .die_id = adev->sdma.instance[sdma_inst].aid_id,
2132         };
2133
2134         /* sdma v4_4_2 doesn't support query ce counts */
2135         amdgpu_ras_inst_query_ras_error_count(adev,
2136                                         sdma_v4_2_2_ue_reg_list,
2137                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2138                                         sdma_v4_4_2_ras_memory_list,
2139                                         ARRAY_SIZE(sdma_v4_4_2_ras_memory_list),
2140                                         sdma_dev_inst,
2141                                         AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
2142                                         &ue_count);
2143
2144         amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, NULL, ue_count);
2145 }
2146
2147 static void sdma_v4_4_2_query_ras_error_count(struct amdgpu_device *adev,
2148                                               void *ras_err_status)
2149 {
2150         uint32_t inst_mask;
2151         int i = 0;
2152
2153         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2154         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2155                 for_each_inst(i, inst_mask)
2156                         sdma_v4_4_2_inst_query_ras_error_count(adev, i, ras_err_status);
2157         } else {
2158                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2159         }
2160 }
2161
2162 static void sdma_v4_4_2_inst_reset_ras_error_count(struct amdgpu_device *adev,
2163                                                    uint32_t sdma_inst)
2164 {
2165         uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst);
2166
2167         amdgpu_ras_inst_reset_ras_error_count(adev,
2168                                         sdma_v4_2_2_ue_reg_list,
2169                                         ARRAY_SIZE(sdma_v4_2_2_ue_reg_list),
2170                                         sdma_dev_inst);
2171 }
2172
2173 static void sdma_v4_4_2_reset_ras_error_count(struct amdgpu_device *adev)
2174 {
2175         uint32_t inst_mask;
2176         int i = 0;
2177
2178         inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
2179         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA)) {
2180                 for_each_inst(i, inst_mask)
2181                         sdma_v4_4_2_inst_reset_ras_error_count(adev, i);
2182         } else {
2183                 dev_warn(adev->dev, "SDMA RAS is not supported\n");
2184         }
2185 }
2186
2187 static const struct amdgpu_ras_block_hw_ops sdma_v4_4_2_ras_hw_ops = {
2188         .query_ras_error_count = sdma_v4_4_2_query_ras_error_count,
2189         .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
2190 };
2191
2192 static int sdma_v4_4_2_aca_bank_parser(struct aca_handle *handle, struct aca_bank *bank,
2193                                        enum aca_smu_type type, void *data)
2194 {
2195         struct aca_bank_info info;
2196         u64 misc0;
2197         int ret;
2198
2199         ret = aca_bank_info_decode(bank, &info);
2200         if (ret)
2201                 return ret;
2202
2203         misc0 = bank->regs[ACA_REG_IDX_MISC0];
2204         switch (type) {
2205         case ACA_SMU_TYPE_UE:
2206                 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_UE,
2207                                                      1ULL);
2208                 break;
2209         case ACA_SMU_TYPE_CE:
2210                 ret = aca_error_cache_log_bank_error(handle, &info, ACA_ERROR_TYPE_CE,
2211                                                      ACA_REG__MISC0__ERRCNT(misc0));
2212                 break;
2213         default:
2214                 return -EINVAL;
2215         }
2216
2217         return ret;
2218 }
2219
2220 /* CODE_SDMA0 - CODE_SDMA4, reference to smu driver if header file */
2221 static int sdma_v4_4_2_err_codes[] = { 33, 34, 35, 36 };
2222
2223 static bool sdma_v4_4_2_aca_bank_is_valid(struct aca_handle *handle, struct aca_bank *bank,
2224                                           enum aca_smu_type type, void *data)
2225 {
2226         u32 instlo;
2227
2228         instlo = ACA_REG__IPID__INSTANCEIDLO(bank->regs[ACA_REG_IDX_IPID]);
2229         instlo &= GENMASK(31, 1);
2230
2231         if (instlo != mmSMNAID_AID0_MCA_SMU)
2232                 return false;
2233
2234         if (aca_bank_check_error_codes(handle->adev, bank,
2235                                        sdma_v4_4_2_err_codes,
2236                                        ARRAY_SIZE(sdma_v4_4_2_err_codes)))
2237                 return false;
2238
2239         return true;
2240 }
2241
2242 static const struct aca_bank_ops sdma_v4_4_2_aca_bank_ops = {
2243         .aca_bank_parser = sdma_v4_4_2_aca_bank_parser,
2244         .aca_bank_is_valid = sdma_v4_4_2_aca_bank_is_valid,
2245 };
2246
2247 static const struct aca_info sdma_v4_4_2_aca_info = {
2248         .hwip = ACA_HWIP_TYPE_SMU,
2249         .mask = ACA_ERROR_UE_MASK,
2250         .bank_ops = &sdma_v4_4_2_aca_bank_ops,
2251 };
2252
2253 static int sdma_v4_4_2_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
2254 {
2255         int r;
2256
2257         r = amdgpu_sdma_ras_late_init(adev, ras_block);
2258         if (r)
2259                 return r;
2260
2261         return amdgpu_ras_bind_aca(adev, AMDGPU_RAS_BLOCK__SDMA,
2262                                    &sdma_v4_4_2_aca_info, NULL);
2263 }
2264
2265 static struct amdgpu_sdma_ras sdma_v4_4_2_ras = {
2266         .ras_block = {
2267                 .hw_ops = &sdma_v4_4_2_ras_hw_ops,
2268                 .ras_late_init = sdma_v4_4_2_ras_late_init,
2269         },
2270 };
2271
2272 static void sdma_v4_4_2_set_ras_funcs(struct amdgpu_device *adev)
2273 {
2274         adev->sdma.ras = &sdma_v4_4_2_ras;
2275 }