drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <[email protected]>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <linux/clk.h>
  40 #include <linux/component.h>
  41 #include <linux/i2c.h>
  42 #include <linux/of_address.h>
  43 #include <linux/of_gpio.h>
  44 #include <linux/of_platform.h>
  45 #include <linux/pm_runtime.h>
  46 #include <linux/rational.h>
  47 #include <linux/reset.h>
  48 #include <sound/dmaengine_pcm.h>
  49 #include <sound/hdmi-codec.h>
  50 #include <sound/pcm_drm_eld.h>
  51 #include <sound/pcm_params.h>
  52 #include <sound/soc.h>
  53 #include "media/cec.h"
  54 #include "vc4_drv.h"
  55 #include "vc4_hdmi.h"
  56 #include "vc4_hdmi_regs.h"
  57 #include "vc4_regs.h"
  58
  59 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  60 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  61 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  62 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  63 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  64 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  65
  66 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  67 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  68 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  69 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  70
  71 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  72 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  73 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  74 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  75 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  76 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  77
  78 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  79 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  80
  81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE           BIT(0)
  82
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  85
  86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  88
  89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  90
  91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  93
  94 # define VC4_HD_M_SW_RST                        BIT(2)
  95 # define VC4_HD_M_ENABLE                        BIT(0)
  96
  97 #define CEC_CLOCK_FREQ 40000
  98
  99 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
 100
 101 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode)
 102 {
 103         return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK;
 104 }
 105
 106 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 107 {
 108         struct drm_info_node *node = (struct drm_info_node *)m->private;
 109         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 110         struct drm_printer p = drm_seq_file_printer(m);
 111
 112         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 113         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 114
 115         return 0;
 116 }
 117
 118 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 119 {
 120         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 121         udelay(1);
 122         HDMI_WRITE(HDMI_M_CTL, 0);
 123
 124         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 125
 126         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 127                    VC4_HDMI_SW_RESET_HDMI |
 128                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 129
 130         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 131 }
 132
 133 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 134 {
 135         reset_control_reset(vc4_hdmi->reset);
 136
 137         HDMI_WRITE(HDMI_DVP_CTL, 0);
 138
 139         HDMI_WRITE(HDMI_CLOCK_STOP,
 140                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 141 }
 142
 143 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 144 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 145 {
 146         u16 clk_cnt;
 147         u32 value;
 148
 149         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 150         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 151
 152         /*
 153          * Set the clock divider: the hsm_clock rate and this divider
 154          * setting will give a 40 kHz CEC clock.
 155          */
 156         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 157         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 158         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 159 }
 160 #else
 161 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 162 #endif
 163
 164 static enum drm_connector_status
 165 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 166 {
 167         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 168         bool connected = false;
 169
 170         if (vc4_hdmi->hpd_gpio &&
 171             gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) {
 172                 connected = true;
 173         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 174                 connected = true;
 175         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 176                 connected = true;
 177         }
 178
 179         if (connected) {
 180                 if (connector->status != connector_status_connected) {
 181                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 182
 183                         if (edid) {
 184                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 185                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 186                                 kfree(edid);
 187                         }
 188                 }
 189
 190                 return connector_status_connected;
 191         }
 192
 193         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 194         return connector_status_disconnected;
 195 }
 196
 197 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 198 {
 199         drm_connector_unregister(connector);
 200         drm_connector_cleanup(connector);
 201 }
 202
 203 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 204 {
 205         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 206         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 207         int ret = 0;
 208         struct edid *edid;
 209
 210         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 211         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 212         if (!edid)
 213                 return -ENODEV;
 214
 215         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 216
 217         drm_connector_update_edid_property(connector, edid);
 218         ret = drm_add_edid_modes(connector, edid);
 219         kfree(edid);
 220
 221         if (vc4_hdmi->disable_4kp60) {
 222                 struct drm_device *drm = connector->dev;
 223                 struct drm_display_mode *mode;
 224
 225                 list_for_each_entry(mode, &connector->probed_modes, head) {
 226                         if (vc4_hdmi_mode_needs_scrambling(mode)) {
 227                                 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
 228                                 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
 229                         }
 230                 }
 231         }
 232
 233         return ret;
 234 }
 235
 236 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
 237                                            struct drm_atomic_state *state)
 238 {
 239         struct drm_connector_state *old_state =
 240                 drm_atomic_get_old_connector_state(state, connector);
 241         struct drm_connector_state *new_state =
 242                 drm_atomic_get_new_connector_state(state, connector);
 243         struct drm_crtc *crtc = new_state->crtc;
 244
 245         if (!crtc)
 246                 return 0;
 247
 248         if (old_state->colorspace != new_state->colorspace ||
 249             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
 250                 struct drm_crtc_state *crtc_state;
 251
 252                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
 253                 if (IS_ERR(crtc_state))
 254                         return PTR_ERR(crtc_state);
 255
 256                 crtc_state->mode_changed = true;
 257         }
 258
 259         return 0;
 260 }
 261
 262 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 263 {
 264         struct vc4_hdmi_connector_state *old_state =
 265                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 266         struct vc4_hdmi_connector_state *new_state =
 267                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 268
 269         if (connector->state)
 270                 __drm_atomic_helper_connector_destroy_state(connector->state);
 271
 272         kfree(old_state);
 273         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 274
 275         if (!new_state)
 276                 return;
 277
 278         new_state->base.max_bpc = 8;
 279         new_state->base.max_requested_bpc = 8;
 280         drm_atomic_helper_connector_tv_reset(connector);
 281 }
 282
 283 static struct drm_connector_state *
 284 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 285 {
 286         struct drm_connector_state *conn_state = connector->state;
 287         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 288         struct vc4_hdmi_connector_state *new_state;
 289
 290         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 291         if (!new_state)
 292                 return NULL;
 293
 294         new_state->pixel_rate = vc4_state->pixel_rate;
 295         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 296
 297         return &new_state->base;
 298 }
 299
 300 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 301         .detect = vc4_hdmi_connector_detect,
 302         .fill_modes = drm_helper_probe_single_connector_modes,
 303         .destroy = vc4_hdmi_connector_destroy,
 304         .reset = vc4_hdmi_connector_reset,
 305         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 306         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 307 };
 308
 309 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 310         .get_modes = vc4_hdmi_connector_get_modes,
 311         .atomic_check = vc4_hdmi_connector_atomic_check,
 312 };
 313
 314 static int vc4_hdmi_connector_init(struct drm_device *dev,
 315                                    struct vc4_hdmi *vc4_hdmi)
 316 {
 317         struct drm_connector *connector = &vc4_hdmi->connector;
 318         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 319         int ret;
 320
 321         drm_connector_init_with_ddc(dev, connector,
 322                                     &vc4_hdmi_connector_funcs,
 323                                     DRM_MODE_CONNECTOR_HDMIA,
 324                                     vc4_hdmi->ddc);
 325         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 326
 327         /*
 328          * Some of the properties below require access to state, like bpc.
 329          * Allocate some default initial connector state with our reset helper.
 330          */
 331         if (connector->funcs->reset)
 332                 connector->funcs->reset(connector);
 333
 334         /* Create and attach TV margin props to this connector. */
 335         ret = drm_mode_create_tv_margin_properties(dev);
 336         if (ret)
 337                 return ret;
 338
 339         ret = drm_mode_create_hdmi_colorspace_property(connector);
 340         if (ret)
 341                 return ret;
 342
 343         drm_connector_attach_colorspace_property(connector);
 344         drm_connector_attach_tv_margin_properties(connector);
 345         drm_connector_attach_max_bpc_property(connector, 8, 12);
 346
 347         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 348                              DRM_CONNECTOR_POLL_DISCONNECT);
 349
 350         connector->interlace_allowed = 1;
 351         connector->doublescan_allowed = 0;
 352
 353         if (vc4_hdmi->variant->supports_hdr)
 354                 drm_connector_attach_hdr_output_metadata_property(connector);
 355
 356         drm_connector_attach_encoder(connector, encoder);
 357
 358         return 0;
 359 }
 360
 361 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 362                                 enum hdmi_infoframe_type type,
 363                                 bool poll)
 364 {
 365         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 366         u32 packet_id = type - 0x80;
 367
 368         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 369                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 370
 371         if (!poll)
 372                 return 0;
 373
 374         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 375                           BIT(packet_id)), 100);
 376 }
 377
 378 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 379                                      union hdmi_infoframe *frame)
 380 {
 381         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 382         u32 packet_id = frame->any.type - 0x80;
 383         const struct vc4_hdmi_register *ram_packet_start =
 384                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 385         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 386         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 387                                                        ram_packet_start->reg);
 388         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 389         ssize_t len, i;
 390         int ret;
 391
 392         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 393                     VC4_HDMI_RAM_PACKET_ENABLE),
 394                   "Packet RAM has to be on to store the packet.");
 395
 396         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 397         if (len < 0)
 398                 return;
 399
 400         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 401         if (ret) {
 402                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 403                 return;
 404         }
 405
 406         for (i = 0; i < len; i += 7) {
 407                 writel(buffer[i + 0] << 0 |
 408                        buffer[i + 1] << 8 |
 409                        buffer[i + 2] << 16,
 410                        base + packet_reg);
 411                 packet_reg += 4;
 412
 413                 writel(buffer[i + 3] << 0 |
 414                        buffer[i + 4] << 8 |
 415                        buffer[i + 5] << 16 |
 416                        buffer[i + 6] << 24,
 417                        base + packet_reg);
 418                 packet_reg += 4;
 419         }
 420
 421         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 422                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 423         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 424                         BIT(packet_id)), 100);
 425         if (ret)
 426                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 427 }
 428
 429 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 430 {
 431         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 432         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 433         struct drm_connector *connector = &vc4_hdmi->connector;
 434         struct drm_connector_state *cstate = connector->state;
 435         struct drm_crtc *crtc = encoder->crtc;
 436         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 437         union hdmi_infoframe frame;
 438         int ret;
 439
 440         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 441                                                        connector, mode);
 442         if (ret < 0) {
 443                 DRM_ERROR("couldn't fill AVI infoframe\n");
 444                 return;
 445         }
 446
 447         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 448                                            connector, mode,
 449                                            vc4_encoder->limited_rgb_range ?
 450                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 451                                            HDMI_QUANTIZATION_RANGE_FULL);
 452         drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate);
 453         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 454
 455         vc4_hdmi_write_infoframe(encoder, &frame);
 456 }
 457
 458 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 459 {
 460         union hdmi_infoframe frame;
 461         int ret;
 462
 463         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 464         if (ret < 0) {
 465                 DRM_ERROR("couldn't fill SPD infoframe\n");
 466                 return;
 467         }
 468
 469         frame.spd.sdi = HDMI_SPD_SDI_PC;
 470
 471         vc4_hdmi_write_infoframe(encoder, &frame);
 472 }
 473
 474 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 475 {
 476         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 477         struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
 478         union hdmi_infoframe frame;
 479
 480         memcpy(&frame.audio, audio, sizeof(*audio));
 481         vc4_hdmi_write_infoframe(encoder, &frame);
 482 }
 483
 484 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
 485 {
 486         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 487         struct drm_connector *connector = &vc4_hdmi->connector;
 488         struct drm_connector_state *conn_state = connector->state;
 489         union hdmi_infoframe frame;
 490
 491         if (!vc4_hdmi->variant->supports_hdr)
 492                 return;
 493
 494         if (!conn_state->hdr_output_metadata)
 495                 return;
 496
 497         if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
 498                 return;
 499
 500         vc4_hdmi_write_infoframe(encoder, &frame);
 501 }
 502
 503 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 504 {
 505         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 506
 507         vc4_hdmi_set_avi_infoframe(encoder);
 508         vc4_hdmi_set_spd_infoframe(encoder);
 509         /*
 510          * If audio was streaming, then we need to reenabled the audio
 511          * infoframe here during encoder_enable.
 512          */
 513         if (vc4_hdmi->audio.streaming)
 514                 vc4_hdmi_set_audio_infoframe(encoder);
 515
 516         vc4_hdmi_set_hdr_infoframe(encoder);
 517 }
 518
 519 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
 520                                          struct drm_display_mode *mode)
 521 {
 522         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 523         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 524         struct drm_display_info *display = &vc4_hdmi->connector.display_info;
 525
 526         if (!vc4_encoder->hdmi_monitor)
 527                 return false;
 528
 529         if (!display->hdmi.scdc.supported ||
 530             !display->hdmi.scdc.scrambling.supported)
 531                 return false;
 532
 533         return true;
 534 }
 535
 536 #define SCRAMBLING_POLLING_DELAY_MS     1000
 537
 538 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
 539 {
 540         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 541         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 542
 543         if (!vc4_hdmi_supports_scrambling(encoder, mode))
 544                 return;
 545
 546         if (!vc4_hdmi_mode_needs_scrambling(mode))
 547                 return;
 548
 549         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 550         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 551
 552         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
 553                    VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 554
 555         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 556                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 557 }
 558
 559 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
 560 {
 561         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 562         struct drm_crtc *crtc = encoder->crtc;
 563
 564         /*
 565          * At boot, encoder->crtc will be NULL. Since we don't know the
 566          * state of the scrambler and in order to avoid any
 567          * inconsistency, let's disable it all the time.
 568          */
 569         if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
 570                 return;
 571
 572         if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
 573                 return;
 574
 575         if (delayed_work_pending(&vc4_hdmi->scrambling_work))
 576                 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
 577
 578         HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
 579                    ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
 580
 581         drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
 582         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
 583 }
 584
 585 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
 586 {
 587         struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
 588                                                  struct vc4_hdmi,
 589                                                  scrambling_work);
 590
 591         if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
 592                 return;
 593
 594         drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
 595         drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
 596
 597         queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
 598                            msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
 599 }
 600
 601 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 602                                                struct drm_atomic_state *state)
 603 {
 604         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 605
 606         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 607
 608         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
 609
 610         mdelay(1);
 611
 612         HDMI_WRITE(HDMI_VID_CTL,
 613                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 614         vc4_hdmi_disable_scrambling(encoder);
 615 }
 616
 617 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 618                                                  struct drm_atomic_state *state)
 619 {
 620         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 621         int ret;
 622
 623         HDMI_WRITE(HDMI_VID_CTL,
 624                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 625
 626         if (vc4_hdmi->variant->phy_disable)
 627                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 628
 629         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 630         clk_disable_unprepare(vc4_hdmi->hsm_clock);
 631         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 632
 633         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 634         if (ret < 0)
 635                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 636 }
 637
 638 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 639 {
 640 }
 641
 642 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 643 {
 644         u32 csc_ctl;
 645
 646         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 647                                 VC4_HD_CSC_CTL_ORDER);
 648
 649         if (enable) {
 650                 /* CEA VICs other than #1 requre limited range RGB
 651                  * output unless overridden by an AVI infoframe.
 652                  * Apply a colorspace conversion to squash 0-255 down
 653                  * to 16-235.  The matrix here is:
 654                  *
 655                  * [ 0      0      0.8594 16]
 656                  * [ 0      0.8594 0      16]
 657                  * [ 0.8594 0      0      16]
 658                  * [ 0      0      0       1]
 659                  */
 660                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 661                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 662                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 663                                          VC4_HD_CSC_CTL_MODE);
 664
 665                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 666                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 667                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 668                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 669                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 670                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 671         }
 672
 673         /* The RGB order applies even when CSC is disabled. */
 674         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 675 }
 676
 677 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 678 {
 679         u32 csc_ctl;
 680
 681         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 682
 683         if (enable) {
 684                 /* CEA VICs other than #1 requre limited range RGB
 685                  * output unless overridden by an AVI infoframe.
 686                  * Apply a colorspace conversion to squash 0-255 down
 687                  * to 16-235.  The matrix here is:
 688                  *
 689                  * [ 0.8594 0      0      16]
 690                  * [ 0      0.8594 0      16]
 691                  * [ 0      0      0.8594 16]
 692                  * [ 0      0      0       1]
 693                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 694                  */
 695                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 696                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 697                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 698                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 699                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 700                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 701         } else {
 702                 /* Still use the matrix for full range, but make it unity.
 703                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 704                  */
 705                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 706                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 707                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 708                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 709                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 710                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 711         }
 712
 713         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 714 }
 715
 716 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 717                                  struct drm_connector_state *state,
 718                                  struct drm_display_mode *mode)
 719 {
 720         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 721         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 722         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 723         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 724         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 725                                    VC4_HDMI_VERTA_VSP) |
 726                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 727                                    VC4_HDMI_VERTA_VFP) |
 728                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 729         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 730                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 731                                    VC4_HDMI_VERTB_VBP));
 732         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 733                           VC4_SET_FIELD(mode->crtc_vtotal -
 734                                         mode->crtc_vsync_end -
 735                                         interlaced,
 736                                         VC4_HDMI_VERTB_VBP));
 737
 738         HDMI_WRITE(HDMI_HORZA,
 739                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 740                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 741                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 742                                  VC4_HDMI_HORZA_HAP));
 743
 744         HDMI_WRITE(HDMI_HORZB,
 745                    VC4_SET_FIELD((mode->htotal -
 746                                   mode->hsync_end) * pixel_rep,
 747                                  VC4_HDMI_HORZB_HBP) |
 748                    VC4_SET_FIELD((mode->hsync_end -
 749                                   mode->hsync_start) * pixel_rep,
 750                                  VC4_HDMI_HORZB_HSP) |
 751                    VC4_SET_FIELD((mode->hsync_start -
 752                                   mode->hdisplay) * pixel_rep,
 753                                  VC4_HDMI_HORZB_HFP));
 754
 755         HDMI_WRITE(HDMI_VERTA0, verta);
 756         HDMI_WRITE(HDMI_VERTA1, verta);
 757
 758         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 759         HDMI_WRITE(HDMI_VERTB1, vertb);
 760 }
 761
 762 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 763                                  struct drm_connector_state *state,
 764                                  struct drm_display_mode *mode)
 765 {
 766         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 767         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 768         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 769         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 770         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 771                                    VC5_HDMI_VERTA_VSP) |
 772                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 773                                    VC5_HDMI_VERTA_VFP) |
 774                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 775         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 776                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 777                                    VC4_HDMI_VERTB_VBP));
 778         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 779                           VC4_SET_FIELD(mode->crtc_vtotal -
 780                                         mode->crtc_vsync_end -
 781                                         interlaced,
 782                                         VC4_HDMI_VERTB_VBP));
 783         unsigned char gcp;
 784         bool gcp_en;
 785         u32 reg;
 786
 787         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 788         HDMI_WRITE(HDMI_HORZA,
 789                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 790                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 791                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 792                                  VC5_HDMI_HORZA_HAP) |
 793                    VC4_SET_FIELD((mode->hsync_start -
 794                                   mode->hdisplay) * pixel_rep,
 795                                  VC5_HDMI_HORZA_HFP));
 796
 797         HDMI_WRITE(HDMI_HORZB,
 798                    VC4_SET_FIELD((mode->htotal -
 799                                   mode->hsync_end) * pixel_rep,
 800                                  VC5_HDMI_HORZB_HBP) |
 801                    VC4_SET_FIELD((mode->hsync_end -
 802                                   mode->hsync_start) * pixel_rep,
 803                                  VC5_HDMI_HORZB_HSP));
 804
 805         HDMI_WRITE(HDMI_VERTA0, verta);
 806         HDMI_WRITE(HDMI_VERTA1, verta);
 807
 808         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 809         HDMI_WRITE(HDMI_VERTB1, vertb);
 810
 811         switch (state->max_bpc) {
 812         case 12:
 813                 gcp = 6;
 814                 gcp_en = true;
 815                 break;
 816         case 10:
 817                 gcp = 5;
 818                 gcp_en = true;
 819                 break;
 820         case 8:
 821         default:
 822                 gcp = 4;
 823                 gcp_en = false;
 824                 break;
 825         }
 826
 827         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 828         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 829                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 830         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 831                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 832         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 833
 834         reg = HDMI_READ(HDMI_GCP_WORD_1);
 835         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 836         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 837         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 838
 839         reg = HDMI_READ(HDMI_GCP_CONFIG);
 840         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 841         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 842         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 843
 844         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 845 }
 846
 847 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 848 {
 849         u32 drift;
 850         int ret;
 851
 852         drift = HDMI_READ(HDMI_FIFO_CTL);
 853         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 854
 855         HDMI_WRITE(HDMI_FIFO_CTL,
 856                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 857         HDMI_WRITE(HDMI_FIFO_CTL,
 858                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 859         usleep_range(1000, 1100);
 860         HDMI_WRITE(HDMI_FIFO_CTL,
 861                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 862         HDMI_WRITE(HDMI_FIFO_CTL,
 863                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 864
 865         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 866                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 867         WARN_ONCE(ret, "Timeout waiting for "
 868                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 869 }
 870
 871 static struct drm_connector_state *
 872 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 873                                      struct drm_atomic_state *state)
 874 {
 875         struct drm_connector_state *conn_state;
 876         struct drm_connector *connector;
 877         unsigned int i;
 878
 879         for_each_new_connector_in_state(state, connector, conn_state, i) {
 880                 if (conn_state->best_encoder == encoder)
 881                         return conn_state;
 882         }
 883
 884         return NULL;
 885 }
 886
 887 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 888                                                 struct drm_atomic_state *state)
 889 {
 890         struct drm_connector_state *conn_state =
 891                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 892         struct vc4_hdmi_connector_state *vc4_conn_state =
 893                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 894         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 895         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 896         unsigned long bvb_rate, pixel_rate, hsm_rate;
 897         int ret;
 898
 899         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 900         if (ret < 0) {
 901                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 902                 return;
 903         }
 904
 905         pixel_rate = vc4_conn_state->pixel_rate;
 906         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 907         if (ret) {
 908                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 909                 return;
 910         }
 911
 912         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 913         if (ret) {
 914                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 915                 return;
 916         }
 917
 918         /*
 919          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 920          * be faster than pixel clock, infinitesimally faster, tested in
 921          * simulation. Otherwise, exact value is unimportant for HDMI
 922          * operation." This conflicts with bcm2835's vc4 documentation, which
 923          * states HSM's clock has to be at least 108% of the pixel clock.
 924          *
 925          * Real life tests reveal that vc4's firmware statement holds up, and
 926          * users are able to use pixel clocks closer to HSM's, namely for
 927          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 928          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 929          * 162MHz.
 930          *
 931          * Additionally, the AXI clock needs to be at least 25% of
 932          * pixel clock, but HSM ends up being the limiting factor.
 933          */
 934         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 935         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 936         if (ret) {
 937                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 938                 return;
 939         }
 940
 941         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
 942         if (ret) {
 943                 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
 944                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 945                 return;
 946         }
 947
 948         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 949
 950         if (pixel_rate > 297000000)
 951                 bvb_rate = 300000000;
 952         else if (pixel_rate > 148500000)
 953                 bvb_rate = 150000000;
 954         else
 955                 bvb_rate = 75000000;
 956
 957         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
 958         if (ret) {
 959                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 960                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 961                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 962                 return;
 963         }
 964
 965         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 966         if (ret) {
 967                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 968                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 969                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 970                 return;
 971         }
 972
 973         if (vc4_hdmi->variant->phy_init)
 974                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 975
 976         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 977                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 978                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 979                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 980
 981         if (vc4_hdmi->variant->set_timings)
 982                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 983 }
 984
 985 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 986                                              struct drm_atomic_state *state)
 987 {
 988         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 989         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 990         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 991
 992         if (vc4_encoder->hdmi_monitor &&
 993             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 994                 if (vc4_hdmi->variant->csc_setup)
 995                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 996
 997                 vc4_encoder->limited_rgb_range = true;
 998         } else {
 999                 if (vc4_hdmi->variant->csc_setup)
1000                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
1001
1002                 vc4_encoder->limited_rgb_range = false;
1003         }
1004
1005         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1006 }
1007
1008 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1009                                               struct drm_atomic_state *state)
1010 {
1011         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1012         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1013         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
1014         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1015         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1016         int ret;
1017
1018         HDMI_WRITE(HDMI_VID_CTL,
1019                    VC4_HD_VID_CTL_ENABLE |
1020                    VC4_HD_VID_CTL_CLRRGB |
1021                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1022                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1023                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1024                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1025
1026         HDMI_WRITE(HDMI_VID_CTL,
1027                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1028
1029         if (vc4_encoder->hdmi_monitor) {
1030                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1031                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1032                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1033
1034                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1035                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1036                 WARN_ONCE(ret, "Timeout waiting for "
1037                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1038         } else {
1039                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1040                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1041                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
1042                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1043                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1044                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1045
1046                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1047                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1048                 WARN_ONCE(ret, "Timeout waiting for "
1049                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1050         }
1051
1052         if (vc4_encoder->hdmi_monitor) {
1053                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1054                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1055                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1056                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1057                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
1058
1059                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1060                            VC4_HDMI_RAM_PACKET_ENABLE);
1061
1062                 vc4_hdmi_set_infoframes(encoder);
1063         }
1064
1065         vc4_hdmi_recenter_fifo(vc4_hdmi);
1066         vc4_hdmi_enable_scrambling(encoder);
1067 }
1068
1069 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
1070 {
1071 }
1072
1073 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
1074 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
1075
1076 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1077                                          struct drm_crtc_state *crtc_state,
1078                                          struct drm_connector_state *conn_state)
1079 {
1080         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1081         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1082         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1083         unsigned long long pixel_rate = mode->clock * 1000;
1084         unsigned long long tmds_rate;
1085
1086         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1087             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1088              (mode->hsync_end % 2) || (mode->htotal % 2)))
1089                 return -EINVAL;
1090
1091         /*
1092          * The 1440p@60 pixel rate is in the same range than the first
1093          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1094          * bandwidth). Slightly lower the frequency to bring it out of
1095          * the WiFi range.
1096          */
1097         tmds_rate = pixel_rate * 10;
1098         if (vc4_hdmi->disable_wifi_frequencies &&
1099             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1100              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1101                 mode->clock = 238560;
1102                 pixel_rate = mode->clock * 1000;
1103         }
1104
1105         if (conn_state->max_bpc == 12) {
1106                 pixel_rate = pixel_rate * 150;
1107                 do_div(pixel_rate, 100);
1108         } else if (conn_state->max_bpc == 10) {
1109                 pixel_rate = pixel_rate * 125;
1110                 do_div(pixel_rate, 100);
1111         }
1112
1113         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1114                 pixel_rate = pixel_rate * 2;
1115
1116         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
1117                 return -EINVAL;
1118
1119         if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK))
1120                 return -EINVAL;
1121
1122         vc4_state->pixel_rate = pixel_rate;
1123
1124         return 0;
1125 }
1126
1127 static enum drm_mode_status
1128 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1129                             const struct drm_display_mode *mode)
1130 {
1131         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1132
1133         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1134             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1135              (mode->hsync_end % 2) || (mode->htotal % 2)))
1136                 return MODE_H_ILLEGAL;
1137
1138         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
1139                 return MODE_CLOCK_HIGH;
1140
1141         if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode))
1142                 return MODE_CLOCK_HIGH;
1143
1144         return MODE_OK;
1145 }
1146
1147 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1148         .atomic_check = vc4_hdmi_encoder_atomic_check,
1149         .mode_valid = vc4_hdmi_encoder_mode_valid,
1150         .disable = vc4_hdmi_encoder_disable,
1151         .enable = vc4_hdmi_encoder_enable,
1152 };
1153
1154 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1155 {
1156         int i;
1157         u32 channel_map = 0;
1158
1159         for (i = 0; i < 8; i++) {
1160                 if (channel_mask & BIT(i))
1161                         channel_map |= i << (3 * i);
1162         }
1163         return channel_map;
1164 }
1165
1166 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1167 {
1168         int i;
1169         u32 channel_map = 0;
1170
1171         for (i = 0; i < 8; i++) {
1172                 if (channel_mask & BIT(i))
1173                         channel_map |= i << (4 * i);
1174         }
1175         return channel_map;
1176 }
1177
1178 /* HDMI audio codec callbacks */
1179 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1180                                          unsigned int samplerate)
1181 {
1182         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1183         unsigned long n, m;
1184
1185         rational_best_approximation(hsm_clock, samplerate,
1186                                     VC4_HD_MAI_SMP_N_MASK >>
1187                                     VC4_HD_MAI_SMP_N_SHIFT,
1188                                     (VC4_HD_MAI_SMP_M_MASK >>
1189                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1190                                     &n, &m);
1191
1192         HDMI_WRITE(HDMI_MAI_SMP,
1193                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1194                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1195 }
1196
1197 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1198 {
1199         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1200         struct drm_crtc *crtc = encoder->crtc;
1201         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1202         u32 n, cts;
1203         u64 tmp;
1204
1205         n = 128 * samplerate / 1000;
1206         tmp = (u64)(mode->clock * 1000) * n;
1207         do_div(tmp, 128 * samplerate);
1208         cts = tmp;
1209
1210         HDMI_WRITE(HDMI_CRP_CFG,
1211                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1212                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1213
1214         /*
1215          * We could get slightly more accurate clocks in some cases by
1216          * providing a CTS_1 value.  The two CTS values are alternated
1217          * between based on the period fields
1218          */
1219         HDMI_WRITE(HDMI_CTS_0, cts);
1220         HDMI_WRITE(HDMI_CTS_1, cts);
1221 }
1222
1223 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1224 {
1225         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1226
1227         return snd_soc_card_get_drvdata(card);
1228 }
1229
1230 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1231 {
1232         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1233         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1234
1235         /*
1236          * If the HDMI encoder hasn't probed, or the encoder is
1237          * currently in DVI mode, treat the codec dai as missing.
1238          */
1239         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1240                                 VC4_HDMI_RAM_PACKET_ENABLE))
1241                 return -ENODEV;
1242
1243         vc4_hdmi->audio.streaming = true;
1244
1245         HDMI_WRITE(HDMI_MAI_CTL,
1246                    VC4_HD_MAI_CTL_RESET |
1247                    VC4_HD_MAI_CTL_FLUSH |
1248                    VC4_HD_MAI_CTL_DLATE |
1249                    VC4_HD_MAI_CTL_ERRORE |
1250                    VC4_HD_MAI_CTL_ERRORF);
1251
1252         if (vc4_hdmi->variant->phy_rng_enable)
1253                 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1254
1255         return 0;
1256 }
1257
1258 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1259 {
1260         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1261         struct device *dev = &vc4_hdmi->pdev->dev;
1262         int ret;
1263
1264         vc4_hdmi->audio.streaming = false;
1265         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1266         if (ret)
1267                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1268
1269         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1270         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1271         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1272 }
1273
1274 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
1275 {
1276         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1277
1278         HDMI_WRITE(HDMI_MAI_CTL,
1279                    VC4_HD_MAI_CTL_DLATE |
1280                    VC4_HD_MAI_CTL_ERRORE |
1281                    VC4_HD_MAI_CTL_ERRORF);
1282
1283         if (vc4_hdmi->variant->phy_rng_disable)
1284                 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1285
1286         vc4_hdmi->audio.streaming = false;
1287         vc4_hdmi_audio_reset(vc4_hdmi);
1288 }
1289
1290 static int sample_rate_to_mai_fmt(int samplerate)
1291 {
1292         switch (samplerate) {
1293         case 8000:
1294                 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
1295         case 11025:
1296                 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
1297         case 12000:
1298                 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
1299         case 16000:
1300                 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
1301         case 22050:
1302                 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
1303         case 24000:
1304                 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
1305         case 32000:
1306                 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
1307         case 44100:
1308                 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
1309         case 48000:
1310                 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
1311         case 64000:
1312                 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
1313         case 88200:
1314                 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
1315         case 96000:
1316                 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
1317         case 128000:
1318                 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
1319         case 176400:
1320                 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
1321         case 192000:
1322                 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
1323         default:
1324                 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
1325         }
1326 }
1327
1328 /* HDMI audio codec callbacks */
1329 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
1330                                   struct hdmi_codec_daifmt *daifmt,
1331                                   struct hdmi_codec_params *params)
1332 {
1333         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1334         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1335         unsigned int sample_rate = params->sample_rate;
1336         unsigned int channels = params->channels;
1337         u32 audio_packet_config, channel_mask;
1338         u32 channel_map;
1339         u32 mai_audio_format;
1340         u32 mai_sample_rate;
1341
1342         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1343                 sample_rate, params->sample_width, channels);
1344
1345         HDMI_WRITE(HDMI_MAI_CTL,
1346                    VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
1347                    VC4_HD_MAI_CTL_WHOLSMP |
1348                    VC4_HD_MAI_CTL_CHALIGN |
1349                    VC4_HD_MAI_CTL_ENABLE);
1350
1351         vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
1352
1353         mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
1354         if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
1355             params->channels == 8)
1356                 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
1357         else
1358                 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
1359         HDMI_WRITE(HDMI_MAI_FMT,
1360                    VC4_SET_FIELD(mai_sample_rate,
1361                                  VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
1362                    VC4_SET_FIELD(mai_audio_format,
1363                                  VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
1364
1365         /* The B frame identifier should match the value used by alsa-lib (8) */
1366         audio_packet_config =
1367                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1368                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1369                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1370
1371         channel_mask = GENMASK(channels - 1, 0);
1372         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1373                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1374
1375         /* Set the MAI threshold */
1376         HDMI_WRITE(HDMI_MAI_THR,
1377                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1378                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1379                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1380                    VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1381
1382         HDMI_WRITE(HDMI_MAI_CONFIG,
1383                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1384                    VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
1385                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1386
1387         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1388         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1389         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1390         vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
1391
1392         memcpy(&vc4_hdmi->audio.infoframe, &params->cea, sizeof(params->cea));
1393         vc4_hdmi_set_audio_infoframe(encoder);
1394
1395         return 0;
1396 }
1397
1398 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1399         .name = "vc4-hdmi-cpu-dai-component",
1400 };
1401
1402 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1403 {
1404         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1405
1406         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1407
1408         return 0;
1409 }
1410
1411 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1412         .name = "vc4-hdmi-cpu-dai",
1413         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1414         .playback = {
1415                 .stream_name = "Playback",
1416                 .channels_min = 1,
1417                 .channels_max = 8,
1418                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1419                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1420                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1421                          SNDRV_PCM_RATE_192000,
1422                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1423         },
1424 };
1425
1426 static const struct snd_dmaengine_pcm_config pcm_conf = {
1427         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1428         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1429 };
1430
1431 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
1432                                   uint8_t *buf, size_t len)
1433 {
1434         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1435         struct drm_connector *connector = &vc4_hdmi->connector;
1436
1437         memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1438
1439         return 0;
1440 }
1441
1442 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
1443         .get_eld = vc4_hdmi_audio_get_eld,
1444         .prepare = vc4_hdmi_audio_prepare,
1445         .audio_shutdown = vc4_hdmi_audio_shutdown,
1446         .audio_startup = vc4_hdmi_audio_startup,
1447 };
1448
1449 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
1450         .ops = &vc4_hdmi_codec_ops,
1451         .max_i2s_channels = 8,
1452         .i2s = 1,
1453 };
1454
1455 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1456 {
1457         const struct vc4_hdmi_register *mai_data =
1458                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1459         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1460         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1461         struct device *dev = &vc4_hdmi->pdev->dev;
1462         struct platform_device *codec_pdev;
1463         const __be32 *addr;
1464         int index;
1465         int ret;
1466
1467         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1468                 dev_warn(dev,
1469                          "'dmas' DT property is missing, no HDMI audio\n");
1470                 return 0;
1471         }
1472
1473         if (mai_data->reg != VC4_HD) {
1474                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1475                 return -EINVAL;
1476         }
1477
1478         /*
1479          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1480          * the bus address specified in the DT, because the physical address
1481          * (the one returned by platform_get_resource()) is not appropriate
1482          * for DMA transfers.
1483          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1484          */
1485         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1486         /* Before BCM2711, we don't have a named register range */
1487         if (index < 0)
1488                 index = 1;
1489
1490         addr = of_get_address(dev->of_node, index, NULL, NULL);
1491
1492         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1493         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1494         vc4_hdmi->audio.dma_data.maxburst = 2;
1495
1496         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1497         if (ret) {
1498                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1499                 return ret;
1500         }
1501
1502         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1503                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1504         if (ret) {
1505                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1506                 return ret;
1507         }
1508
1509         codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1510                                                    PLATFORM_DEVID_AUTO,
1511                                                    &vc4_hdmi_codec_pdata,
1512                                                    sizeof(vc4_hdmi_codec_pdata));
1513         if (IS_ERR(codec_pdev)) {
1514                 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
1515                 return PTR_ERR(codec_pdev);
1516         }
1517
1518         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1519         dai_link->codecs        = &vc4_hdmi->audio.codec;
1520         dai_link->platforms     = &vc4_hdmi->audio.platform;
1521
1522         dai_link->num_cpus      = 1;
1523         dai_link->num_codecs    = 1;
1524         dai_link->num_platforms = 1;
1525
1526         dai_link->name = "MAI";
1527         dai_link->stream_name = "MAI PCM";
1528         dai_link->codecs->dai_name = "i2s-hifi";
1529         dai_link->cpus->dai_name = dev_name(dev);
1530         dai_link->codecs->name = dev_name(&codec_pdev->dev);
1531         dai_link->platforms->name = dev_name(dev);
1532
1533         card->dai_link = dai_link;
1534         card->num_links = 1;
1535         card->name = vc4_hdmi->variant->card_name;
1536         card->driver_name = "vc4-hdmi";
1537         card->dev = dev;
1538         card->owner = THIS_MODULE;
1539
1540         /*
1541          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1542          * stores a pointer to the snd card object in dev->driver_data. This
1543          * means we cannot use it for something else. The hdmi back-pointer is
1544          * now stored in card->drvdata and should be retrieved with
1545          * snd_soc_card_get_drvdata() if needed.
1546          */
1547         snd_soc_card_set_drvdata(card, vc4_hdmi);
1548         ret = devm_snd_soc_register_card(dev, card);
1549         if (ret)
1550                 dev_err_probe(dev, ret, "Could not register sound card\n");
1551
1552         return ret;
1553
1554 }
1555
1556 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
1557 {
1558         struct vc4_hdmi *vc4_hdmi = priv;
1559         struct drm_connector *connector = &vc4_hdmi->connector;
1560         struct drm_device *dev = connector->dev;
1561
1562         if (dev && dev->registered)
1563                 drm_connector_helper_hpd_irq_event(connector);
1564
1565         return IRQ_HANDLED;
1566 }
1567
1568 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
1569 {
1570         struct drm_connector *connector = &vc4_hdmi->connector;
1571         struct platform_device *pdev = vc4_hdmi->pdev;
1572         int ret;
1573
1574         if (vc4_hdmi->variant->external_irq_controller) {
1575                 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
1576                 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
1577
1578                 ret = request_threaded_irq(hpd_con,
1579                                            NULL,
1580                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1581                                            "vc4 hdmi hpd connected", vc4_hdmi);
1582                 if (ret)
1583                         return ret;
1584
1585                 ret = request_threaded_irq(hpd_rm,
1586                                            NULL,
1587                                            vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
1588                                            "vc4 hdmi hpd disconnected", vc4_hdmi);
1589                 if (ret) {
1590                         free_irq(hpd_con, vc4_hdmi);
1591                         return ret;
1592                 }
1593
1594                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1595         }
1596
1597         return 0;
1598 }
1599
1600 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi)
1601 {
1602         struct platform_device *pdev = vc4_hdmi->pdev;
1603
1604         if (vc4_hdmi->variant->external_irq_controller) {
1605                 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi);
1606                 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi);
1607         }
1608 }
1609
1610 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1611 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1612 {
1613         struct vc4_hdmi *vc4_hdmi = priv;
1614
1615         if (vc4_hdmi->cec_rx_msg.len)
1616                 cec_received_msg(vc4_hdmi->cec_adap,
1617                                  &vc4_hdmi->cec_rx_msg);
1618
1619         return IRQ_HANDLED;
1620 }
1621
1622 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1623 {
1624         struct vc4_hdmi *vc4_hdmi = priv;
1625
1626         if (vc4_hdmi->cec_tx_ok) {
1627                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1628                                   0, 0, 0, 0);
1629         } else {
1630                 /*
1631                  * This CEC implementation makes 1 retry, so if we
1632                  * get a NACK, then that means it made 2 attempts.
1633                  */
1634                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1635                                   0, 2, 0, 0);
1636         }
1637         return IRQ_HANDLED;
1638 }
1639
1640 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1641 {
1642         struct vc4_hdmi *vc4_hdmi = priv;
1643         irqreturn_t ret;
1644
1645         if (vc4_hdmi->cec_irq_was_rx)
1646                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1647         else
1648                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1649
1650         return ret;
1651 }
1652
1653 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1654 {
1655         struct drm_device *dev = vc4_hdmi->connector.dev;
1656         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1657         unsigned int i;
1658
1659         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1660                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1661
1662         if (msg->len > 16) {
1663                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1664                 return;
1665         }
1666
1667         for (i = 0; i < msg->len; i += 4) {
1668                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1669
1670                 msg->msg[i] = val & 0xff;
1671                 msg->msg[i + 1] = (val >> 8) & 0xff;
1672                 msg->msg[i + 2] = (val >> 16) & 0xff;
1673                 msg->msg[i + 3] = (val >> 24) & 0xff;
1674         }
1675 }
1676
1677 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1678 {
1679         struct vc4_hdmi *vc4_hdmi = priv;
1680         u32 cntrl1;
1681
1682         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1683         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1684         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1685         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1686
1687         return IRQ_WAKE_THREAD;
1688 }
1689
1690 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1691 {
1692         struct vc4_hdmi *vc4_hdmi = priv;
1693         u32 cntrl1;
1694
1695         vc4_hdmi->cec_rx_msg.len = 0;
1696         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1697         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1698         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1699         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1700         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1701
1702         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1703
1704         return IRQ_WAKE_THREAD;
1705 }
1706
1707 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1708 {
1709         struct vc4_hdmi *vc4_hdmi = priv;
1710         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1711         irqreturn_t ret;
1712         u32 cntrl5;
1713
1714         if (!(stat & VC4_HDMI_CPU_CEC))
1715                 return IRQ_NONE;
1716
1717         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1718         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1719         if (vc4_hdmi->cec_irq_was_rx)
1720                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1721         else
1722                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1723
1724         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1725         return ret;
1726 }
1727
1728 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1729 {
1730         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1731         /* clock period in microseconds */
1732         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1733         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1734
1735         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1736                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1737                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1738         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1739                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1740
1741         if (enable) {
1742                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1743                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1744                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1745                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1746                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1747                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1748                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1749                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1750                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1751                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1752                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1753                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1754                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1755                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1756                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1757                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1758                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1759                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1760                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1761
1762                 if (!vc4_hdmi->variant->external_irq_controller)
1763                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1764         } else {
1765                 if (!vc4_hdmi->variant->external_irq_controller)
1766                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1767                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1768                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1769         }
1770         return 0;
1771 }
1772
1773 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1774 {
1775         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1776
1777         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1778                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1779                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1780         return 0;
1781 }
1782
1783 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1784                                       u32 signal_free_time, struct cec_msg *msg)
1785 {
1786         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1787         struct drm_device *dev = vc4_hdmi->connector.dev;
1788         u32 val;
1789         unsigned int i;
1790
1791         if (msg->len > 16) {
1792                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1793                 return -ENOMEM;
1794         }
1795
1796         for (i = 0; i < msg->len; i += 4)
1797                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1798                            (msg->msg[i]) |
1799                            (msg->msg[i + 1] << 8) |
1800                            (msg->msg[i + 2] << 16) |
1801                            (msg->msg[i + 3] << 24));
1802
1803         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1804         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1805         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1806         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1807         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1808         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1809
1810         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1811         return 0;
1812 }
1813
1814 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1815         .adap_enable = vc4_hdmi_cec_adap_enable,
1816         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1817         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1818 };
1819
1820 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1821 {
1822         struct cec_connector_info conn_info;
1823         struct platform_device *pdev = vc4_hdmi->pdev;
1824         struct device *dev = &pdev->dev;
1825         u32 value;
1826         int ret;
1827
1828         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1829                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1830                 return 0;
1831         }
1832
1833         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1834                                                   vc4_hdmi, "vc4",
1835                                                   CEC_CAP_DEFAULTS |
1836                                                   CEC_CAP_CONNECTOR_INFO, 1);
1837         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1838         if (ret < 0)
1839                 return ret;
1840
1841         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1842         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1843
1844         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1845         /* Set the logical address to Unregistered */
1846         value |= VC4_HDMI_CEC_ADDR_MASK;
1847         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1848
1849         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1850
1851         if (vc4_hdmi->variant->external_irq_controller) {
1852                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"),
1853                                            vc4_cec_irq_handler_rx_bare,
1854                                            vc4_cec_irq_handler_rx_thread, 0,
1855                                            "vc4 hdmi cec rx", vc4_hdmi);
1856                 if (ret)
1857                         goto err_delete_cec_adap;
1858
1859                 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"),
1860                                            vc4_cec_irq_handler_tx_bare,
1861                                            vc4_cec_irq_handler_tx_thread, 0,
1862                                            "vc4 hdmi cec tx", vc4_hdmi);
1863                 if (ret)
1864                         goto err_remove_cec_rx_handler;
1865         } else {
1866                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1867
1868                 ret = request_threaded_irq(platform_get_irq(pdev, 0),
1869                                            vc4_cec_irq_handler,
1870                                            vc4_cec_irq_handler_thread, 0,
1871                                            "vc4 hdmi cec", vc4_hdmi);
1872                 if (ret)
1873                         goto err_delete_cec_adap;
1874         }
1875
1876         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1877         if (ret < 0)
1878                 goto err_remove_handlers;
1879
1880         return 0;
1881
1882 err_remove_handlers:
1883         if (vc4_hdmi->variant->external_irq_controller)
1884                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1885         else
1886                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1887
1888 err_remove_cec_rx_handler:
1889         if (vc4_hdmi->variant->external_irq_controller)
1890                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1891
1892 err_delete_cec_adap:
1893         cec_delete_adapter(vc4_hdmi->cec_adap);
1894
1895         return ret;
1896 }
1897
1898 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1899 {
1900         struct platform_device *pdev = vc4_hdmi->pdev;
1901
1902         if (vc4_hdmi->variant->external_irq_controller) {
1903                 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi);
1904                 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi);
1905         } else {
1906                 free_irq(platform_get_irq(pdev, 0), vc4_hdmi);
1907         }
1908
1909         cec_unregister_adapter(vc4_hdmi->cec_adap);
1910 }
1911 #else
1912 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1913 {
1914         return 0;
1915 }
1916
1917 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1918
1919 #endif
1920
1921 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1922                                  struct debugfs_regset32 *regset,
1923                                  enum vc4_hdmi_regs reg)
1924 {
1925         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1926         struct debugfs_reg32 *regs, *new_regs;
1927         unsigned int count = 0;
1928         unsigned int i;
1929
1930         regs = kcalloc(variant->num_registers, sizeof(*regs),
1931                        GFP_KERNEL);
1932         if (!regs)
1933                 return -ENOMEM;
1934
1935         for (i = 0; i < variant->num_registers; i++) {
1936                 const struct vc4_hdmi_register *field = &variant->registers[i];
1937
1938                 if (field->reg != reg)
1939                         continue;
1940
1941                 regs[count].name = field->name;
1942                 regs[count].offset = field->offset;
1943                 count++;
1944         }
1945
1946         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1947         if (!new_regs)
1948                 return -ENOMEM;
1949
1950         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1951         regset->regs = new_regs;
1952         regset->nregs = count;
1953
1954         return 0;
1955 }
1956
1957 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1958 {
1959         struct platform_device *pdev = vc4_hdmi->pdev;
1960         struct device *dev = &pdev->dev;
1961         int ret;
1962
1963         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1964         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1965                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1966
1967         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1968         if (IS_ERR(vc4_hdmi->hd_regs))
1969                 return PTR_ERR(vc4_hdmi->hd_regs);
1970
1971         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1972         if (ret)
1973                 return ret;
1974
1975         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1976         if (ret)
1977                 return ret;
1978
1979         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1980         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1981                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1982                 if (ret != -EPROBE_DEFER)
1983                         DRM_ERROR("Failed to get pixel clock\n");
1984                 return ret;
1985         }
1986
1987         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1988         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1989                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1990                 return PTR_ERR(vc4_hdmi->hsm_clock);
1991         }
1992         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1993         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
1994
1995         return 0;
1996 }
1997
1998 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1999 {
2000         struct platform_device *pdev = vc4_hdmi->pdev;
2001         struct device *dev = &pdev->dev;
2002         struct resource *res;
2003
2004         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
2005         if (!res)
2006                 return -ENODEV;
2007
2008         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
2009                                                resource_size(res));
2010         if (!vc4_hdmi->hdmicore_regs)
2011                 return -ENOMEM;
2012
2013         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
2014         if (!res)
2015                 return -ENODEV;
2016
2017         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
2018         if (!vc4_hdmi->hd_regs)
2019                 return -ENOMEM;
2020
2021         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
2022         if (!res)
2023                 return -ENODEV;
2024
2025         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
2026         if (!vc4_hdmi->cec_regs)
2027                 return -ENOMEM;
2028
2029         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
2030         if (!res)
2031                 return -ENODEV;
2032
2033         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
2034         if (!vc4_hdmi->csc_regs)
2035                 return -ENOMEM;
2036
2037         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
2038         if (!res)
2039                 return -ENODEV;
2040
2041         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
2042         if (!vc4_hdmi->dvp_regs)
2043                 return -ENOMEM;
2044
2045         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
2046         if (!res)
2047                 return -ENODEV;
2048
2049         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
2050         if (!vc4_hdmi->phy_regs)
2051                 return -ENOMEM;
2052
2053         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
2054         if (!res)
2055                 return -ENODEV;
2056
2057         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
2058         if (!vc4_hdmi->ram_regs)
2059                 return -ENOMEM;
2060
2061         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
2062         if (!res)
2063                 return -ENODEV;
2064
2065         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
2066         if (!vc4_hdmi->rm_regs)
2067                 return -ENOMEM;
2068
2069         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
2070         if (IS_ERR(vc4_hdmi->hsm_clock)) {
2071                 DRM_ERROR("Failed to get HDMI state machine clock\n");
2072                 return PTR_ERR(vc4_hdmi->hsm_clock);
2073         }
2074
2075         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
2076         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
2077                 DRM_ERROR("Failed to get pixel bvb clock\n");
2078                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
2079         }
2080
2081         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
2082         if (IS_ERR(vc4_hdmi->audio_clock)) {
2083                 DRM_ERROR("Failed to get audio clock\n");
2084                 return PTR_ERR(vc4_hdmi->audio_clock);
2085         }
2086
2087         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
2088         if (IS_ERR(vc4_hdmi->cec_clock)) {
2089                 DRM_ERROR("Failed to get CEC clock\n");
2090                 return PTR_ERR(vc4_hdmi->cec_clock);
2091         }
2092
2093         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
2094         if (IS_ERR(vc4_hdmi->reset)) {
2095                 DRM_ERROR("Failed to get HDMI reset line\n");
2096                 return PTR_ERR(vc4_hdmi->reset);
2097         }
2098
2099         return 0;
2100 }
2101
2102 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
2103 {
2104         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
2105         struct platform_device *pdev = to_platform_device(dev);
2106         struct drm_device *drm = dev_get_drvdata(master);
2107         struct vc4_hdmi *vc4_hdmi;
2108         struct drm_encoder *encoder;
2109         struct device_node *ddc_node;
2110         int ret;
2111
2112         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
2113         if (!vc4_hdmi)
2114                 return -ENOMEM;
2115         INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
2116
2117         dev_set_drvdata(dev, vc4_hdmi);
2118         encoder = &vc4_hdmi->encoder.base.base;
2119         vc4_hdmi->encoder.base.type = variant->encoder_type;
2120         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
2121         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
2122         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
2123         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
2124         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
2125         vc4_hdmi->pdev = pdev;
2126         vc4_hdmi->variant = variant;
2127
2128         ret = variant->init_resources(vc4_hdmi);
2129         if (ret)
2130                 return ret;
2131
2132         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2133         if (!ddc_node) {
2134                 DRM_ERROR("Failed to find ddc node in device tree\n");
2135                 return -ENODEV;
2136         }
2137
2138         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2139         of_node_put(ddc_node);
2140         if (!vc4_hdmi->ddc) {
2141                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
2142                 return -EPROBE_DEFER;
2143         }
2144
2145         /* Only use the GPIO HPD pin if present in the DT, otherwise
2146          * we'll use the HDMI core's register.
2147          */
2148         vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
2149         if (IS_ERR(vc4_hdmi->hpd_gpio)) {
2150                 ret = PTR_ERR(vc4_hdmi->hpd_gpio);
2151                 goto err_put_ddc;
2152         }
2153
2154         vc4_hdmi->disable_wifi_frequencies =
2155                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2156
2157         if (variant->max_pixel_clock == 600000000) {
2158                 struct vc4_dev *vc4 = to_vc4_dev(drm);
2159                 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
2160
2161                 if (max_rate < 550000000)
2162                         vc4_hdmi->disable_4kp60 = true;
2163         }
2164
2165         if (vc4_hdmi->variant->reset)
2166                 vc4_hdmi->variant->reset(vc4_hdmi);
2167
2168         if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
2169              of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
2170             HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
2171                 clk_prepare_enable(vc4_hdmi->pixel_clock);
2172                 clk_prepare_enable(vc4_hdmi->hsm_clock);
2173                 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
2174         }
2175
2176         pm_runtime_enable(dev);
2177
2178         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2179         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2180
2181         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2182         if (ret)
2183                 goto err_destroy_encoder;
2184
2185         ret = vc4_hdmi_hotplug_init(vc4_hdmi);
2186         if (ret)
2187                 goto err_destroy_conn;
2188
2189         ret = vc4_hdmi_cec_init(vc4_hdmi);
2190         if (ret)
2191                 goto err_free_hotplug;
2192
2193         ret = vc4_hdmi_audio_init(vc4_hdmi);
2194         if (ret)
2195                 goto err_free_cec;
2196
2197         vc4_debugfs_add_file(drm, variant->debugfs_name,
2198                              vc4_hdmi_debugfs_regs,
2199                              vc4_hdmi);
2200
2201         return 0;
2202
2203 err_free_cec:
2204         vc4_hdmi_cec_exit(vc4_hdmi);
2205 err_free_hotplug:
2206         vc4_hdmi_hotplug_exit(vc4_hdmi);
2207 err_destroy_conn:
2208         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2209 err_destroy_encoder:
2210         drm_encoder_cleanup(encoder);
2211         pm_runtime_disable(dev);
2212 err_put_ddc:
2213         put_device(&vc4_hdmi->ddc->dev);
2214
2215         return ret;
2216 }
2217
2218 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2219                             void *data)
2220 {
2221         struct vc4_hdmi *vc4_hdmi;
2222
2223         /*
2224          * ASoC makes it a bit hard to retrieve a pointer to the
2225          * vc4_hdmi structure. Registering the card will overwrite our
2226          * device drvdata with a pointer to the snd_soc_card structure,
2227          * which can then be used to retrieve whatever drvdata we want
2228          * to associate.
2229          *
2230          * However, that doesn't fly in the case where we wouldn't
2231          * register an ASoC card (because of an old DT that is missing
2232          * the dmas properties for example), then the card isn't
2233          * registered and the device drvdata wouldn't be set.
2234          *
2235          * We can deal with both cases by making sure a snd_soc_card
2236          * pointer and a vc4_hdmi structure are pointing to the same
2237          * memory address, so we can treat them indistinctly without any
2238          * issue.
2239          */
2240         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2241         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2242         vc4_hdmi = dev_get_drvdata(dev);
2243
2244         kfree(vc4_hdmi->hdmi_regset.regs);
2245         kfree(vc4_hdmi->hd_regset.regs);
2246
2247         vc4_hdmi_cec_exit(vc4_hdmi);
2248         vc4_hdmi_hotplug_exit(vc4_hdmi);
2249         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2250         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2251
2252         pm_runtime_disable(dev);
2253
2254         put_device(&vc4_hdmi->ddc->dev);
2255 }
2256
2257 static const struct component_ops vc4_hdmi_ops = {
2258         .bind   = vc4_hdmi_bind,
2259         .unbind = vc4_hdmi_unbind,
2260 };
2261
2262 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2263 {
2264         return component_add(&pdev->dev, &vc4_hdmi_ops);
2265 }
2266
2267 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2268 {
2269         component_del(&pdev->dev, &vc4_hdmi_ops);
2270         return 0;
2271 }
2272
2273 static const struct vc4_hdmi_variant bcm2835_variant = {
2274         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2275         .debugfs_name           = "hdmi_regs",
2276         .card_name              = "vc4-hdmi",
2277         .max_pixel_clock        = 162000000,
2278         .registers              = vc4_hdmi_fields,
2279         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2280
2281         .init_resources         = vc4_hdmi_init_resources,
2282         .csc_setup              = vc4_hdmi_csc_setup,
2283         .reset                  = vc4_hdmi_reset,
2284         .set_timings            = vc4_hdmi_set_timings,
2285         .phy_init               = vc4_hdmi_phy_init,
2286         .phy_disable            = vc4_hdmi_phy_disable,
2287         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2288         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2289         .channel_map            = vc4_hdmi_channel_map,
2290         .supports_hdr           = false,
2291 };
2292
2293 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2294         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2295         .debugfs_name           = "hdmi0_regs",
2296         .card_name              = "vc4-hdmi-0",
2297         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2298         .registers              = vc5_hdmi_hdmi0_fields,
2299         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2300         .phy_lane_mapping       = {
2301                 PHY_LANE_0,
2302                 PHY_LANE_1,
2303                 PHY_LANE_2,
2304                 PHY_LANE_CK,
2305         },
2306         .unsupported_odd_h_timings      = true,
2307         .external_irq_controller        = true,
2308
2309         .init_resources         = vc5_hdmi_init_resources,
2310         .csc_setup              = vc5_hdmi_csc_setup,
2311         .reset                  = vc5_hdmi_reset,
2312         .set_timings            = vc5_hdmi_set_timings,
2313         .phy_init               = vc5_hdmi_phy_init,
2314         .phy_disable            = vc5_hdmi_phy_disable,
2315         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2316         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2317         .channel_map            = vc5_hdmi_channel_map,
2318         .supports_hdr           = true,
2319 };
2320
2321 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2322         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2323         .debugfs_name           = "hdmi1_regs",
2324         .card_name              = "vc4-hdmi-1",
2325         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2326         .registers              = vc5_hdmi_hdmi1_fields,
2327         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2328         .phy_lane_mapping       = {
2329                 PHY_LANE_1,
2330                 PHY_LANE_0,
2331                 PHY_LANE_CK,
2332                 PHY_LANE_2,
2333         },
2334         .unsupported_odd_h_timings      = true,
2335         .external_irq_controller        = true,
2336
2337         .init_resources         = vc5_hdmi_init_resources,
2338         .csc_setup              = vc5_hdmi_csc_setup,
2339         .reset                  = vc5_hdmi_reset,
2340         .set_timings            = vc5_hdmi_set_timings,
2341         .phy_init               = vc5_hdmi_phy_init,
2342         .phy_disable            = vc5_hdmi_phy_disable,
2343         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2344         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2345         .channel_map            = vc5_hdmi_channel_map,
2346         .supports_hdr           = true,
2347 };
2348
2349 static const struct of_device_id vc4_hdmi_dt_match[] = {
2350         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2351         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2352         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2353         {}
2354 };
2355
2356 struct platform_driver vc4_hdmi_driver = {
2357         .probe = vc4_hdmi_dev_probe,
2358         .remove = vc4_hdmi_dev_remove,
2359         .driver = {
2360                 .name = "vc4_hdmi",
2361                 .of_match_table = vc4_hdmi_dt_match,
2362         },
2363 };