drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_dmc.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dp.h"
  54 #include "display/intel_fbdev.h"
  55 #include "display/intel_hotplug.h"
  56 #include "display/intel_overlay.h"
  57 #include "display/intel_pipe_crc.h"
  58 #include "display/intel_pps.h"
  59 #include "display/intel_sprite.h"
  60 #include "display/intel_vga.h"
  61
  62 #include "gem/i915_gem_context.h"
  63 #include "gem/i915_gem_ioctls.h"
  64 #include "gem/i915_gem_mman.h"
  65 #include "gem/i915_gem_pm.h"
  66 #include "gt/intel_gt.h"
  67 #include "gt/intel_gt_pm.h"
  68 #include "gt/intel_rc6.h"
  69
  70 #include "pxp/intel_pxp_pm.h"
  71
  72 #include "i915_debugfs.h"
  73 #include "i915_drv.h"
  74 #include "i915_ioc32.h"
  75 #include "i915_irq.h"
  76 #include "i915_memcpy.h"
  77 #include "i915_perf.h"
  78 #include "i915_query.h"
  79 #include "i915_suspend.h"
  80 #include "i915_switcheroo.h"
  81 #include "i915_sysfs.h"
  82 #include "i915_trace.h"
  83 #include "i915_vgpu.h"
  84 #include "intel_dram.h"
  85 #include "intel_gvt.h"
  86 #include "intel_memory_region.h"
  87 #include "intel_pcode.h"
  88 #include "intel_pm.h"
  89 #include "intel_region_ttm.h"
  90 #include "vlv_suspend.h"
  91
  92 static const struct drm_driver driver;
  93
  94 static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
  95 {
  96         int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus);
  97
  98         dev_priv->bridge_dev =
  99                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
 100         if (!dev_priv->bridge_dev) {
 101                 drm_err(&dev_priv->drm, "bridge device not found\n");
 102                 return -EIO;
 103         }
 104         return 0;
 105 }
 106
 107 /* Allocate space for the MCH regs if needed, return nonzero on error */
 108 static int
 109 intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
 110 {
 111         int reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 112         u32 temp_lo, temp_hi = 0;
 113         u64 mchbar_addr;
 114         int ret;
 115
 116         if (GRAPHICS_VER(dev_priv) >= 4)
 117                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 118         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 119         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 120
 121         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 122 #ifdef CONFIG_PNP
 123         if (mchbar_addr &&
 124             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 125                 return 0;
 126 #endif
 127
 128         /* Get some space for it */
 129         dev_priv->mch_res.name = "i915 MCHBAR";
 130         dev_priv->mch_res.flags = IORESOURCE_MEM;
 131         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 132                                      &dev_priv->mch_res,
 133                                      MCHBAR_SIZE, MCHBAR_SIZE,
 134                                      PCIBIOS_MIN_MEM,
 135                                      0, pcibios_align_resource,
 136                                      dev_priv->bridge_dev);
 137         if (ret) {
 138                 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
 139                 dev_priv->mch_res.start = 0;
 140                 return ret;
 141         }
 142
 143         if (GRAPHICS_VER(dev_priv) >= 4)
 144                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 145                                        upper_32_bits(dev_priv->mch_res.start));
 146
 147         pci_write_config_dword(dev_priv->bridge_dev, reg,
 148                                lower_32_bits(dev_priv->mch_res.start));
 149         return 0;
 150 }
 151
 152 /* Setup MCHBAR if possible, return true if we should disable it again */
 153 static void
 154 intel_setup_mchbar(struct drm_i915_private *dev_priv)
 155 {
 156         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 157         u32 temp;
 158         bool enabled;
 159
 160         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 161                 return;
 162
 163         dev_priv->mchbar_need_disable = false;
 164
 165         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 166                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 167                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 168         } else {
 169                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 170                 enabled = temp & 1;
 171         }
 172
 173         /* If it's already enabled, don't have to do anything */
 174         if (enabled)
 175                 return;
 176
 177         if (intel_alloc_mchbar_resource(dev_priv))
 178                 return;
 179
 180         dev_priv->mchbar_need_disable = true;
 181
 182         /* Space is allocated or reserved, so enable it. */
 183         if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 184                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 185                                        temp | DEVEN_MCHBAR_EN);
 186         } else {
 187                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 188                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 189         }
 190 }
 191
 192 static void
 193 intel_teardown_mchbar(struct drm_i915_private *dev_priv)
 194 {
 195         int mchbar_reg = GRAPHICS_VER(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 196
 197         if (dev_priv->mchbar_need_disable) {
 198                 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
 199                         u32 deven_val;
 200
 201                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 202                                               &deven_val);
 203                         deven_val &= ~DEVEN_MCHBAR_EN;
 204                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 205                                                deven_val);
 206                 } else {
 207                         u32 mchbar_val;
 208
 209                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 210                                               &mchbar_val);
 211                         mchbar_val &= ~1;
 212                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 213                                                mchbar_val);
 214                 }
 215         }
 216
 217         if (dev_priv->mch_res.start)
 218                 release_resource(&dev_priv->mch_res);
 219 }
 220
 221 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 222 {
 223         /*
 224          * The i915 workqueue is primarily used for batched retirement of
 225          * requests (and thus managing bo) once the task has been completed
 226          * by the GPU. i915_retire_requests() is called directly when we
 227          * need high-priority retirement, such as waiting for an explicit
 228          * bo.
 229          *
 230          * It is also used for periodic low-priority events, such as
 231          * idle-timers and recording error state.
 232          *
 233          * All tasks on the workqueue are expected to acquire the dev mutex
 234          * so there is no point in running more than one instance of the
 235          * workqueue at any time.  Use an ordered one.
 236          */
 237         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 238         if (dev_priv->wq == NULL)
 239                 goto out_err;
 240
 241         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 242         if (dev_priv->hotplug.dp_wq == NULL)
 243                 goto out_free_wq;
 244
 245         return 0;
 246
 247 out_free_wq:
 248         destroy_workqueue(dev_priv->wq);
 249 out_err:
 250         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 251
 252         return -ENOMEM;
 253 }
 254
 255 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 256 {
 257         destroy_workqueue(dev_priv->hotplug.dp_wq);
 258         destroy_workqueue(dev_priv->wq);
 259 }
 260
 261 /*
 262  * We don't keep the workarounds for pre-production hardware, so we expect our
 263  * driver to fail on these machines in one way or another. A little warning on
 264  * dmesg may help both the user and the bug triagers.
 265  *
 266  * Our policy for removing pre-production workarounds is to keep the
 267  * current gen workarounds as a guide to the bring-up of the next gen
 268  * (workarounds have a habit of persisting!). Anything older than that
 269  * should be removed along with the complications they introduce.
 270  */
 271 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 272 {
 273         bool pre = false;
 274
 275         pre |= IS_HSW_EARLY_SDV(dev_priv);
 276         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 277         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 278         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 279         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 280         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 281
 282         if (pre) {
 283                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 284                           "It may not be fully functional.\n");
 285                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 286         }
 287 }
 288
 289 static void sanitize_gpu(struct drm_i915_private *i915)
 290 {
 291         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
 292                 __intel_gt_reset(&i915->gt, ALL_ENGINES);
 293 }
 294
 295 /**
 296  * i915_driver_early_probe - setup state not requiring device access
 297  * @dev_priv: device private
 298  *
 299  * Initialize everything that is a "SW-only" state, that is state not
 300  * requiring accessing the device or exposing the driver via kernel internal
 301  * or userspace interfaces. Example steps belonging here: lock initialization,
 302  * system memory allocation, setting up device specific attributes and
 303  * function hooks not requiring accessing the device.
 304  */
 305 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 306 {
 307         int ret = 0;
 308
 309         if (i915_inject_probe_failure(dev_priv))
 310                 return -ENODEV;
 311
 312         intel_device_info_subplatform_init(dev_priv);
 313         intel_step_init(dev_priv);
 314
 315         intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
 316         intel_uncore_init_early(&dev_priv->uncore, dev_priv);
 317
 318         spin_lock_init(&dev_priv->irq_lock);
 319         spin_lock_init(&dev_priv->gpu_error.lock);
 320         mutex_init(&dev_priv->backlight_lock);
 321
 322         mutex_init(&dev_priv->sb_lock);
 323         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 324
 325         mutex_init(&dev_priv->av_mutex);
 326         mutex_init(&dev_priv->wm.wm_mutex);
 327         mutex_init(&dev_priv->pps_mutex);
 328         mutex_init(&dev_priv->hdcp_comp_mutex);
 329
 330         i915_memcpy_init_early(dev_priv);
 331         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 332
 333         ret = i915_workqueues_init(dev_priv);
 334         if (ret < 0)
 335                 return ret;
 336
 337         ret = vlv_suspend_init(dev_priv);
 338         if (ret < 0)
 339                 goto err_workqueues;
 340
 341         ret = intel_region_ttm_device_init(dev_priv);
 342         if (ret)
 343                 goto err_ttm;
 344
 345         intel_wopcm_init_early(&dev_priv->wopcm);
 346
 347         intel_gt_init_early(&dev_priv->gt, dev_priv);
 348
 349         i915_gem_init_early(dev_priv);
 350
 351         /* This must be called before any calls to HAS_PCH_* */
 352         intel_detect_pch(dev_priv);
 353
 354         intel_pm_setup(dev_priv);
 355         ret = intel_power_domains_init(dev_priv);
 356         if (ret < 0)
 357                 goto err_gem;
 358         intel_irq_init(dev_priv);
 359         intel_init_display_hooks(dev_priv);
 360         intel_init_clock_gating_hooks(dev_priv);
 361
 362         intel_detect_preproduction_hw(dev_priv);
 363
 364         return 0;
 365
 366 err_gem:
 367         i915_gem_cleanup_early(dev_priv);
 368         intel_gt_driver_late_release(&dev_priv->gt);
 369         intel_region_ttm_device_fini(dev_priv);
 370 err_ttm:
 371         vlv_suspend_cleanup(dev_priv);
 372 err_workqueues:
 373         i915_workqueues_cleanup(dev_priv);
 374         return ret;
 375 }
 376
 377 /**
 378  * i915_driver_late_release - cleanup the setup done in
 379  *                             i915_driver_early_probe()
 380  * @dev_priv: device private
 381  */
 382 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 383 {
 384         intel_irq_fini(dev_priv);
 385         intel_power_domains_cleanup(dev_priv);
 386         i915_gem_cleanup_early(dev_priv);
 387         intel_gt_driver_late_release(&dev_priv->gt);
 388         intel_region_ttm_device_fini(dev_priv);
 389         vlv_suspend_cleanup(dev_priv);
 390         i915_workqueues_cleanup(dev_priv);
 391
 392         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 393         mutex_destroy(&dev_priv->sb_lock);
 394
 395         i915_params_free(&dev_priv->params);
 396 }
 397
 398 /**
 399  * i915_driver_mmio_probe - setup device MMIO
 400  * @dev_priv: device private
 401  *
 402  * Setup minimal device state necessary for MMIO accesses later in the
 403  * initialization sequence. The setup here should avoid any other device-wide
 404  * side effects or exposing the driver via kernel internal or user space
 405  * interfaces.
 406  */
 407 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 408 {
 409         int ret;
 410
 411         if (i915_inject_probe_failure(dev_priv))
 412                 return -ENODEV;
 413
 414         ret = i915_get_bridge_dev(dev_priv);
 415         if (ret < 0)
 416                 return ret;
 417
 418         ret = intel_uncore_init_mmio(&dev_priv->uncore);
 419         if (ret < 0)
 420                 goto err_bridge;
 421
 422         /* Try to make sure MCHBAR is enabled before poking at it */
 423         intel_setup_mchbar(dev_priv);
 424         intel_device_info_runtime_init(dev_priv);
 425
 426         ret = intel_gt_init_mmio(&dev_priv->gt);
 427         if (ret)
 428                 goto err_uncore;
 429
 430         /* As early as possible, scrub existing GPU state before clobbering */
 431         sanitize_gpu(dev_priv);
 432
 433         return 0;
 434
 435 err_uncore:
 436         intel_teardown_mchbar(dev_priv);
 437         intel_uncore_fini_mmio(&dev_priv->uncore);
 438 err_bridge:
 439         pci_dev_put(dev_priv->bridge_dev);
 440
 441         return ret;
 442 }
 443
 444 /**
 445  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 446  * @dev_priv: device private
 447  */
 448 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 449 {
 450         intel_teardown_mchbar(dev_priv);
 451         intel_uncore_fini_mmio(&dev_priv->uncore);
 452         pci_dev_put(dev_priv->bridge_dev);
 453 }
 454
 455 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 456 {
 457         intel_gvt_sanitize_options(dev_priv);
 458 }
 459
 460 /**
 461  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 462  * platform
 463  * @i915: valid i915 instance
 464  *
 465  * Set the dma max segment size, device and coherent masks.  The dma mask set
 466  * needs to occur before i915_ggtt_probe_hw.
 467  *
 468  * A couple of platforms have special needs.  Address them as well.
 469  *
 470  */
 471 static int i915_set_dma_info(struct drm_i915_private *i915)
 472 {
 473         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 474         int ret;
 475
 476         GEM_BUG_ON(!mask_size);
 477
 478         /*
 479          * We don't have a max segment size, so set it to the max so sg's
 480          * debugging layer doesn't complain
 481          */
 482         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 483
 484         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 485         if (ret)
 486                 goto mask_err;
 487
 488         /* overlay on gen2 is broken and can't address above 1G */
 489         if (GRAPHICS_VER(i915) == 2)
 490                 mask_size = 30;
 491
 492         /*
 493          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 494          * using 32bit addressing, overwriting memory if HWS is located
 495          * above 4GB.
 496          *
 497          * The documentation also mentions an issue with undefined
 498          * behaviour if any general state is accessed within a page above 4GB,
 499          * which also needs to be handled carefully.
 500          */
 501         if (IS_I965G(i915) || IS_I965GM(i915))
 502                 mask_size = 32;
 503
 504         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 505         if (ret)
 506                 goto mask_err;
 507
 508         return 0;
 509
 510 mask_err:
 511         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 512         return ret;
 513 }
 514
 515 /**
 516  * i915_driver_hw_probe - setup state requiring device access
 517  * @dev_priv: device private
 518  *
 519  * Setup state that requires accessing the device, but doesn't require
 520  * exposing the driver via kernel internal or userspace interfaces.
 521  */
 522 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 523 {
 524         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 525         int ret;
 526
 527         if (i915_inject_probe_failure(dev_priv))
 528                 return -ENODEV;
 529
 530         if (HAS_PPGTT(dev_priv)) {
 531                 if (intel_vgpu_active(dev_priv) &&
 532                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 533                         i915_report_error(dev_priv,
 534                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 535                         return -ENXIO;
 536                 }
 537         }
 538
 539         if (HAS_EXECLISTS(dev_priv)) {
 540                 /*
 541                  * Older GVT emulation depends upon intercepting CSB mmio,
 542                  * which we no longer use, preferring to use the HWSP cache
 543                  * instead.
 544                  */
 545                 if (intel_vgpu_active(dev_priv) &&
 546                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 547                         i915_report_error(dev_priv,
 548                                           "old vGPU host found, support for HWSP emulation required\n");
 549                         return -ENXIO;
 550                 }
 551         }
 552
 553         intel_sanitize_options(dev_priv);
 554
 555         /* needs to be done before ggtt probe */
 556         intel_dram_edram_detect(dev_priv);
 557
 558         ret = i915_set_dma_info(dev_priv);
 559         if (ret)
 560                 return ret;
 561
 562         i915_perf_init(dev_priv);
 563
 564         ret = i915_ggtt_probe_hw(dev_priv);
 565         if (ret)
 566                 goto err_perf;
 567
 568         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 569         if (ret)
 570                 goto err_ggtt;
 571
 572         ret = i915_ggtt_init_hw(dev_priv);
 573         if (ret)
 574                 goto err_ggtt;
 575
 576         ret = intel_memory_regions_hw_probe(dev_priv);
 577         if (ret)
 578                 goto err_ggtt;
 579
 580         intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
 581
 582         ret = intel_gt_probe_lmem(&dev_priv->gt);
 583         if (ret)
 584                 goto err_mem_regions;
 585
 586         ret = i915_ggtt_enable_hw(dev_priv);
 587         if (ret) {
 588                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 589                 goto err_mem_regions;
 590         }
 591
 592         pci_set_master(pdev);
 593
 594         /* On the 945G/GM, the chipset reports the MSI capability on the
 595          * integrated graphics even though the support isn't actually there
 596          * according to the published specs.  It doesn't appear to function
 597          * correctly in testing on 945G.
 598          * This may be a side effect of MSI having been made available for PEG
 599          * and the registers being closely associated.
 600          *
 601          * According to chipset errata, on the 965GM, MSI interrupts may
 602          * be lost or delayed, and was defeatured. MSI interrupts seem to
 603          * get lost on g4x as well, and interrupt delivery seems to stay
 604          * properly dead afterwards. So we'll just disable them for all
 605          * pre-gen5 chipsets.
 606          *
 607          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 608          * interrupts even when in MSI mode. This results in spurious
 609          * interrupt warnings if the legacy irq no. is shared with another
 610          * device. The kernel then disables that interrupt source and so
 611          * prevents the other device from working properly.
 612          */
 613         if (GRAPHICS_VER(dev_priv) >= 5) {
 614                 if (pci_enable_msi(pdev) < 0)
 615                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 616         }
 617
 618         ret = intel_gvt_init(dev_priv);
 619         if (ret)
 620                 goto err_msi;
 621
 622         intel_opregion_setup(dev_priv);
 623
 624         ret = intel_pcode_init(dev_priv);
 625         if (ret)
 626                 goto err_msi;
 627
 628         /*
 629          * Fill the dram structure to get the system dram info. This will be
 630          * used for memory latency calculation.
 631          */
 632         intel_dram_detect(dev_priv);
 633
 634         intel_bw_init_hw(dev_priv);
 635
 636         return 0;
 637
 638 err_msi:
 639         if (pdev->msi_enabled)
 640                 pci_disable_msi(pdev);
 641 err_mem_regions:
 642         intel_memory_regions_driver_release(dev_priv);
 643 err_ggtt:
 644         i915_ggtt_driver_release(dev_priv);
 645         i915_gem_drain_freed_objects(dev_priv);
 646         i915_ggtt_driver_late_release(dev_priv);
 647 err_perf:
 648         i915_perf_fini(dev_priv);
 649         return ret;
 650 }
 651
 652 /**
 653  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 654  * @dev_priv: device private
 655  */
 656 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 657 {
 658         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 659
 660         i915_perf_fini(dev_priv);
 661
 662         if (pdev->msi_enabled)
 663                 pci_disable_msi(pdev);
 664 }
 665
 666 /**
 667  * i915_driver_register - register the driver with the rest of the system
 668  * @dev_priv: device private
 669  *
 670  * Perform any steps necessary to make the driver available via kernel
 671  * internal or userspace interfaces.
 672  */
 673 static void i915_driver_register(struct drm_i915_private *dev_priv)
 674 {
 675         struct drm_device *dev = &dev_priv->drm;
 676
 677         i915_gem_driver_register(dev_priv);
 678         i915_pmu_register(dev_priv);
 679
 680         intel_vgpu_register(dev_priv);
 681
 682         /* Reveal our presence to userspace */
 683         if (drm_dev_register(dev, 0)) {
 684                 drm_err(&dev_priv->drm,
 685                         "Failed to register driver for userspace access!\n");
 686                 return;
 687         }
 688
 689         i915_debugfs_register(dev_priv);
 690         i915_setup_sysfs(dev_priv);
 691
 692         /* Depends on sysfs having been initialized */
 693         i915_perf_register(dev_priv);
 694
 695         intel_gt_driver_register(&dev_priv->gt);
 696
 697         intel_display_driver_register(dev_priv);
 698
 699         intel_power_domains_enable(dev_priv);
 700         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 701
 702         intel_register_dsm_handler();
 703
 704         if (i915_switcheroo_register(dev_priv))
 705                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 706 }
 707
 708 /**
 709  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 710  * @dev_priv: device private
 711  */
 712 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 713 {
 714         i915_switcheroo_unregister(dev_priv);
 715
 716         intel_unregister_dsm_handler();
 717
 718         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 719         intel_power_domains_disable(dev_priv);
 720
 721         intel_display_driver_unregister(dev_priv);
 722
 723         intel_gt_driver_unregister(&dev_priv->gt);
 724
 725         i915_perf_unregister(dev_priv);
 726         i915_pmu_unregister(dev_priv);
 727
 728         i915_teardown_sysfs(dev_priv);
 729         drm_dev_unplug(&dev_priv->drm);
 730
 731         i915_gem_driver_unregister(dev_priv);
 732 }
 733
 734 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 735 {
 736         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 737                 struct drm_printer p = drm_debug_printer("i915 device info:");
 738
 739                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 740                            INTEL_DEVID(dev_priv),
 741                            INTEL_REVID(dev_priv),
 742                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 743                            intel_subplatform(RUNTIME_INFO(dev_priv),
 744                                              INTEL_INFO(dev_priv)->platform),
 745                            GRAPHICS_VER(dev_priv));
 746
 747                 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 748                 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 749                 intel_gt_info_print(&dev_priv->gt.info, &p);
 750         }
 751
 752         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 753                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 754         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 755                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 756         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 757                 drm_info(&dev_priv->drm,
 758                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 759 }
 760
 761 static struct drm_i915_private *
 762 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 763 {
 764         const struct intel_device_info *match_info =
 765                 (struct intel_device_info *)ent->driver_data;
 766         struct intel_device_info *device_info;
 767         struct drm_i915_private *i915;
 768
 769         i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
 770                                   struct drm_i915_private, drm);
 771         if (IS_ERR(i915))
 772                 return i915;
 773
 774         pci_set_drvdata(pdev, i915);
 775
 776         /* Device parameters start as a copy of module parameters. */
 777         i915_params_copy(&i915->params, &i915_modparams);
 778
 779         /* Setup the write-once "constant" device info */
 780         device_info = mkwrite_device_info(i915);
 781         memcpy(device_info, match_info, sizeof(*device_info));
 782         RUNTIME_INFO(i915)->device_id = pdev->device;
 783
 784         return i915;
 785 }
 786
 787 /**
 788  * i915_driver_probe - setup chip and create an initial config
 789  * @pdev: PCI device
 790  * @ent: matching PCI ID entry
 791  *
 792  * The driver probe routine has to do several things:
 793  *   - drive output discovery via intel_modeset_init()
 794  *   - initialize the memory manager
 795  *   - allocate initial config memory
 796  *   - setup the DRM framebuffer with the allocated memory
 797  */
 798 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 799 {
 800         const struct intel_device_info *match_info =
 801                 (struct intel_device_info *)ent->driver_data;
 802         struct drm_i915_private *i915;
 803         int ret;
 804
 805         i915 = i915_driver_create(pdev, ent);
 806         if (IS_ERR(i915))
 807                 return PTR_ERR(i915);
 808
 809         /* Disable nuclear pageflip by default on pre-ILK */
 810         if (!i915->params.nuclear_pageflip && match_info->graphics_ver < 5)
 811                 i915->drm.driver_features &= ~DRIVER_ATOMIC;
 812
 813         /*
 814          * Check if we support fake LMEM -- for now we only unleash this for
 815          * the live selftests(test-and-exit).
 816          */
 817 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 818         if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
 819                 if (GRAPHICS_VER(i915) >= 9 && i915_selftest.live < 0 &&
 820                     i915->params.fake_lmem_start) {
 821                         mkwrite_device_info(i915)->memory_regions =
 822                                 REGION_SMEM | REGION_LMEM | REGION_STOLEN_SMEM;
 823                         GEM_BUG_ON(!HAS_LMEM(i915));
 824                 }
 825         }
 826 #endif
 827
 828         ret = pci_enable_device(pdev);
 829         if (ret)
 830                 goto out_fini;
 831
 832         ret = i915_driver_early_probe(i915);
 833         if (ret < 0)
 834                 goto out_pci_disable;
 835
 836         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 837
 838         intel_vgpu_detect(i915);
 839
 840         ret = i915_driver_mmio_probe(i915);
 841         if (ret < 0)
 842                 goto out_runtime_pm_put;
 843
 844         ret = i915_driver_hw_probe(i915);
 845         if (ret < 0)
 846                 goto out_cleanup_mmio;
 847
 848         ret = intel_modeset_init_noirq(i915);
 849         if (ret < 0)
 850                 goto out_cleanup_hw;
 851
 852         ret = intel_irq_install(i915);
 853         if (ret)
 854                 goto out_cleanup_modeset;
 855
 856         ret = intel_modeset_init_nogem(i915);
 857         if (ret)
 858                 goto out_cleanup_irq;
 859
 860         ret = i915_gem_init(i915);
 861         if (ret)
 862                 goto out_cleanup_modeset2;
 863
 864         ret = intel_modeset_init(i915);
 865         if (ret)
 866                 goto out_cleanup_gem;
 867
 868         i915_driver_register(i915);
 869
 870         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 871
 872         i915_welcome_messages(i915);
 873
 874         i915->do_release = true;
 875
 876         return 0;
 877
 878 out_cleanup_gem:
 879         i915_gem_suspend(i915);
 880         i915_gem_driver_remove(i915);
 881         i915_gem_driver_release(i915);
 882 out_cleanup_modeset2:
 883         /* FIXME clean up the error path */
 884         intel_modeset_driver_remove(i915);
 885         intel_irq_uninstall(i915);
 886         intel_modeset_driver_remove_noirq(i915);
 887         goto out_cleanup_modeset;
 888 out_cleanup_irq:
 889         intel_irq_uninstall(i915);
 890 out_cleanup_modeset:
 891         intel_modeset_driver_remove_nogem(i915);
 892 out_cleanup_hw:
 893         i915_driver_hw_remove(i915);
 894         intel_memory_regions_driver_release(i915);
 895         i915_ggtt_driver_release(i915);
 896         i915_gem_drain_freed_objects(i915);
 897         i915_ggtt_driver_late_release(i915);
 898 out_cleanup_mmio:
 899         i915_driver_mmio_release(i915);
 900 out_runtime_pm_put:
 901         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 902         i915_driver_late_release(i915);
 903 out_pci_disable:
 904         pci_disable_device(pdev);
 905 out_fini:
 906         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 907         return ret;
 908 }
 909
 910 void i915_driver_remove(struct drm_i915_private *i915)
 911 {
 912         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 913
 914         i915_driver_unregister(i915);
 915
 916         /* Flush any external code that still may be under the RCU lock */
 917         synchronize_rcu();
 918
 919         i915_gem_suspend(i915);
 920
 921         intel_gvt_driver_remove(i915);
 922
 923         intel_modeset_driver_remove(i915);
 924
 925         intel_irq_uninstall(i915);
 926
 927         intel_modeset_driver_remove_noirq(i915);
 928
 929         i915_reset_error_state(i915);
 930         i915_gem_driver_remove(i915);
 931
 932         intel_modeset_driver_remove_nogem(i915);
 933
 934         i915_driver_hw_remove(i915);
 935
 936         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 937 }
 938
 939 static void i915_driver_release(struct drm_device *dev)
 940 {
 941         struct drm_i915_private *dev_priv = to_i915(dev);
 942         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 943
 944         if (!dev_priv->do_release)
 945                 return;
 946
 947         disable_rpm_wakeref_asserts(rpm);
 948
 949         i915_gem_driver_release(dev_priv);
 950
 951         intel_memory_regions_driver_release(dev_priv);
 952         i915_ggtt_driver_release(dev_priv);
 953         i915_gem_drain_freed_objects(dev_priv);
 954         i915_ggtt_driver_late_release(dev_priv);
 955
 956         i915_driver_mmio_release(dev_priv);
 957
 958         enable_rpm_wakeref_asserts(rpm);
 959         intel_runtime_pm_driver_release(rpm);
 960
 961         i915_driver_late_release(dev_priv);
 962 }
 963
 964 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 965 {
 966         struct drm_i915_private *i915 = to_i915(dev);
 967         int ret;
 968
 969         ret = i915_gem_open(i915, file);
 970         if (ret)
 971                 return ret;
 972
 973         return 0;
 974 }
 975
 976 /**
 977  * i915_driver_lastclose - clean up after all DRM clients have exited
 978  * @dev: DRM device
 979  *
 980  * Take care of cleaning up after all DRM clients have exited.  In the
 981  * mode setting case, we want to restore the kernel's initial mode (just
 982  * in case the last client left us in a bad state).
 983  *
 984  * Additionally, in the non-mode setting case, we'll tear down the GTT
 985  * and DMA structures, since the kernel won't be using them, and clea
 986  * up any GEM state.
 987  */
 988 static void i915_driver_lastclose(struct drm_device *dev)
 989 {
 990         struct drm_i915_private *i915 = to_i915(dev);
 991
 992         intel_fbdev_restore_mode(dev);
 993
 994         if (HAS_DISPLAY(i915))
 995                 vga_switcheroo_process_delayed_switch();
 996 }
 997
 998 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 999 {
1000         struct drm_i915_file_private *file_priv = file->driver_priv;
1001
1002         i915_gem_context_close(file);
1003
1004         kfree_rcu(file_priv, rcu);
1005
1006         /* Catch up with all the deferred frees from "this" client */
1007         i915_gem_flush_free_objects(to_i915(dev));
1008 }
1009
1010 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1011 {
1012         struct drm_device *dev = &dev_priv->drm;
1013         struct intel_encoder *encoder;
1014
1015         if (!HAS_DISPLAY(dev_priv))
1016                 return;
1017
1018         drm_modeset_lock_all(dev);
1019         for_each_intel_encoder(dev, encoder)
1020                 if (encoder->suspend)
1021                         encoder->suspend(encoder);
1022         drm_modeset_unlock_all(dev);
1023 }
1024
1025 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
1026 {
1027         struct drm_device *dev = &dev_priv->drm;
1028         struct intel_encoder *encoder;
1029
1030         if (!HAS_DISPLAY(dev_priv))
1031                 return;
1032
1033         drm_modeset_lock_all(dev);
1034         for_each_intel_encoder(dev, encoder)
1035                 if (encoder->shutdown)
1036                         encoder->shutdown(encoder);
1037         drm_modeset_unlock_all(dev);
1038 }
1039
1040 void i915_driver_shutdown(struct drm_i915_private *i915)
1041 {
1042         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1043         intel_runtime_pm_disable(&i915->runtime_pm);
1044         intel_power_domains_disable(i915);
1045
1046         i915_gem_suspend(i915);
1047
1048         if (HAS_DISPLAY(i915)) {
1049                 drm_kms_helper_poll_disable(&i915->drm);
1050
1051                 drm_atomic_helper_shutdown(&i915->drm);
1052         }
1053
1054         intel_dp_mst_suspend(i915);
1055
1056         intel_runtime_pm_disable_interrupts(i915);
1057         intel_hpd_cancel_work(i915);
1058
1059         intel_suspend_encoders(i915);
1060         intel_shutdown_encoders(i915);
1061
1062         intel_dmc_ucode_suspend(i915);
1063
1064         /*
1065          * The only requirement is to reboot with display DC states disabled,
1066          * for now leaving all display power wells in the INIT power domain
1067          * enabled.
1068          *
1069          * TODO:
1070          * - unify the pci_driver::shutdown sequence here with the
1071          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1072          * - unify the driver remove and system/runtime suspend sequences with
1073          *   the above unified shutdown/poweroff sequence.
1074          */
1075         intel_power_domains_driver_remove(i915);
1076         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1077
1078         intel_runtime_pm_driver_release(&i915->runtime_pm);
1079 }
1080
1081 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1082 {
1083 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1084         if (acpi_target_system_state() < ACPI_STATE_S3)
1085                 return true;
1086 #endif
1087         return false;
1088 }
1089
1090 static int i915_drm_prepare(struct drm_device *dev)
1091 {
1092         struct drm_i915_private *i915 = to_i915(dev);
1093
1094         /*
1095          * NB intel_display_suspend() may issue new requests after we've
1096          * ostensibly marked the GPU as ready-to-sleep here. We need to
1097          * split out that work and pull it forward so that after point,
1098          * the GPU is not woken again.
1099          */
1100         return i915_gem_backup_suspend(i915);
1101 }
1102
1103 static int i915_drm_suspend(struct drm_device *dev)
1104 {
1105         struct drm_i915_private *dev_priv = to_i915(dev);
1106         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1107         pci_power_t opregion_target_state;
1108
1109         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1110
1111         /* We do a lot of poking in a lot of registers, make sure they work
1112          * properly. */
1113         intel_power_domains_disable(dev_priv);
1114         if (HAS_DISPLAY(dev_priv))
1115                 drm_kms_helper_poll_disable(dev);
1116
1117         pci_save_state(pdev);
1118
1119         intel_display_suspend(dev);
1120
1121         intel_dp_mst_suspend(dev_priv);
1122
1123         intel_runtime_pm_disable_interrupts(dev_priv);
1124         intel_hpd_cancel_work(dev_priv);
1125
1126         intel_suspend_encoders(dev_priv);
1127
1128         intel_suspend_hw(dev_priv);
1129
1130         i915_ggtt_suspend(&dev_priv->ggtt);
1131
1132         i915_save_display(dev_priv);
1133
1134         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1135         intel_opregion_suspend(dev_priv, opregion_target_state);
1136
1137         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1138
1139         dev_priv->suspend_count++;
1140
1141         intel_dmc_ucode_suspend(dev_priv);
1142
1143         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1144
1145         return 0;
1146 }
1147
1148 static enum i915_drm_suspend_mode
1149 get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1150 {
1151         if (hibernate)
1152                 return I915_DRM_SUSPEND_HIBERNATE;
1153
1154         if (suspend_to_idle(dev_priv))
1155                 return I915_DRM_SUSPEND_IDLE;
1156
1157         return I915_DRM_SUSPEND_MEM;
1158 }
1159
1160 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1161 {
1162         struct drm_i915_private *dev_priv = to_i915(dev);
1163         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1164         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1165         int ret;
1166
1167         disable_rpm_wakeref_asserts(rpm);
1168
1169         i915_gem_suspend_late(dev_priv);
1170
1171         intel_uncore_suspend(&dev_priv->uncore);
1172
1173         intel_power_domains_suspend(dev_priv,
1174                                     get_suspend_mode(dev_priv, hibernation));
1175
1176         intel_display_power_suspend_late(dev_priv);
1177
1178         ret = vlv_suspend_complete(dev_priv);
1179         if (ret) {
1180                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1181                 intel_power_domains_resume(dev_priv);
1182
1183                 goto out;
1184         }
1185
1186         pci_disable_device(pdev);
1187         /*
1188          * During hibernation on some platforms the BIOS may try to access
1189          * the device even though it's already in D3 and hang the machine. So
1190          * leave the device in D0 on those platforms and hope the BIOS will
1191          * power down the device properly. The issue was seen on multiple old
1192          * GENs with different BIOS vendors, so having an explicit blacklist
1193          * is inpractical; apply the workaround on everything pre GEN6. The
1194          * platforms where the issue was seen:
1195          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1196          * Fujitsu FSC S7110
1197          * Acer Aspire 1830T
1198          */
1199         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1200                 pci_set_power_state(pdev, PCI_D3hot);
1201
1202 out:
1203         enable_rpm_wakeref_asserts(rpm);
1204         if (!dev_priv->uncore.user_forcewake_count)
1205                 intel_runtime_pm_driver_release(rpm);
1206
1207         return ret;
1208 }
1209
1210 int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1211 {
1212         int error;
1213
1214         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1215                              state.event != PM_EVENT_FREEZE))
1216                 return -EINVAL;
1217
1218         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1219                 return 0;
1220
1221         error = i915_drm_suspend(&i915->drm);
1222         if (error)
1223                 return error;
1224
1225         return i915_drm_suspend_late(&i915->drm, false);
1226 }
1227
1228 static int i915_drm_resume(struct drm_device *dev)
1229 {
1230         struct drm_i915_private *dev_priv = to_i915(dev);
1231         int ret;
1232
1233         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1234
1235         ret = intel_pcode_init(dev_priv);
1236         if (ret)
1237                 return ret;
1238
1239         sanitize_gpu(dev_priv);
1240
1241         ret = i915_ggtt_enable_hw(dev_priv);
1242         if (ret)
1243                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1244
1245         i915_ggtt_resume(&dev_priv->ggtt);
1246
1247         intel_dmc_ucode_resume(dev_priv);
1248
1249         i915_restore_display(dev_priv);
1250         intel_pps_unlock_regs_wa(dev_priv);
1251
1252         intel_init_pch_refclk(dev_priv);
1253
1254         /*
1255          * Interrupts have to be enabled before any batches are run. If not the
1256          * GPU will hang. i915_gem_init_hw() will initiate batches to
1257          * update/restore the context.
1258          *
1259          * drm_mode_config_reset() needs AUX interrupts.
1260          *
1261          * Modeset enabling in intel_modeset_init_hw() also needs working
1262          * interrupts.
1263          */
1264         intel_runtime_pm_enable_interrupts(dev_priv);
1265
1266         if (HAS_DISPLAY(dev_priv))
1267                 drm_mode_config_reset(dev);
1268
1269         i915_gem_resume(dev_priv);
1270
1271         intel_modeset_init_hw(dev_priv);
1272         intel_init_clock_gating(dev_priv);
1273         intel_hpd_init(dev_priv);
1274
1275         /* MST sideband requires HPD interrupts enabled */
1276         intel_dp_mst_resume(dev_priv);
1277         intel_display_resume(dev);
1278
1279         intel_hpd_poll_disable(dev_priv);
1280         if (HAS_DISPLAY(dev_priv))
1281                 drm_kms_helper_poll_enable(dev);
1282
1283         intel_opregion_resume(dev_priv);
1284
1285         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1286
1287         intel_power_domains_enable(dev_priv);
1288
1289         intel_gvt_resume(dev_priv);
1290
1291         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1292
1293         return 0;
1294 }
1295
1296 static int i915_drm_resume_early(struct drm_device *dev)
1297 {
1298         struct drm_i915_private *dev_priv = to_i915(dev);
1299         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1300         int ret;
1301
1302         /*
1303          * We have a resume ordering issue with the snd-hda driver also
1304          * requiring our device to be power up. Due to the lack of a
1305          * parent/child relationship we currently solve this with an early
1306          * resume hook.
1307          *
1308          * FIXME: This should be solved with a special hdmi sink device or
1309          * similar so that power domains can be employed.
1310          */
1311
1312         /*
1313          * Note that we need to set the power state explicitly, since we
1314          * powered off the device during freeze and the PCI core won't power
1315          * it back up for us during thaw. Powering off the device during
1316          * freeze is not a hard requirement though, and during the
1317          * suspend/resume phases the PCI core makes sure we get here with the
1318          * device powered on. So in case we change our freeze logic and keep
1319          * the device powered we can also remove the following set power state
1320          * call.
1321          */
1322         ret = pci_set_power_state(pdev, PCI_D0);
1323         if (ret) {
1324                 drm_err(&dev_priv->drm,
1325                         "failed to set PCI D0 power state (%d)\n", ret);
1326                 return ret;
1327         }
1328
1329         /*
1330          * Note that pci_enable_device() first enables any parent bridge
1331          * device and only then sets the power state for this device. The
1332          * bridge enabling is a nop though, since bridge devices are resumed
1333          * first. The order of enabling power and enabling the device is
1334          * imposed by the PCI core as described above, so here we preserve the
1335          * same order for the freeze/thaw phases.
1336          *
1337          * TODO: eventually we should remove pci_disable_device() /
1338          * pci_enable_enable_device() from suspend/resume. Due to how they
1339          * depend on the device enable refcount we can't anyway depend on them
1340          * disabling/enabling the device.
1341          */
1342         if (pci_enable_device(pdev))
1343                 return -EIO;
1344
1345         pci_set_master(pdev);
1346
1347         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1348
1349         ret = vlv_resume_prepare(dev_priv, false);
1350         if (ret)
1351                 drm_err(&dev_priv->drm,
1352                         "Resume prepare failed: %d, continuing anyway\n", ret);
1353
1354         intel_uncore_resume_early(&dev_priv->uncore);
1355
1356         intel_gt_check_and_clear_faults(&dev_priv->gt);
1357
1358         intel_display_power_resume_early(dev_priv);
1359
1360         intel_power_domains_resume(dev_priv);
1361
1362         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1363
1364         return ret;
1365 }
1366
1367 int i915_resume_switcheroo(struct drm_i915_private *i915)
1368 {
1369         int ret;
1370
1371         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1372                 return 0;
1373
1374         ret = i915_drm_resume_early(&i915->drm);
1375         if (ret)
1376                 return ret;
1377
1378         return i915_drm_resume(&i915->drm);
1379 }
1380
1381 static int i915_pm_prepare(struct device *kdev)
1382 {
1383         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1384
1385         if (!i915) {
1386                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1387                 return -ENODEV;
1388         }
1389
1390         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1391                 return 0;
1392
1393         return i915_drm_prepare(&i915->drm);
1394 }
1395
1396 static int i915_pm_suspend(struct device *kdev)
1397 {
1398         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1399
1400         if (!i915) {
1401                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1402                 return -ENODEV;
1403         }
1404
1405         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1406                 return 0;
1407
1408         return i915_drm_suspend(&i915->drm);
1409 }
1410
1411 static int i915_pm_suspend_late(struct device *kdev)
1412 {
1413         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1414
1415         /*
1416          * We have a suspend ordering issue with the snd-hda driver also
1417          * requiring our device to be power up. Due to the lack of a
1418          * parent/child relationship we currently solve this with an late
1419          * suspend hook.
1420          *
1421          * FIXME: This should be solved with a special hdmi sink device or
1422          * similar so that power domains can be employed.
1423          */
1424         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1425                 return 0;
1426
1427         return i915_drm_suspend_late(&i915->drm, false);
1428 }
1429
1430 static int i915_pm_poweroff_late(struct device *kdev)
1431 {
1432         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1433
1434         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1435                 return 0;
1436
1437         return i915_drm_suspend_late(&i915->drm, true);
1438 }
1439
1440 static int i915_pm_resume_early(struct device *kdev)
1441 {
1442         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1443
1444         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1445                 return 0;
1446
1447         return i915_drm_resume_early(&i915->drm);
1448 }
1449
1450 static int i915_pm_resume(struct device *kdev)
1451 {
1452         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1453
1454         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1455                 return 0;
1456
1457         return i915_drm_resume(&i915->drm);
1458 }
1459
1460 /* freeze: before creating the hibernation_image */
1461 static int i915_pm_freeze(struct device *kdev)
1462 {
1463         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1464         int ret;
1465
1466         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1467                 ret = i915_drm_suspend(&i915->drm);
1468                 if (ret)
1469                         return ret;
1470         }
1471
1472         ret = i915_gem_freeze(i915);
1473         if (ret)
1474                 return ret;
1475
1476         return 0;
1477 }
1478
1479 static int i915_pm_freeze_late(struct device *kdev)
1480 {
1481         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1482         int ret;
1483
1484         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1485                 ret = i915_drm_suspend_late(&i915->drm, true);
1486                 if (ret)
1487                         return ret;
1488         }
1489
1490         ret = i915_gem_freeze_late(i915);
1491         if (ret)
1492                 return ret;
1493
1494         return 0;
1495 }
1496
1497 /* thaw: called after creating the hibernation image, but before turning off. */
1498 static int i915_pm_thaw_early(struct device *kdev)
1499 {
1500         return i915_pm_resume_early(kdev);
1501 }
1502
1503 static int i915_pm_thaw(struct device *kdev)
1504 {
1505         return i915_pm_resume(kdev);
1506 }
1507
1508 /* restore: called after loading the hibernation image. */
1509 static int i915_pm_restore_early(struct device *kdev)
1510 {
1511         return i915_pm_resume_early(kdev);
1512 }
1513
1514 static int i915_pm_restore(struct device *kdev)
1515 {
1516         return i915_pm_resume(kdev);
1517 }
1518
1519 static int intel_runtime_suspend(struct device *kdev)
1520 {
1521         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1522         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1523         int ret;
1524
1525         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1526                 return -ENODEV;
1527
1528         drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1529
1530         disable_rpm_wakeref_asserts(rpm);
1531
1532         /*
1533          * We are safe here against re-faults, since the fault handler takes
1534          * an RPM reference.
1535          */
1536         i915_gem_runtime_suspend(dev_priv);
1537
1538         intel_gt_runtime_suspend(&dev_priv->gt);
1539
1540         intel_runtime_pm_disable_interrupts(dev_priv);
1541
1542         intel_uncore_suspend(&dev_priv->uncore);
1543
1544         intel_display_power_suspend(dev_priv);
1545
1546         ret = vlv_suspend_complete(dev_priv);
1547         if (ret) {
1548                 drm_err(&dev_priv->drm,
1549                         "Runtime suspend failed, disabling it (%d)\n", ret);
1550                 intel_uncore_runtime_resume(&dev_priv->uncore);
1551
1552                 intel_runtime_pm_enable_interrupts(dev_priv);
1553
1554                 intel_gt_runtime_resume(&dev_priv->gt);
1555
1556                 enable_rpm_wakeref_asserts(rpm);
1557
1558                 return ret;
1559         }
1560
1561         enable_rpm_wakeref_asserts(rpm);
1562         intel_runtime_pm_driver_release(rpm);
1563
1564         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1565                 drm_err(&dev_priv->drm,
1566                         "Unclaimed access detected prior to suspending\n");
1567
1568         rpm->suspended = true;
1569
1570         /*
1571          * FIXME: We really should find a document that references the arguments
1572          * used below!
1573          */
1574         if (IS_BROADWELL(dev_priv)) {
1575                 /*
1576                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1577                  * being detected, and the call we do at intel_runtime_resume()
1578                  * won't be able to restore them. Since PCI_D3hot matches the
1579                  * actual specification and appears to be working, use it.
1580                  */
1581                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1582         } else {
1583                 /*
1584                  * current versions of firmware which depend on this opregion
1585                  * notification have repurposed the D1 definition to mean
1586                  * "runtime suspended" vs. what you would normally expect (D3)
1587                  * to distinguish it from notifications that might be sent via
1588                  * the suspend path.
1589                  */
1590                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1591         }
1592
1593         assert_forcewakes_inactive(&dev_priv->uncore);
1594
1595         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1596                 intel_hpd_poll_enable(dev_priv);
1597
1598         drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1599         return 0;
1600 }
1601
1602 static int intel_runtime_resume(struct device *kdev)
1603 {
1604         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1605         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1606         int ret;
1607
1608         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1609                 return -ENODEV;
1610
1611         drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1612
1613         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1614         disable_rpm_wakeref_asserts(rpm);
1615
1616         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1617         rpm->suspended = false;
1618         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1619                 drm_dbg(&dev_priv->drm,
1620                         "Unclaimed access during suspend, bios?\n");
1621
1622         intel_display_power_resume(dev_priv);
1623
1624         ret = vlv_resume_prepare(dev_priv, true);
1625
1626         intel_uncore_runtime_resume(&dev_priv->uncore);
1627
1628         intel_runtime_pm_enable_interrupts(dev_priv);
1629
1630         /*
1631          * No point of rolling back things in case of an error, as the best
1632          * we can do is to hope that things will still work (and disable RPM).
1633          */
1634         intel_gt_runtime_resume(&dev_priv->gt);
1635
1636         /*
1637          * On VLV/CHV display interrupts are part of the display
1638          * power well, so hpd is reinitialized from there. For
1639          * everyone else do it here.
1640          */
1641         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1642                 intel_hpd_init(dev_priv);
1643                 intel_hpd_poll_disable(dev_priv);
1644         }
1645
1646         intel_enable_ipc(dev_priv);
1647
1648         enable_rpm_wakeref_asserts(rpm);
1649
1650         if (ret)
1651                 drm_err(&dev_priv->drm,
1652                         "Runtime resume failed, disabling it (%d)\n", ret);
1653         else
1654                 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1655
1656         return ret;
1657 }
1658
1659 const struct dev_pm_ops i915_pm_ops = {
1660         /*
1661          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1662          * PMSG_RESUME]
1663          */
1664         .prepare = i915_pm_prepare,
1665         .suspend = i915_pm_suspend,
1666         .suspend_late = i915_pm_suspend_late,
1667         .resume_early = i915_pm_resume_early,
1668         .resume = i915_pm_resume,
1669
1670         /*
1671          * S4 event handlers
1672          * @freeze, @freeze_late    : called (1) before creating the
1673          *                            hibernation image [PMSG_FREEZE] and
1674          *                            (2) after rebooting, before restoring
1675          *                            the image [PMSG_QUIESCE]
1676          * @thaw, @thaw_early       : called (1) after creating the hibernation
1677          *                            image, before writing it [PMSG_THAW]
1678          *                            and (2) after failing to create or
1679          *                            restore the image [PMSG_RECOVER]
1680          * @poweroff, @poweroff_late: called after writing the hibernation
1681          *                            image, before rebooting [PMSG_HIBERNATE]
1682          * @restore, @restore_early : called after rebooting and restoring the
1683          *                            hibernation image [PMSG_RESTORE]
1684          */
1685         .freeze = i915_pm_freeze,
1686         .freeze_late = i915_pm_freeze_late,
1687         .thaw_early = i915_pm_thaw_early,
1688         .thaw = i915_pm_thaw,
1689         .poweroff = i915_pm_suspend,
1690         .poweroff_late = i915_pm_poweroff_late,
1691         .restore_early = i915_pm_restore_early,
1692         .restore = i915_pm_restore,
1693
1694         /* S0ix (via runtime suspend) event handlers */
1695         .runtime_suspend = intel_runtime_suspend,
1696         .runtime_resume = intel_runtime_resume,
1697 };
1698
1699 static const struct file_operations i915_driver_fops = {
1700         .owner = THIS_MODULE,
1701         .open = drm_open,
1702         .release = drm_release_noglobal,
1703         .unlocked_ioctl = drm_ioctl,
1704         .mmap = i915_gem_mmap,
1705         .poll = drm_poll,
1706         .read = drm_read,
1707         .compat_ioctl = i915_ioc32_compat_ioctl,
1708         .llseek = noop_llseek,
1709 };
1710
1711 static int
1712 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1713                           struct drm_file *file)
1714 {
1715         return -ENODEV;
1716 }
1717
1718 static const struct drm_ioctl_desc i915_ioctls[] = {
1719         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1720         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1721         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1722         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1724         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1725         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1726         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1727         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1728         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1729         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1730         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1731         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1733         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1734         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1735         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1758         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1759         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1760         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1761         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1762         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1763         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1772         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1773         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1774         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1775         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1778 };
1779
1780 static const struct drm_driver driver = {
1781         /* Don't use MTRRs here; the Xserver or userspace app should
1782          * deal with them for Intel hardware.
1783          */
1784         .driver_features =
1785             DRIVER_GEM |
1786             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1787             DRIVER_SYNCOBJ_TIMELINE,
1788         .release = i915_driver_release,
1789         .open = i915_driver_open,
1790         .lastclose = i915_driver_lastclose,
1791         .postclose = i915_driver_postclose,
1792
1793         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1794         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1795         .gem_prime_import = i915_gem_prime_import,
1796
1797         .dumb_create = i915_gem_dumb_create,
1798         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1799
1800         .ioctls = i915_ioctls,
1801         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1802         .fops = &i915_driver_fops,
1803         .name = DRIVER_NAME,
1804         .desc = DRIVER_DESC,
1805         .date = DRIVER_DATE,
1806         .major = DRIVER_MAJOR,
1807         .minor = DRIVER_MINOR,
1808         .patchlevel = DRIVER_PATCHLEVEL,
1809 };