drivers/gpu/drm/i915/display/skl_universal_plane.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include <drm/drm_atomic_helper.h>
   7 #include <drm/drm_blend.h>
   8 #include <drm/drm_damage_helper.h>
   9 #include <drm/drm_fourcc.h>
  10
  11 #include "i915_drv.h"
  12 #include "i915_reg.h"
  13 #include "intel_atomic_plane.h"
  14 #include "intel_de.h"
  15 #include "intel_display_irq.h"
  16 #include "intel_display_types.h"
  17 #include "intel_fb.h"
  18 #include "intel_fbc.h"
  19 #include "intel_frontbuffer.h"
  20 #include "intel_psr.h"
  21 #include "skl_scaler.h"
  22 #include "skl_universal_plane.h"
  23 #include "skl_watermark.h"
  24 #include "gt/intel_gt.h"
  25 #include "pxp/intel_pxp.h"
  26
  27 static const u32 skl_plane_formats[] = {
  28         DRM_FORMAT_C8,
  29         DRM_FORMAT_RGB565,
  30         DRM_FORMAT_XRGB8888,
  31         DRM_FORMAT_XBGR8888,
  32         DRM_FORMAT_ARGB8888,
  33         DRM_FORMAT_ABGR8888,
  34         DRM_FORMAT_XRGB2101010,
  35         DRM_FORMAT_XBGR2101010,
  36         DRM_FORMAT_XRGB16161616F,
  37         DRM_FORMAT_XBGR16161616F,
  38         DRM_FORMAT_YUYV,
  39         DRM_FORMAT_YVYU,
  40         DRM_FORMAT_UYVY,
  41         DRM_FORMAT_VYUY,
  42         DRM_FORMAT_XYUV8888,
  43 };
  44
  45 static const u32 skl_planar_formats[] = {
  46         DRM_FORMAT_C8,
  47         DRM_FORMAT_RGB565,
  48         DRM_FORMAT_XRGB8888,
  49         DRM_FORMAT_XBGR8888,
  50         DRM_FORMAT_ARGB8888,
  51         DRM_FORMAT_ABGR8888,
  52         DRM_FORMAT_XRGB2101010,
  53         DRM_FORMAT_XBGR2101010,
  54         DRM_FORMAT_XRGB16161616F,
  55         DRM_FORMAT_XBGR16161616F,
  56         DRM_FORMAT_YUYV,
  57         DRM_FORMAT_YVYU,
  58         DRM_FORMAT_UYVY,
  59         DRM_FORMAT_VYUY,
  60         DRM_FORMAT_NV12,
  61         DRM_FORMAT_XYUV8888,
  62 };
  63
  64 static const u32 glk_planar_formats[] = {
  65         DRM_FORMAT_C8,
  66         DRM_FORMAT_RGB565,
  67         DRM_FORMAT_XRGB8888,
  68         DRM_FORMAT_XBGR8888,
  69         DRM_FORMAT_ARGB8888,
  70         DRM_FORMAT_ABGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73         DRM_FORMAT_XRGB16161616F,
  74         DRM_FORMAT_XBGR16161616F,
  75         DRM_FORMAT_YUYV,
  76         DRM_FORMAT_YVYU,
  77         DRM_FORMAT_UYVY,
  78         DRM_FORMAT_VYUY,
  79         DRM_FORMAT_NV12,
  80         DRM_FORMAT_XYUV8888,
  81         DRM_FORMAT_P010,
  82         DRM_FORMAT_P012,
  83         DRM_FORMAT_P016,
  84 };
  85
  86 static const u32 icl_sdr_y_plane_formats[] = {
  87         DRM_FORMAT_C8,
  88         DRM_FORMAT_RGB565,
  89         DRM_FORMAT_XRGB8888,
  90         DRM_FORMAT_XBGR8888,
  91         DRM_FORMAT_ARGB8888,
  92         DRM_FORMAT_ABGR8888,
  93         DRM_FORMAT_XRGB2101010,
  94         DRM_FORMAT_XBGR2101010,
  95         DRM_FORMAT_ARGB2101010,
  96         DRM_FORMAT_ABGR2101010,
  97         DRM_FORMAT_YUYV,
  98         DRM_FORMAT_YVYU,
  99         DRM_FORMAT_UYVY,
 100         DRM_FORMAT_VYUY,
 101         DRM_FORMAT_Y210,
 102         DRM_FORMAT_Y212,
 103         DRM_FORMAT_Y216,
 104         DRM_FORMAT_XYUV8888,
 105         DRM_FORMAT_XVYU2101010,
 106         DRM_FORMAT_XVYU12_16161616,
 107         DRM_FORMAT_XVYU16161616,
 108 };
 109
 110 static const u32 icl_sdr_uv_plane_formats[] = {
 111         DRM_FORMAT_C8,
 112         DRM_FORMAT_RGB565,
 113         DRM_FORMAT_XRGB8888,
 114         DRM_FORMAT_XBGR8888,
 115         DRM_FORMAT_ARGB8888,
 116         DRM_FORMAT_ABGR8888,
 117         DRM_FORMAT_XRGB2101010,
 118         DRM_FORMAT_XBGR2101010,
 119         DRM_FORMAT_ARGB2101010,
 120         DRM_FORMAT_ABGR2101010,
 121         DRM_FORMAT_YUYV,
 122         DRM_FORMAT_YVYU,
 123         DRM_FORMAT_UYVY,
 124         DRM_FORMAT_VYUY,
 125         DRM_FORMAT_NV12,
 126         DRM_FORMAT_P010,
 127         DRM_FORMAT_P012,
 128         DRM_FORMAT_P016,
 129         DRM_FORMAT_Y210,
 130         DRM_FORMAT_Y212,
 131         DRM_FORMAT_Y216,
 132         DRM_FORMAT_XYUV8888,
 133         DRM_FORMAT_XVYU2101010,
 134         DRM_FORMAT_XVYU12_16161616,
 135         DRM_FORMAT_XVYU16161616,
 136 };
 137
 138 static const u32 icl_hdr_plane_formats[] = {
 139         DRM_FORMAT_C8,
 140         DRM_FORMAT_RGB565,
 141         DRM_FORMAT_XRGB8888,
 142         DRM_FORMAT_XBGR8888,
 143         DRM_FORMAT_ARGB8888,
 144         DRM_FORMAT_ABGR8888,
 145         DRM_FORMAT_XRGB2101010,
 146         DRM_FORMAT_XBGR2101010,
 147         DRM_FORMAT_ARGB2101010,
 148         DRM_FORMAT_ABGR2101010,
 149         DRM_FORMAT_XRGB16161616F,
 150         DRM_FORMAT_XBGR16161616F,
 151         DRM_FORMAT_ARGB16161616F,
 152         DRM_FORMAT_ABGR16161616F,
 153         DRM_FORMAT_YUYV,
 154         DRM_FORMAT_YVYU,
 155         DRM_FORMAT_UYVY,
 156         DRM_FORMAT_VYUY,
 157         DRM_FORMAT_NV12,
 158         DRM_FORMAT_P010,
 159         DRM_FORMAT_P012,
 160         DRM_FORMAT_P016,
 161         DRM_FORMAT_Y210,
 162         DRM_FORMAT_Y212,
 163         DRM_FORMAT_Y216,
 164         DRM_FORMAT_XYUV8888,
 165         DRM_FORMAT_XVYU2101010,
 166         DRM_FORMAT_XVYU12_16161616,
 167         DRM_FORMAT_XVYU16161616,
 168 };
 169
 170 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 171 {
 172         switch (format) {
 173         case PLANE_CTL_FORMAT_RGB_565:
 174                 return DRM_FORMAT_RGB565;
 175         case PLANE_CTL_FORMAT_NV12:
 176                 return DRM_FORMAT_NV12;
 177         case PLANE_CTL_FORMAT_XYUV:
 178                 return DRM_FORMAT_XYUV8888;
 179         case PLANE_CTL_FORMAT_P010:
 180                 return DRM_FORMAT_P010;
 181         case PLANE_CTL_FORMAT_P012:
 182                 return DRM_FORMAT_P012;
 183         case PLANE_CTL_FORMAT_P016:
 184                 return DRM_FORMAT_P016;
 185         case PLANE_CTL_FORMAT_Y210:
 186                 return DRM_FORMAT_Y210;
 187         case PLANE_CTL_FORMAT_Y212:
 188                 return DRM_FORMAT_Y212;
 189         case PLANE_CTL_FORMAT_Y216:
 190                 return DRM_FORMAT_Y216;
 191         case PLANE_CTL_FORMAT_Y410:
 192                 return DRM_FORMAT_XVYU2101010;
 193         case PLANE_CTL_FORMAT_Y412:
 194                 return DRM_FORMAT_XVYU12_16161616;
 195         case PLANE_CTL_FORMAT_Y416:
 196                 return DRM_FORMAT_XVYU16161616;
 197         default:
 198         case PLANE_CTL_FORMAT_XRGB_8888:
 199                 if (rgb_order) {
 200                         if (alpha)
 201                                 return DRM_FORMAT_ABGR8888;
 202                         else
 203                                 return DRM_FORMAT_XBGR8888;
 204                 } else {
 205                         if (alpha)
 206                                 return DRM_FORMAT_ARGB8888;
 207                         else
 208                                 return DRM_FORMAT_XRGB8888;
 209                 }
 210         case PLANE_CTL_FORMAT_XRGB_2101010:
 211                 if (rgb_order) {
 212                         if (alpha)
 213                                 return DRM_FORMAT_ABGR2101010;
 214                         else
 215                                 return DRM_FORMAT_XBGR2101010;
 216                 } else {
 217                         if (alpha)
 218                                 return DRM_FORMAT_ARGB2101010;
 219                         else
 220                                 return DRM_FORMAT_XRGB2101010;
 221                 }
 222         case PLANE_CTL_FORMAT_XRGB_16161616F:
 223                 if (rgb_order) {
 224                         if (alpha)
 225                                 return DRM_FORMAT_ABGR16161616F;
 226                         else
 227                                 return DRM_FORMAT_XBGR16161616F;
 228                 } else {
 229                         if (alpha)
 230                                 return DRM_FORMAT_ARGB16161616F;
 231                         else
 232                                 return DRM_FORMAT_XRGB16161616F;
 233                 }
 234         }
 235 }
 236
 237 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
 238 {
 239         if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
 240                 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
 241         else
 242                 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
 243 }
 244
 245 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
 246                          enum plane_id plane_id)
 247 {
 248         return DISPLAY_VER(dev_priv) >= 11 &&
 249                 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
 250 }
 251
 252 u8 icl_hdr_plane_mask(void)
 253 {
 254         return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
 255 }
 256
 257 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
 258 {
 259         return DISPLAY_VER(dev_priv) >= 11 &&
 260                 icl_hdr_plane_mask() & BIT(plane_id);
 261 }
 262
 263 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 264                                const struct intel_plane_state *plane_state)
 265 {
 266         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 267
 268         /* two pixels per clock */
 269         return DIV_ROUND_UP(pixel_rate, 2);
 270 }
 271
 272 static void
 273 glk_plane_ratio(const struct intel_plane_state *plane_state,
 274                 unsigned int *num, unsigned int *den)
 275 {
 276         const struct drm_framebuffer *fb = plane_state->hw.fb;
 277
 278         if (fb->format->cpp[0] == 8) {
 279                 *num = 10;
 280                 *den = 8;
 281         } else {
 282                 *num = 1;
 283                 *den = 1;
 284         }
 285 }
 286
 287 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 288                                const struct intel_plane_state *plane_state)
 289 {
 290         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 291         unsigned int num, den;
 292
 293         glk_plane_ratio(plane_state, &num, &den);
 294
 295         /* two pixels per clock */
 296         return DIV_ROUND_UP(pixel_rate * num, 2 * den);
 297 }
 298
 299 static void
 300 skl_plane_ratio(const struct intel_plane_state *plane_state,
 301                 unsigned int *num, unsigned int *den)
 302 {
 303         const struct drm_framebuffer *fb = plane_state->hw.fb;
 304
 305         if (fb->format->cpp[0] == 8) {
 306                 *num = 9;
 307                 *den = 8;
 308         } else {
 309                 *num = 1;
 310                 *den = 1;
 311         }
 312 }
 313
 314 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
 315                                const struct intel_plane_state *plane_state)
 316 {
 317         unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
 318         unsigned int num, den;
 319
 320         skl_plane_ratio(plane_state, &num, &den);
 321
 322         return DIV_ROUND_UP(pixel_rate * num, den);
 323 }
 324
 325 static int skl_plane_max_width(const struct drm_framebuffer *fb,
 326                                int color_plane,
 327                                unsigned int rotation)
 328 {
 329         int cpp = fb->format->cpp[color_plane];
 330
 331         switch (fb->modifier) {
 332         case DRM_FORMAT_MOD_LINEAR:
 333         case I915_FORMAT_MOD_X_TILED:
 334                 /*
 335                  * Validated limit is 4k, but has 5k should
 336                  * work apart from the following features:
 337                  * - Ytile (already limited to 4k)
 338                  * - FP16 (already limited to 4k)
 339                  * - render compression (already limited to 4k)
 340                  * - KVMR sprite and cursor (don't care)
 341                  * - horizontal panning (TODO verify this)
 342                  * - pipe and plane scaling (TODO verify this)
 343                  */
 344                 if (cpp == 8)
 345                         return 4096;
 346                 else
 347                         return 5120;
 348         case I915_FORMAT_MOD_Y_TILED_CCS:
 349         case I915_FORMAT_MOD_Yf_TILED_CCS:
 350         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 351                 /* FIXME AUX plane? */
 352         case I915_FORMAT_MOD_Y_TILED:
 353         case I915_FORMAT_MOD_Yf_TILED:
 354                 if (cpp == 8)
 355                         return 2048;
 356                 else
 357                         return 4096;
 358         default:
 359                 MISSING_CASE(fb->modifier);
 360                 return 2048;
 361         }
 362 }
 363
 364 static int glk_plane_max_width(const struct drm_framebuffer *fb,
 365                                int color_plane,
 366                                unsigned int rotation)
 367 {
 368         int cpp = fb->format->cpp[color_plane];
 369
 370         switch (fb->modifier) {
 371         case DRM_FORMAT_MOD_LINEAR:
 372         case I915_FORMAT_MOD_X_TILED:
 373                 if (cpp == 8)
 374                         return 4096;
 375                 else
 376                         return 5120;
 377         case I915_FORMAT_MOD_Y_TILED_CCS:
 378         case I915_FORMAT_MOD_Yf_TILED_CCS:
 379                 /* FIXME AUX plane? */
 380         case I915_FORMAT_MOD_Y_TILED:
 381         case I915_FORMAT_MOD_Yf_TILED:
 382                 if (cpp == 8)
 383                         return 2048;
 384                 else
 385                         return 5120;
 386         default:
 387                 MISSING_CASE(fb->modifier);
 388                 return 2048;
 389         }
 390 }
 391
 392 static int icl_plane_min_width(const struct drm_framebuffer *fb,
 393                                int color_plane,
 394                                unsigned int rotation)
 395 {
 396         /* Wa_14011264657, Wa_14011050563: gen11+ */
 397         switch (fb->format->format) {
 398         case DRM_FORMAT_C8:
 399                 return 18;
 400         case DRM_FORMAT_RGB565:
 401                 return 10;
 402         case DRM_FORMAT_XRGB8888:
 403         case DRM_FORMAT_XBGR8888:
 404         case DRM_FORMAT_ARGB8888:
 405         case DRM_FORMAT_ABGR8888:
 406         case DRM_FORMAT_XRGB2101010:
 407         case DRM_FORMAT_XBGR2101010:
 408         case DRM_FORMAT_ARGB2101010:
 409         case DRM_FORMAT_ABGR2101010:
 410         case DRM_FORMAT_XVYU2101010:
 411         case DRM_FORMAT_Y212:
 412         case DRM_FORMAT_Y216:
 413                 return 6;
 414         case DRM_FORMAT_NV12:
 415                 return 20;
 416         case DRM_FORMAT_P010:
 417         case DRM_FORMAT_P012:
 418         case DRM_FORMAT_P016:
 419                 return 12;
 420         case DRM_FORMAT_XRGB16161616F:
 421         case DRM_FORMAT_XBGR16161616F:
 422         case DRM_FORMAT_ARGB16161616F:
 423         case DRM_FORMAT_ABGR16161616F:
 424         case DRM_FORMAT_XVYU12_16161616:
 425         case DRM_FORMAT_XVYU16161616:
 426                 return 4;
 427         default:
 428                 return 1;
 429         }
 430 }
 431
 432 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
 433                                    int color_plane,
 434                                    unsigned int rotation)
 435 {
 436         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 437                 return 4096;
 438         else
 439                 return 5120;
 440 }
 441
 442 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
 443                                    int color_plane,
 444                                    unsigned int rotation)
 445 {
 446         return 5120;
 447 }
 448
 449 static int skl_plane_max_height(const struct drm_framebuffer *fb,
 450                                 int color_plane,
 451                                 unsigned int rotation)
 452 {
 453         return 4096;
 454 }
 455
 456 static int icl_plane_max_height(const struct drm_framebuffer *fb,
 457                                 int color_plane,
 458                                 unsigned int rotation)
 459 {
 460         return 4320;
 461 }
 462
 463 static unsigned int
 464 skl_plane_max_stride(struct intel_plane *plane,
 465                      u32 pixel_format, u64 modifier,
 466                      unsigned int rotation)
 467 {
 468         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 469         const struct drm_format_info *info = drm_format_info(pixel_format);
 470         int cpp = info->cpp[0];
 471         int max_horizontal_pixels = 8192;
 472         int max_stride_bytes;
 473
 474         if (DISPLAY_VER(i915) >= 13) {
 475                 /*
 476                  * The stride in bytes must not exceed of the size
 477                  * of 128K bytes. For pixel formats of 64bpp will allow
 478                  * for a 16K pixel surface.
 479                  */
 480                 max_stride_bytes = 131072;
 481                 if (cpp == 8)
 482                         max_horizontal_pixels = 16384;
 483                 else
 484                         max_horizontal_pixels = 65536;
 485         } else {
 486                 /*
 487                  * "The stride in bytes must not exceed the
 488                  * of the size of 8K pixels and 32K bytes."
 489                  */
 490                 max_stride_bytes = 32768;
 491         }
 492
 493         if (drm_rotation_90_or_270(rotation))
 494                 return min(max_horizontal_pixels, max_stride_bytes / cpp);
 495         else
 496                 return min(max_horizontal_pixels * cpp, max_stride_bytes);
 497 }
 498
 499
 500 /* Preoffset values for YUV to RGB Conversion */
 501 #define PREOFF_YUV_TO_RGB_HI            0x1800
 502 #define PREOFF_YUV_TO_RGB_ME            0x0000
 503 #define PREOFF_YUV_TO_RGB_LO            0x1800
 504
 505 #define  ROFF(x)          (((x) & 0xffff) << 16)
 506 #define  GOFF(x)          (((x) & 0xffff) << 0)
 507 #define  BOFF(x)          (((x) & 0xffff) << 16)
 508
 509 /*
 510  * Programs the input color space conversion stage for ICL HDR planes.
 511  * Note that it is assumed that this stage always happens after YUV
 512  * range correction. Thus, the input to this stage is assumed to be
 513  * in full-range YCbCr.
 514  */
 515 static void
 516 icl_program_input_csc(struct intel_plane *plane,
 517                       const struct intel_crtc_state *crtc_state,
 518                       const struct intel_plane_state *plane_state)
 519 {
 520         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 521         enum pipe pipe = plane->pipe;
 522         enum plane_id plane_id = plane->id;
 523
 524         static const u16 input_csc_matrix[][9] = {
 525                 /*
 526                  * BT.601 full range YCbCr -> full range RGB
 527                  * The matrix required is :
 528                  * [1.000, 0.000, 1.371,
 529                  *  1.000, -0.336, -0.698,
 530                  *  1.000, 1.732, 0.0000]
 531                  */
 532                 [DRM_COLOR_YCBCR_BT601] = {
 533                         0x7AF8, 0x7800, 0x0,
 534                         0x8B28, 0x7800, 0x9AC0,
 535                         0x0, 0x7800, 0x7DD8,
 536                 },
 537                 /*
 538                  * BT.709 full range YCbCr -> full range RGB
 539                  * The matrix required is :
 540                  * [1.000, 0.000, 1.574,
 541                  *  1.000, -0.187, -0.468,
 542                  *  1.000, 1.855, 0.0000]
 543                  */
 544                 [DRM_COLOR_YCBCR_BT709] = {
 545                         0x7C98, 0x7800, 0x0,
 546                         0x9EF8, 0x7800, 0xAC00,
 547                         0x0, 0x7800,  0x7ED8,
 548                 },
 549                 /*
 550                  * BT.2020 full range YCbCr -> full range RGB
 551                  * The matrix required is :
 552                  * [1.000, 0.000, 1.474,
 553                  *  1.000, -0.1645, -0.5713,
 554                  *  1.000, 1.8814, 0.0000]
 555                  */
 556                 [DRM_COLOR_YCBCR_BT2020] = {
 557                         0x7BC8, 0x7800, 0x0,
 558                         0x8928, 0x7800, 0xAA88,
 559                         0x0, 0x7800, 0x7F10,
 560                 },
 561         };
 562         const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
 563
 564         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
 565                           ROFF(csc[0]) | GOFF(csc[1]));
 566         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
 567                           BOFF(csc[2]));
 568         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
 569                           ROFF(csc[3]) | GOFF(csc[4]));
 570         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
 571                           BOFF(csc[5]));
 572         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
 573                           ROFF(csc[6]) | GOFF(csc[7]));
 574         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
 575                           BOFF(csc[8]));
 576
 577         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
 578                           PREOFF_YUV_TO_RGB_HI);
 579         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
 580                           PREOFF_YUV_TO_RGB_ME);
 581         intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
 582                           PREOFF_YUV_TO_RGB_LO);
 583         intel_de_write_fw(dev_priv,
 584                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
 585         intel_de_write_fw(dev_priv,
 586                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
 587         intel_de_write_fw(dev_priv,
 588                           PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 589 }
 590
 591 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
 592                                           int color_plane, unsigned int rotation)
 593 {
 594         /*
 595          * The stride is either expressed as a multiple of 64 bytes chunks for
 596          * linear buffers or in number of tiles for tiled buffers.
 597          */
 598         if (is_surface_linear(fb, color_plane))
 599                 return 64;
 600         else if (drm_rotation_90_or_270(rotation))
 601                 return intel_tile_height(fb, color_plane);
 602         else
 603                 return intel_tile_width_bytes(fb, color_plane);
 604 }
 605
 606 static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 607                             int color_plane)
 608 {
 609         const struct drm_framebuffer *fb = plane_state->hw.fb;
 610         unsigned int rotation = plane_state->hw.rotation;
 611         u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;
 612
 613         if (color_plane >= fb->format->num_planes)
 614                 return 0;
 615
 616         return stride / skl_plane_stride_mult(fb, color_plane, rotation);
 617 }
 618
 619 static void
 620 skl_plane_disable_arm(struct intel_plane *plane,
 621                       const struct intel_crtc_state *crtc_state)
 622 {
 623         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 624         enum plane_id plane_id = plane->id;
 625         enum pipe pipe = plane->pipe;
 626
 627         skl_write_plane_wm(plane, crtc_state);
 628
 629         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
 630         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
 631 }
 632
 633 static void
 634 icl_plane_disable_arm(struct intel_plane *plane,
 635                       const struct intel_crtc_state *crtc_state)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 638         enum plane_id plane_id = plane->id;
 639         enum pipe pipe = plane->pipe;
 640
 641         if (icl_is_hdr_plane(dev_priv, plane_id))
 642                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
 643
 644         skl_write_plane_wm(plane, crtc_state);
 645
 646         intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);
 647         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
 648         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
 649 }
 650
 651 static bool
 652 skl_plane_get_hw_state(struct intel_plane *plane,
 653                        enum pipe *pipe)
 654 {
 655         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 656         enum intel_display_power_domain power_domain;
 657         enum plane_id plane_id = plane->id;
 658         intel_wakeref_t wakeref;
 659         bool ret;
 660
 661         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 662         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 663         if (!wakeref)
 664                 return false;
 665
 666         ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
 667
 668         *pipe = plane->pipe;
 669
 670         intel_display_power_put(dev_priv, power_domain, wakeref);
 671
 672         return ret;
 673 }
 674
 675 static u32 skl_plane_ctl_format(u32 pixel_format)
 676 {
 677         switch (pixel_format) {
 678         case DRM_FORMAT_C8:
 679                 return PLANE_CTL_FORMAT_INDEXED;
 680         case DRM_FORMAT_RGB565:
 681                 return PLANE_CTL_FORMAT_RGB_565;
 682         case DRM_FORMAT_XBGR8888:
 683         case DRM_FORMAT_ABGR8888:
 684                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
 685         case DRM_FORMAT_XRGB8888:
 686         case DRM_FORMAT_ARGB8888:
 687                 return PLANE_CTL_FORMAT_XRGB_8888;
 688         case DRM_FORMAT_XBGR2101010:
 689         case DRM_FORMAT_ABGR2101010:
 690                 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
 691         case DRM_FORMAT_XRGB2101010:
 692         case DRM_FORMAT_ARGB2101010:
 693                 return PLANE_CTL_FORMAT_XRGB_2101010;
 694         case DRM_FORMAT_XBGR16161616F:
 695         case DRM_FORMAT_ABGR16161616F:
 696                 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
 697         case DRM_FORMAT_XRGB16161616F:
 698         case DRM_FORMAT_ARGB16161616F:
 699                 return PLANE_CTL_FORMAT_XRGB_16161616F;
 700         case DRM_FORMAT_XYUV8888:
 701                 return PLANE_CTL_FORMAT_XYUV;
 702         case DRM_FORMAT_YUYV:
 703                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
 704         case DRM_FORMAT_YVYU:
 705                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
 706         case DRM_FORMAT_UYVY:
 707                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
 708         case DRM_FORMAT_VYUY:
 709                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
 710         case DRM_FORMAT_NV12:
 711                 return PLANE_CTL_FORMAT_NV12;
 712         case DRM_FORMAT_P010:
 713                 return PLANE_CTL_FORMAT_P010;
 714         case DRM_FORMAT_P012:
 715                 return PLANE_CTL_FORMAT_P012;
 716         case DRM_FORMAT_P016:
 717                 return PLANE_CTL_FORMAT_P016;
 718         case DRM_FORMAT_Y210:
 719                 return PLANE_CTL_FORMAT_Y210;
 720         case DRM_FORMAT_Y212:
 721                 return PLANE_CTL_FORMAT_Y212;
 722         case DRM_FORMAT_Y216:
 723                 return PLANE_CTL_FORMAT_Y216;
 724         case DRM_FORMAT_XVYU2101010:
 725                 return PLANE_CTL_FORMAT_Y410;
 726         case DRM_FORMAT_XVYU12_16161616:
 727                 return PLANE_CTL_FORMAT_Y412;
 728         case DRM_FORMAT_XVYU16161616:
 729                 return PLANE_CTL_FORMAT_Y416;
 730         default:
 731                 MISSING_CASE(pixel_format);
 732         }
 733
 734         return 0;
 735 }
 736
 737 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
 738 {
 739         if (!plane_state->hw.fb->format->has_alpha)
 740                 return PLANE_CTL_ALPHA_DISABLE;
 741
 742         switch (plane_state->hw.pixel_blend_mode) {
 743         case DRM_MODE_BLEND_PIXEL_NONE:
 744                 return PLANE_CTL_ALPHA_DISABLE;
 745         case DRM_MODE_BLEND_PREMULTI:
 746                 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
 747         case DRM_MODE_BLEND_COVERAGE:
 748                 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
 749         default:
 750                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 751                 return PLANE_CTL_ALPHA_DISABLE;
 752         }
 753 }
 754
 755 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
 756 {
 757         if (!plane_state->hw.fb->format->has_alpha)
 758                 return PLANE_COLOR_ALPHA_DISABLE;
 759
 760         switch (plane_state->hw.pixel_blend_mode) {
 761         case DRM_MODE_BLEND_PIXEL_NONE:
 762                 return PLANE_COLOR_ALPHA_DISABLE;
 763         case DRM_MODE_BLEND_PREMULTI:
 764                 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
 765         case DRM_MODE_BLEND_COVERAGE:
 766                 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
 767         default:
 768                 MISSING_CASE(plane_state->hw.pixel_blend_mode);
 769                 return PLANE_COLOR_ALPHA_DISABLE;
 770         }
 771 }
 772
 773 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 774 {
 775         switch (fb_modifier) {
 776         case DRM_FORMAT_MOD_LINEAR:
 777                 break;
 778         case I915_FORMAT_MOD_X_TILED:
 779                 return PLANE_CTL_TILED_X;
 780         case I915_FORMAT_MOD_Y_TILED:
 781                 return PLANE_CTL_TILED_Y;
 782         case I915_FORMAT_MOD_4_TILED:
 783                 return PLANE_CTL_TILED_4;
 784         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 785                 return PLANE_CTL_TILED_4 |
 786                         PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 787                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 788         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 789                 return PLANE_CTL_TILED_4 |
 790                         PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
 791                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 792         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 793                 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 794         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
 795                 return PLANE_CTL_TILED_4 |
 796                         PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 797                         PLANE_CTL_CLEAR_COLOR_DISABLE;
 798         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 799                 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 800         case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 801                 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 802         case I915_FORMAT_MOD_Y_TILED_CCS:
 803         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 804                 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 805         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 806                 return PLANE_CTL_TILED_Y |
 807                        PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
 808                        PLANE_CTL_CLEAR_COLOR_DISABLE;
 809         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 810                 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
 811         case I915_FORMAT_MOD_Yf_TILED:
 812                 return PLANE_CTL_TILED_YF;
 813         case I915_FORMAT_MOD_Yf_TILED_CCS:
 814                 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 815         default:
 816                 MISSING_CASE(fb_modifier);
 817         }
 818
 819         return 0;
 820 }
 821
 822 static u32 skl_plane_ctl_rotate(unsigned int rotate)
 823 {
 824         switch (rotate) {
 825         case DRM_MODE_ROTATE_0:
 826                 break;
 827         /*
 828          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
 829          * while i915 HW rotation is clockwise, thats why this swapping.
 830          */
 831         case DRM_MODE_ROTATE_90:
 832                 return PLANE_CTL_ROTATE_270;
 833         case DRM_MODE_ROTATE_180:
 834                 return PLANE_CTL_ROTATE_180;
 835         case DRM_MODE_ROTATE_270:
 836                 return PLANE_CTL_ROTATE_90;
 837         default:
 838                 MISSING_CASE(rotate);
 839         }
 840
 841         return 0;
 842 }
 843
 844 static u32 icl_plane_ctl_flip(unsigned int reflect)
 845 {
 846         switch (reflect) {
 847         case 0:
 848                 break;
 849         case DRM_MODE_REFLECT_X:
 850                 return PLANE_CTL_FLIP_HORIZONTAL;
 851         case DRM_MODE_REFLECT_Y:
 852         default:
 853                 MISSING_CASE(reflect);
 854         }
 855
 856         return 0;
 857 }
 858
 859 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
 860 {
 861         const struct drm_framebuffer *fb = plane_state->hw.fb;
 862
 863         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 864                 switch (fb->format->cpp[0]) {
 865                 case 2:
 866                         return PLANE_CTL_ARB_SLOTS(1);
 867                 default:
 868                         return PLANE_CTL_ARB_SLOTS(0);
 869                 }
 870         } else {
 871                 switch (fb->format->cpp[0]) {
 872                 case 8:
 873                         return PLANE_CTL_ARB_SLOTS(3);
 874                 case 4:
 875                         return PLANE_CTL_ARB_SLOTS(1);
 876                 default:
 877                         return PLANE_CTL_ARB_SLOTS(0);
 878                 }
 879         }
 880 }
 881
 882 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
 883 {
 884         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 885         u32 plane_ctl = 0;
 886
 887         if (DISPLAY_VER(dev_priv) >= 10)
 888                 return plane_ctl;
 889
 890         if (crtc_state->gamma_enable)
 891                 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
 892
 893         if (crtc_state->csc_enable)
 894                 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
 895
 896         return plane_ctl;
 897 }
 898
 899 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 900                          const struct intel_plane_state *plane_state)
 901 {
 902         struct drm_i915_private *dev_priv =
 903                 to_i915(plane_state->uapi.plane->dev);
 904         const struct drm_framebuffer *fb = plane_state->hw.fb;
 905         unsigned int rotation = plane_state->hw.rotation;
 906         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 907         u32 plane_ctl;
 908
 909         plane_ctl = PLANE_CTL_ENABLE;
 910
 911         if (DISPLAY_VER(dev_priv) < 10) {
 912                 plane_ctl |= skl_plane_ctl_alpha(plane_state);
 913                 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
 914
 915                 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
 916                         plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
 917
 918                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 919                         plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
 920         }
 921
 922         plane_ctl |= skl_plane_ctl_format(fb->format->format);
 923         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 924         plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
 925
 926         if (DISPLAY_VER(dev_priv) >= 11)
 927                 plane_ctl |= icl_plane_ctl_flip(rotation &
 928                                                 DRM_MODE_REFLECT_MASK);
 929
 930         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 931                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 932         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 933                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 934
 935         /* Wa_22012358565:adl-p */
 936         if (DISPLAY_VER(dev_priv) == 13)
 937                 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
 938
 939         return plane_ctl;
 940 }
 941
 942 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 945         u32 plane_color_ctl = 0;
 946
 947         if (DISPLAY_VER(dev_priv) >= 11)
 948                 return plane_color_ctl;
 949
 950         if (crtc_state->gamma_enable)
 951                 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
 952
 953         if (crtc_state->csc_enable)
 954                 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
 955
 956         return plane_color_ctl;
 957 }
 958
 959 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
 960                                const struct intel_plane_state *plane_state)
 961 {
 962         struct drm_i915_private *dev_priv =
 963                 to_i915(plane_state->uapi.plane->dev);
 964         const struct drm_framebuffer *fb = plane_state->hw.fb;
 965         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 966         u32 plane_color_ctl = 0;
 967
 968         plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
 969         plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
 970
 971         if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
 972                 switch (plane_state->hw.color_encoding) {
 973                 case DRM_COLOR_YCBCR_BT709:
 974                         plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
 975                         break;
 976                 case DRM_COLOR_YCBCR_BT2020:
 977                         plane_color_ctl |=
 978                                 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
 979                         break;
 980                 default:
 981                         plane_color_ctl |=
 982                                 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
 983                 }
 984                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 985                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 986         } else if (fb->format->is_yuv) {
 987                 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
 988                 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
 989                         plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
 990         }
 991
 992         if (plane_state->force_black)
 993                 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
 994
 995         return plane_color_ctl;
 996 }
 997
 998 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
 999                             int color_plane)
1000 {
1001         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1002         const struct drm_framebuffer *fb = plane_state->hw.fb;
1003         u32 offset = plane_state->view.color_plane[color_plane].offset;
1004
1005         if (intel_fb_uses_dpt(fb)) {
1006                 /*
1007                  * The DPT object contains only one vma, so the VMA's offset
1008                  * within the DPT is always 0.
1009                  */
1010                 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start);
1011                 drm_WARN_ON(&i915->drm, offset & 0x1fffff);
1012                 return offset >> 9;
1013         } else {
1014                 drm_WARN_ON(&i915->drm, offset & 0xfff);
1015                 return offset;
1016         }
1017 }
1018
1019 static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
1020                           int color_plane)
1021 {
1022         u32 plane_surf;
1023
1024         plane_surf = intel_plane_ggtt_offset(plane_state) +
1025                 skl_surf_address(plane_state, color_plane);
1026
1027         if (plane_state->decrypt)
1028                 plane_surf |= PLANE_SURF_DECRYPT;
1029
1030         return plane_surf;
1031 }
1032
1033 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
1034                               int color_plane)
1035 {
1036         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1037         const struct drm_framebuffer *fb = plane_state->hw.fb;
1038         int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1039         u32 aux_dist;
1040
1041         if (!aux_plane)
1042                 return 0;
1043
1044         aux_dist = skl_surf_address(plane_state, aux_plane) -
1045                 skl_surf_address(plane_state, color_plane);
1046
1047         if (DISPLAY_VER(i915) < 12)
1048                 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
1049
1050         return aux_dist;
1051 }
1052
1053 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
1054 {
1055         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1056
1057         return key->min_value;
1058 }
1059
1060 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
1061 {
1062         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1063         u8 alpha = plane_state->hw.alpha >> 8;
1064
1065         return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1066 }
1067
1068 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
1069 {
1070         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1071         u8 alpha = plane_state->hw.alpha >> 8;
1072         u32 keymsk;
1073
1074         keymsk = key->channel_mask & 0x7ffffff;
1075         if (alpha < 0xff)
1076                 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1077
1078         return keymsk;
1079 }
1080
1081 static void icl_plane_csc_load_black(struct intel_plane *plane)
1082 {
1083         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1084         enum plane_id plane_id = plane->id;
1085         enum pipe pipe = plane->pipe;
1086
1087         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
1088         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
1089
1090         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
1091         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
1092
1093         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
1094         intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
1095
1096         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
1097         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
1098         intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
1099
1100         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1101         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1102         intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1103 }
1104
1105 static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1106 {
1107         /* Program the UV plane on planar master */
1108         if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1109                 return 1;
1110         else
1111                 return 0;
1112 }
1113
1114 static void
1115 skl_plane_update_noarm(struct intel_plane *plane,
1116                        const struct intel_crtc_state *crtc_state,
1117                        const struct intel_plane_state *plane_state)
1118 {
1119         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1120         enum plane_id plane_id = plane->id;
1121         enum pipe pipe = plane->pipe;
1122         u32 stride = skl_plane_stride(plane_state, 0);
1123         int crtc_x = plane_state->uapi.dst.x1;
1124         int crtc_y = plane_state->uapi.dst.y1;
1125         u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1126         u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1127
1128         /* The scaler will handle the output position */
1129         if (plane_state->scaler_id >= 0) {
1130                 crtc_x = 0;
1131                 crtc_y = 0;
1132         }
1133
1134         intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1135                           PLANE_STRIDE_(stride));
1136         intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1137                           PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1138         intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1139                           PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1140
1141         skl_write_plane_wm(plane, crtc_state);
1142 }
1143
1144 static void
1145 skl_plane_update_arm(struct intel_plane *plane,
1146                      const struct intel_crtc_state *crtc_state,
1147                      const struct intel_plane_state *plane_state)
1148 {
1149         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1150         enum plane_id plane_id = plane->id;
1151         enum pipe pipe = plane->pipe;
1152         u32 x = plane_state->view.color_plane[0].x;
1153         u32 y = plane_state->view.color_plane[0].y;
1154         u32 plane_ctl, plane_color_ctl = 0;
1155
1156         plane_ctl = plane_state->ctl |
1157                 skl_plane_ctl_crtc(crtc_state);
1158
1159         if (DISPLAY_VER(dev_priv) >= 10)
1160                 plane_color_ctl = plane_state->color_ctl |
1161                         glk_plane_color_ctl_crtc(crtc_state);
1162
1163         intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1164         intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1165         intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1166
1167         intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1168                           PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1169
1170         intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1171                           skl_plane_aux_dist(plane_state, 0));
1172
1173         intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
1174                           PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
1175                           PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
1176
1177         if (DISPLAY_VER(dev_priv) >= 10)
1178                 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1179
1180         /*
1181          * Enable the scaler before the plane so that we don't
1182          * get a catastrophic underrun even if the two operations
1183          * end up happening in two different frames.
1184          *
1185          * TODO: split into noarm+arm pair
1186          */
1187         if (plane_state->scaler_id >= 0)
1188                 skl_program_plane_scaler(plane, crtc_state, plane_state);
1189
1190         /*
1191          * The control register self-arms if the plane was previously
1192          * disabled. Try to make the plane enable atomic by writing
1193          * the control register just before the surface register.
1194          */
1195         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1196         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1197                           skl_plane_surf(plane_state, 0));
1198 }
1199
1200 static void
1201 icl_plane_update_noarm(struct intel_plane *plane,
1202                        const struct intel_crtc_state *crtc_state,
1203                        const struct intel_plane_state *plane_state)
1204 {
1205         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1206         enum plane_id plane_id = plane->id;
1207         enum pipe pipe = plane->pipe;
1208         int color_plane = icl_plane_color_plane(plane_state);
1209         u32 stride = skl_plane_stride(plane_state, color_plane);
1210         const struct drm_framebuffer *fb = plane_state->hw.fb;
1211         int crtc_x = plane_state->uapi.dst.x1;
1212         int crtc_y = plane_state->uapi.dst.y1;
1213         int x = plane_state->view.color_plane[color_plane].x;
1214         int y = plane_state->view.color_plane[color_plane].y;
1215         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1216         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1217         u32 plane_color_ctl;
1218
1219         plane_color_ctl = plane_state->color_ctl |
1220                 glk_plane_color_ctl_crtc(crtc_state);
1221
1222         /* The scaler will handle the output position */
1223         if (plane_state->scaler_id >= 0) {
1224                 crtc_x = 0;
1225                 crtc_y = 0;
1226         }
1227
1228         intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1229                           PLANE_STRIDE_(stride));
1230         intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1231                           PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1232         intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1233                           PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1234
1235         intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1236         intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1237         intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1238
1239         intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1240                           PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1241
1242         if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
1243                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
1244                                   lower_32_bits(plane_state->ccval));
1245                 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
1246                                   upper_32_bits(plane_state->ccval));
1247         }
1248
1249         /* FLAT CCS doesn't need to program AUX_DIST */
1250         if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
1251                 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1252                                   skl_plane_aux_dist(plane_state, color_plane));
1253
1254         if (icl_is_hdr_plane(dev_priv, plane_id))
1255                 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
1256                                   plane_state->cus_ctl);
1257
1258         intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1259
1260         if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
1261                 icl_program_input_csc(plane, crtc_state, plane_state);
1262
1263         skl_write_plane_wm(plane, crtc_state);
1264
1265         /*
1266          * FIXME: pxp session invalidation can hit any time even at time of commit
1267          * or after the commit, display content will be garbage.
1268          */
1269         if (plane_state->force_black)
1270                 icl_plane_csc_load_black(plane);
1271
1272         intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
1273 }
1274
1275 static void
1276 icl_plane_update_arm(struct intel_plane *plane,
1277                      const struct intel_crtc_state *crtc_state,
1278                      const struct intel_plane_state *plane_state)
1279 {
1280         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1281         enum plane_id plane_id = plane->id;
1282         enum pipe pipe = plane->pipe;
1283         int color_plane = icl_plane_color_plane(plane_state);
1284         u32 plane_ctl;
1285
1286         plane_ctl = plane_state->ctl |
1287                 skl_plane_ctl_crtc(crtc_state);
1288
1289         /*
1290          * Enable the scaler before the plane so that we don't
1291          * get a catastrophic underrun even if the two operations
1292          * end up happening in two different frames.
1293          *
1294          * TODO: split into noarm+arm pair
1295          */
1296         if (plane_state->scaler_id >= 0)
1297                 skl_program_plane_scaler(plane, crtc_state, plane_state);
1298
1299         intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state);
1300
1301         /*
1302          * The control register self-arms if the plane was previously
1303          * disabled. Try to make the plane enable atomic by writing
1304          * the control register just before the surface register.
1305          */
1306         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1307         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1308                           skl_plane_surf(plane_state, color_plane));
1309 }
1310
1311 static void
1312 skl_plane_async_flip(struct intel_plane *plane,
1313                      const struct intel_crtc_state *crtc_state,
1314                      const struct intel_plane_state *plane_state,
1315                      bool async_flip)
1316 {
1317         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1318         enum plane_id plane_id = plane->id;
1319         enum pipe pipe = plane->pipe;
1320         u32 plane_ctl = plane_state->ctl;
1321
1322         plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1323
1324         if (async_flip)
1325                 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1326
1327         intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1328         intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1329                           skl_plane_surf(plane_state, 0));
1330 }
1331
1332 static bool intel_format_is_p01x(u32 format)
1333 {
1334         switch (format) {
1335         case DRM_FORMAT_P010:
1336         case DRM_FORMAT_P012:
1337         case DRM_FORMAT_P016:
1338                 return true;
1339         default:
1340                 return false;
1341         }
1342 }
1343
1344 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1345                               const struct intel_plane_state *plane_state)
1346 {
1347         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1348         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1349         const struct drm_framebuffer *fb = plane_state->hw.fb;
1350         unsigned int rotation = plane_state->hw.rotation;
1351
1352         if (!fb)
1353                 return 0;
1354
1355         if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1356             intel_fb_is_ccs_modifier(fb->modifier)) {
1357                 drm_dbg_kms(&dev_priv->drm,
1358                             "RC support only with 0/180 degree rotation (%x)\n",
1359                             rotation);
1360                 return -EINVAL;
1361         }
1362
1363         if (rotation & DRM_MODE_REFLECT_X &&
1364             fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1365                 drm_dbg_kms(&dev_priv->drm,
1366                             "horizontal flip is not supported with linear surface formats\n");
1367                 return -EINVAL;
1368         }
1369
1370         if (drm_rotation_90_or_270(rotation)) {
1371                 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
1372                         drm_dbg_kms(&dev_priv->drm,
1373                                     "Y/Yf tiling required for 90/270!\n");
1374                         return -EINVAL;
1375                 }
1376
1377                 /*
1378                  * 90/270 is not allowed with RGB64 16:16:16:16 and
1379                  * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1380                  */
1381                 switch (fb->format->format) {
1382                 case DRM_FORMAT_RGB565:
1383                         if (DISPLAY_VER(dev_priv) >= 11)
1384                                 break;
1385                         fallthrough;
1386                 case DRM_FORMAT_C8:
1387                 case DRM_FORMAT_XRGB16161616F:
1388                 case DRM_FORMAT_XBGR16161616F:
1389                 case DRM_FORMAT_ARGB16161616F:
1390                 case DRM_FORMAT_ABGR16161616F:
1391                 case DRM_FORMAT_Y210:
1392                 case DRM_FORMAT_Y212:
1393                 case DRM_FORMAT_Y216:
1394                 case DRM_FORMAT_XVYU12_16161616:
1395                 case DRM_FORMAT_XVYU16161616:
1396                         drm_dbg_kms(&dev_priv->drm,
1397                                     "Unsupported pixel format %p4cc for 90/270!\n",
1398                                     &fb->format->format);
1399                         return -EINVAL;
1400                 default:
1401                         break;
1402                 }
1403         }
1404
1405         /* Y-tiling is not supported in IF-ID Interlace mode */
1406         if (crtc_state->hw.enable &&
1407             crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1408             fb->modifier != DRM_FORMAT_MOD_LINEAR &&
1409             fb->modifier != I915_FORMAT_MOD_X_TILED) {
1410                 drm_dbg_kms(&dev_priv->drm,
1411                             "Y/Yf tiling not supported in IF-ID mode\n");
1412                 return -EINVAL;
1413         }
1414
1415         /* Wa_1606054188:tgl,adl-s */
1416         if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
1417             plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
1418             intel_format_is_p01x(fb->format->format)) {
1419                 drm_dbg_kms(&dev_priv->drm,
1420                             "Source color keying not supported with P01x formats\n");
1421                 return -EINVAL;
1422         }
1423
1424         return 0;
1425 }
1426
1427 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1428                                            const struct intel_plane_state *plane_state)
1429 {
1430         struct drm_i915_private *dev_priv =
1431                 to_i915(plane_state->uapi.plane->dev);
1432         int crtc_x = plane_state->uapi.dst.x1;
1433         int crtc_w = drm_rect_width(&plane_state->uapi.dst);
1434         int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
1435
1436         /*
1437          * Display WA #1175: glk
1438          * Planes other than the cursor may cause FIFO underflow and display
1439          * corruption if starting less than 4 pixels from the right edge of
1440          * the screen.
1441          * Besides the above WA fix the similar problem, where planes other
1442          * than the cursor ending less than 4 pixels from the left edge of the
1443          * screen may cause FIFO underflow and display corruption.
1444          */
1445         if (DISPLAY_VER(dev_priv) == 10 &&
1446             (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1447                 drm_dbg_kms(&dev_priv->drm,
1448                             "requested plane X %s position %d invalid (valid range %d-%d)\n",
1449                             crtc_x + crtc_w < 4 ? "end" : "start",
1450                             crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1451                             4, pipe_src_w - 4);
1452                 return -ERANGE;
1453         }
1454
1455         return 0;
1456 }
1457
1458 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1459 {
1460         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1461         const struct drm_framebuffer *fb = plane_state->hw.fb;
1462         unsigned int rotation = plane_state->hw.rotation;
1463         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1464
1465         /* Display WA #1106 */
1466         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1467             src_w & 3 &&
1468             (rotation == DRM_MODE_ROTATE_270 ||
1469              rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1470                 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
1471                 return -EINVAL;
1472         }
1473
1474         return 0;
1475 }
1476
1477 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
1478                                const struct drm_framebuffer *fb)
1479 {
1480         /*
1481          * We don't yet know the final source width nor
1482          * whether we can use the HQ scaler mode. Assume
1483          * the best case.
1484          * FIXME need to properly check this later.
1485          */
1486         if (DISPLAY_VER(dev_priv) >= 10 ||
1487             !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1488                 return 0x30000 - 1;
1489         else
1490                 return 0x20000 - 1;
1491 }
1492
1493 static int intel_plane_min_width(struct intel_plane *plane,
1494                                  const struct drm_framebuffer *fb,
1495                                  int color_plane,
1496                                  unsigned int rotation)
1497 {
1498         if (plane->min_width)
1499                 return plane->min_width(fb, color_plane, rotation);
1500         else
1501                 return 1;
1502 }
1503
1504 static int intel_plane_max_width(struct intel_plane *plane,
1505                                  const struct drm_framebuffer *fb,
1506                                  int color_plane,
1507                                  unsigned int rotation)
1508 {
1509         if (plane->max_width)
1510                 return plane->max_width(fb, color_plane, rotation);
1511         else
1512                 return INT_MAX;
1513 }
1514
1515 static int intel_plane_max_height(struct intel_plane *plane,
1516                                   const struct drm_framebuffer *fb,
1517                                   int color_plane,
1518                                   unsigned int rotation)
1519 {
1520         if (plane->max_height)
1521                 return plane->max_height(fb, color_plane, rotation);
1522         else
1523                 return INT_MAX;
1524 }
1525
1526 static bool
1527 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
1528                                int main_x, int main_y, u32 main_offset,
1529                                int ccs_plane)
1530 {
1531         const struct drm_framebuffer *fb = plane_state->hw.fb;
1532         int aux_x = plane_state->view.color_plane[ccs_plane].x;
1533         int aux_y = plane_state->view.color_plane[ccs_plane].y;
1534         u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1535         u32 alignment = intel_surf_alignment(fb, ccs_plane);
1536         int hsub;
1537         int vsub;
1538
1539         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1540         while (aux_offset >= main_offset && aux_y <= main_y) {
1541                 int x, y;
1542
1543                 if (aux_x == main_x && aux_y == main_y)
1544                         break;
1545
1546                 if (aux_offset == 0)
1547                         break;
1548
1549                 x = aux_x / hsub;
1550                 y = aux_y / vsub;
1551                 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
1552                                                                plane_state,
1553                                                                ccs_plane,
1554                                                                aux_offset,
1555                                                                aux_offset -
1556                                                                 alignment);
1557                 aux_x = x * hsub + aux_x % hsub;
1558                 aux_y = y * vsub + aux_y % vsub;
1559         }
1560
1561         if (aux_x != main_x || aux_y != main_y)
1562                 return false;
1563
1564         plane_state->view.color_plane[ccs_plane].offset = aux_offset;
1565         plane_state->view.color_plane[ccs_plane].x = aux_x;
1566         plane_state->view.color_plane[ccs_plane].y = aux_y;
1567
1568         return true;
1569 }
1570
1571
1572 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
1573                                  int *x, int *y, u32 *offset)
1574 {
1575         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1576         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1577         const struct drm_framebuffer *fb = plane_state->hw.fb;
1578         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1579         const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;
1580         const u32 alignment = intel_surf_alignment(fb, 0);
1581         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1582
1583         intel_add_fb_offsets(x, y, plane_state, 0);
1584         *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
1585         if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
1586                 return -EINVAL;
1587
1588         /*
1589          * AUX surface offset is specified as the distance from the
1590          * main surface offset, and it must be non-negative. Make
1591          * sure that is what we will get.
1592          */
1593         if (aux_plane && *offset > aux_offset)
1594                 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1595                                                             *offset,
1596                                                             aux_offset & ~(alignment - 1));
1597
1598         /*
1599          * When using an X-tiled surface, the plane blows up
1600          * if the x offset + width exceed the stride.
1601          *
1602          * TODO: linear and Y-tiled seem fine, Yf untested,
1603          */
1604         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
1605                 int cpp = fb->format->cpp[0];
1606
1607                 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
1608                         if (*offset == 0) {
1609                                 drm_dbg_kms(&dev_priv->drm,
1610                                             "Unable to find suitable display surface offset due to X-tiling\n");
1611                                 return -EINVAL;
1612                         }
1613
1614                         *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1615                                                                     *offset,
1616                                                                     *offset - alignment);
1617                 }
1618         }
1619
1620         return 0;
1621 }
1622
1623 static int skl_check_main_surface(struct intel_plane_state *plane_state)
1624 {
1625         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1626         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1627         const struct drm_framebuffer *fb = plane_state->hw.fb;
1628         const unsigned int rotation = plane_state->hw.rotation;
1629         int x = plane_state->uapi.src.x1 >> 16;
1630         int y = plane_state->uapi.src.y1 >> 16;
1631         const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1632         const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
1633         const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
1634         const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
1635         const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
1636         const int aux_plane = skl_main_to_aux_plane(fb, 0);
1637         const u32 alignment = intel_surf_alignment(fb, 0);
1638         u32 offset;
1639         int ret;
1640
1641         if (w > max_width || w < min_width || h > max_height || h < 1) {
1642                 drm_dbg_kms(&dev_priv->drm,
1643                             "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
1644                             w, h, min_width, max_width, max_height);
1645                 return -EINVAL;
1646         }
1647
1648         ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1649         if (ret)
1650                 return ret;
1651
1652         /*
1653          * CCS AUX surface doesn't have its own x/y offsets, we must make sure
1654          * they match with the main surface x/y offsets. On DG2
1655          * there's no aux plane on fb so skip this checking.
1656          */
1657         if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
1658                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1659                                                        offset, aux_plane)) {
1660                         if (offset == 0)
1661                                 break;
1662
1663                         offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1664                                                                    offset, offset - alignment);
1665                 }
1666
1667                 if (x != plane_state->view.color_plane[aux_plane].x ||
1668                     y != plane_state->view.color_plane[aux_plane].y) {
1669                         drm_dbg_kms(&dev_priv->drm,
1670                                     "Unable to find suitable display surface offset due to CCS\n");
1671                         return -EINVAL;
1672                 }
1673         }
1674
1675         if (DISPLAY_VER(dev_priv) >= 13)
1676                 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
1677         else
1678                 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
1679
1680         plane_state->view.color_plane[0].offset = offset;
1681         plane_state->view.color_plane[0].x = x;
1682         plane_state->view.color_plane[0].y = y;
1683
1684         /*
1685          * Put the final coordinates back so that the src
1686          * coordinate checks will see the right values.
1687          */
1688         drm_rect_translate_to(&plane_state->uapi.src,
1689                               x << 16, y << 16);
1690
1691         return 0;
1692 }
1693
1694 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
1695 {
1696         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1697         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1698         const struct drm_framebuffer *fb = plane_state->hw.fb;
1699         unsigned int rotation = plane_state->hw.rotation;
1700         int uv_plane = 1;
1701         int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
1702                         skl_main_to_aux_plane(fb, uv_plane) : 0;
1703         int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
1704         int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
1705         int x = plane_state->uapi.src.x1 >> 17;
1706         int y = plane_state->uapi.src.y1 >> 17;
1707         int w = drm_rect_width(&plane_state->uapi.src) >> 17;
1708         int h = drm_rect_height(&plane_state->uapi.src) >> 17;
1709         u32 offset;
1710
1711         /* FIXME not quite sure how/if these apply to the chroma plane */
1712         if (w > max_width || h > max_height) {
1713                 drm_dbg_kms(&i915->drm,
1714                             "CbCr source size %dx%d too big (limit %dx%d)\n",
1715                             w, h, max_width, max_height);
1716                 return -EINVAL;
1717         }
1718
1719         intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
1720         offset = intel_plane_compute_aligned_offset(&x, &y,
1721                                                     plane_state, uv_plane);
1722
1723         if (ccs_plane) {
1724                 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1725                 u32 alignment = intel_surf_alignment(fb, uv_plane);
1726
1727                 if (offset > aux_offset)
1728                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1729                                                                    plane_state,
1730                                                                    uv_plane,
1731                                                                    offset,
1732                                                                    aux_offset & ~(alignment - 1));
1733
1734                 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1735                                                        offset, ccs_plane)) {
1736                         if (offset == 0)
1737                                 break;
1738
1739                         offset = intel_plane_adjust_aligned_offset(&x, &y,
1740                                                                    plane_state,
1741                                                                    uv_plane,
1742                                                                    offset, offset - alignment);
1743                 }
1744
1745                 if (x != plane_state->view.color_plane[ccs_plane].x ||
1746                     y != plane_state->view.color_plane[ccs_plane].y) {
1747                         drm_dbg_kms(&i915->drm,
1748                                     "Unable to find suitable display surface offset due to CCS\n");
1749                         return -EINVAL;
1750                 }
1751         }
1752
1753         if (DISPLAY_VER(i915) >= 13)
1754                 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
1755         else
1756                 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
1757
1758         plane_state->view.color_plane[uv_plane].offset = offset;
1759         plane_state->view.color_plane[uv_plane].x = x;
1760         plane_state->view.color_plane[uv_plane].y = y;
1761
1762         return 0;
1763 }
1764
1765 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
1766 {
1767         const struct drm_framebuffer *fb = plane_state->hw.fb;
1768         int src_x = plane_state->uapi.src.x1 >> 16;
1769         int src_y = plane_state->uapi.src.y1 >> 16;
1770         u32 offset;
1771         int ccs_plane;
1772
1773         for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
1774                 int main_hsub, main_vsub;
1775                 int hsub, vsub;
1776                 int x, y;
1777
1778                 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1779                         continue;
1780
1781                 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
1782                                                skl_ccs_to_main_plane(fb, ccs_plane));
1783                 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1784
1785                 hsub *= main_hsub;
1786                 vsub *= main_vsub;
1787                 x = src_x / hsub;
1788                 y = src_y / vsub;
1789
1790                 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
1791
1792                 offset = intel_plane_compute_aligned_offset(&x, &y,
1793                                                             plane_state,
1794                                                             ccs_plane);
1795
1796                 plane_state->view.color_plane[ccs_plane].offset = offset;
1797                 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;
1798                 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;
1799         }
1800
1801         return 0;
1802 }
1803
1804 static int skl_check_plane_surface(struct intel_plane_state *plane_state)
1805 {
1806         const struct drm_framebuffer *fb = plane_state->hw.fb;
1807         int ret;
1808
1809         ret = intel_plane_compute_gtt(plane_state);
1810         if (ret)
1811                 return ret;
1812
1813         if (!plane_state->uapi.visible)
1814                 return 0;
1815
1816         /*
1817          * Handle the AUX surface first since the main surface setup depends on
1818          * it.
1819          */
1820         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1821                 ret = skl_check_ccs_aux_surface(plane_state);
1822                 if (ret)
1823                         return ret;
1824         }
1825
1826         if (intel_format_info_is_yuv_semiplanar(fb->format,
1827                                                 fb->modifier)) {
1828                 ret = skl_check_nv12_aux_surface(plane_state);
1829                 if (ret)
1830                         return ret;
1831         }
1832
1833         ret = skl_check_main_surface(plane_state);
1834         if (ret)
1835                 return ret;
1836
1837         return 0;
1838 }
1839
1840 static bool skl_fb_scalable(const struct drm_framebuffer *fb)
1841 {
1842         if (!fb)
1843                 return false;
1844
1845         switch (fb->format->format) {
1846         case DRM_FORMAT_C8:
1847                 return false;
1848         case DRM_FORMAT_XRGB16161616F:
1849         case DRM_FORMAT_ARGB16161616F:
1850         case DRM_FORMAT_XBGR16161616F:
1851         case DRM_FORMAT_ABGR16161616F:
1852                 return DISPLAY_VER(to_i915(fb->dev)) >= 11;
1853         default:
1854                 return true;
1855         }
1856 }
1857
1858 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
1859 {
1860         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1861
1862         return intel_pxp_key_check(i915->pxp, obj, false) == 0;
1863 }
1864
1865 static bool pxp_is_borked(struct drm_i915_gem_object *obj)
1866 {
1867         return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj);
1868 }
1869
1870 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1871                            struct intel_plane_state *plane_state)
1872 {
1873         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1874         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1875         const struct drm_framebuffer *fb = plane_state->hw.fb;
1876         int min_scale = DRM_PLANE_NO_SCALING;
1877         int max_scale = DRM_PLANE_NO_SCALING;
1878         int ret;
1879
1880         ret = skl_plane_check_fb(crtc_state, plane_state);
1881         if (ret)
1882                 return ret;
1883
1884         /* use scaler when colorkey is not required */
1885         if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
1886                 min_scale = 1;
1887                 max_scale = skl_plane_max_scale(dev_priv, fb);
1888         }
1889
1890         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
1891                                                 min_scale, max_scale, true);
1892         if (ret)
1893                 return ret;
1894
1895         ret = skl_check_plane_surface(plane_state);
1896         if (ret)
1897                 return ret;
1898
1899         if (!plane_state->uapi.visible)
1900                 return 0;
1901
1902         ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1903         if (ret)
1904                 return ret;
1905
1906         ret = intel_plane_check_src_coordinates(plane_state);
1907         if (ret)
1908                 return ret;
1909
1910         ret = skl_plane_check_nv12_rotation(plane_state);
1911         if (ret)
1912                 return ret;
1913
1914         if (DISPLAY_VER(dev_priv) >= 11) {
1915                 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb));
1916                 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
1917         }
1918
1919         /* HW only has 8 bits pixel precision, disable plane if invisible */
1920         if (!(plane_state->hw.alpha >> 8))
1921                 plane_state->uapi.visible = false;
1922
1923         plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1924
1925         if (DISPLAY_VER(dev_priv) >= 10)
1926                 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1927                                                              plane_state);
1928
1929         if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1930             icl_is_hdr_plane(dev_priv, plane->id))
1931                 /* Enable and use MPEG-2 chroma siting */
1932                 plane_state->cus_ctl = PLANE_CUS_ENABLE |
1933                         PLANE_CUS_HPHASE_0 |
1934                         PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
1935         else
1936                 plane_state->cus_ctl = 0;
1937
1938         return 0;
1939 }
1940
1941 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
1942 {
1943         return pipe - PIPE_A + INTEL_FBC_A;
1944 }
1945
1946 static bool skl_plane_has_fbc(struct drm_i915_private *i915,
1947                               enum intel_fbc_id fbc_id, enum plane_id plane_id)
1948 {
1949         if ((DISPLAY_RUNTIME_INFO(i915)->fbc_mask & BIT(fbc_id)) == 0)
1950                 return false;
1951
1952         if (DISPLAY_VER(i915) >= 20)
1953                 return icl_is_hdr_plane(i915, plane_id);
1954         else
1955                 return plane_id == PLANE_PRIMARY;
1956 }
1957
1958 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
1959                                        enum pipe pipe, enum plane_id plane_id)
1960 {
1961         enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
1962
1963         if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
1964                 return dev_priv->display.fbc[fbc_id];
1965         else
1966                 return NULL;
1967 }
1968
1969 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1970                                  enum pipe pipe, enum plane_id plane_id)
1971 {
1972         /* Display WA #0870: skl, bxt */
1973         if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1974                 return false;
1975
1976         if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
1977                 return false;
1978
1979         if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
1980                 return false;
1981
1982         return true;
1983 }
1984
1985 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
1986                                         enum pipe pipe, enum plane_id plane_id,
1987                                         int *num_formats)
1988 {
1989         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1990                 *num_formats = ARRAY_SIZE(skl_planar_formats);
1991                 return skl_planar_formats;
1992         } else {
1993                 *num_formats = ARRAY_SIZE(skl_plane_formats);
1994                 return skl_plane_formats;
1995         }
1996 }
1997
1998 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
1999                                         enum pipe pipe, enum plane_id plane_id,
2000                                         int *num_formats)
2001 {
2002         if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
2003                 *num_formats = ARRAY_SIZE(glk_planar_formats);
2004                 return glk_planar_formats;
2005         } else {
2006                 *num_formats = ARRAY_SIZE(skl_plane_formats);
2007                 return skl_plane_formats;
2008         }
2009 }
2010
2011 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2012                                         enum pipe pipe, enum plane_id plane_id,
2013                                         int *num_formats)
2014 {
2015         if (icl_is_hdr_plane(dev_priv, plane_id)) {
2016                 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2017                 return icl_hdr_plane_formats;
2018         } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
2019                 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2020                 return icl_sdr_y_plane_formats;
2021         } else {
2022                 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2023                 return icl_sdr_uv_plane_formats;
2024         }
2025 }
2026
2027 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2028                                            u32 format, u64 modifier)
2029 {
2030         struct intel_plane *plane = to_intel_plane(_plane);
2031
2032         if (!intel_fb_plane_supports_modifier(plane, modifier))
2033                 return false;
2034
2035         switch (format) {
2036         case DRM_FORMAT_XRGB8888:
2037         case DRM_FORMAT_XBGR8888:
2038         case DRM_FORMAT_ARGB8888:
2039         case DRM_FORMAT_ABGR8888:
2040                 if (intel_fb_is_ccs_modifier(modifier))
2041                         return true;
2042                 fallthrough;
2043         case DRM_FORMAT_RGB565:
2044         case DRM_FORMAT_XRGB2101010:
2045         case DRM_FORMAT_XBGR2101010:
2046         case DRM_FORMAT_ARGB2101010:
2047         case DRM_FORMAT_ABGR2101010:
2048         case DRM_FORMAT_YUYV:
2049         case DRM_FORMAT_YVYU:
2050         case DRM_FORMAT_UYVY:
2051         case DRM_FORMAT_VYUY:
2052         case DRM_FORMAT_NV12:
2053         case DRM_FORMAT_XYUV8888:
2054         case DRM_FORMAT_P010:
2055         case DRM_FORMAT_P012:
2056         case DRM_FORMAT_P016:
2057         case DRM_FORMAT_XVYU2101010:
2058                 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2059                         return true;
2060                 fallthrough;
2061         case DRM_FORMAT_C8:
2062         case DRM_FORMAT_XBGR16161616F:
2063         case DRM_FORMAT_ABGR16161616F:
2064         case DRM_FORMAT_XRGB16161616F:
2065         case DRM_FORMAT_ARGB16161616F:
2066         case DRM_FORMAT_Y210:
2067         case DRM_FORMAT_Y212:
2068         case DRM_FORMAT_Y216:
2069         case DRM_FORMAT_XVYU12_16161616:
2070         case DRM_FORMAT_XVYU16161616:
2071                 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2072                     modifier == I915_FORMAT_MOD_X_TILED ||
2073                     modifier == I915_FORMAT_MOD_Y_TILED)
2074                         return true;
2075                 fallthrough;
2076         default:
2077                 return false;
2078         }
2079 }
2080
2081 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
2082                                              u32 format, u64 modifier)
2083 {
2084         struct intel_plane *plane = to_intel_plane(_plane);
2085
2086         if (!intel_fb_plane_supports_modifier(plane, modifier))
2087                 return false;
2088
2089         switch (format) {
2090         case DRM_FORMAT_XRGB8888:
2091         case DRM_FORMAT_XBGR8888:
2092         case DRM_FORMAT_ARGB8888:
2093         case DRM_FORMAT_ABGR8888:
2094                 if (intel_fb_is_ccs_modifier(modifier))
2095                         return true;
2096                 fallthrough;
2097         case DRM_FORMAT_YUYV:
2098         case DRM_FORMAT_YVYU:
2099         case DRM_FORMAT_UYVY:
2100         case DRM_FORMAT_VYUY:
2101         case DRM_FORMAT_NV12:
2102         case DRM_FORMAT_XYUV8888:
2103         case DRM_FORMAT_P010:
2104         case DRM_FORMAT_P012:
2105         case DRM_FORMAT_P016:
2106                 if (intel_fb_is_mc_ccs_modifier(modifier))
2107                         return true;
2108                 fallthrough;
2109         case DRM_FORMAT_RGB565:
2110         case DRM_FORMAT_XRGB2101010:
2111         case DRM_FORMAT_XBGR2101010:
2112         case DRM_FORMAT_ARGB2101010:
2113         case DRM_FORMAT_ABGR2101010:
2114         case DRM_FORMAT_XVYU2101010:
2115         case DRM_FORMAT_C8:
2116         case DRM_FORMAT_XBGR16161616F:
2117         case DRM_FORMAT_ABGR16161616F:
2118         case DRM_FORMAT_XRGB16161616F:
2119         case DRM_FORMAT_ARGB16161616F:
2120         case DRM_FORMAT_Y210:
2121         case DRM_FORMAT_Y212:
2122         case DRM_FORMAT_Y216:
2123         case DRM_FORMAT_XVYU12_16161616:
2124         case DRM_FORMAT_XVYU16161616:
2125                 if (!intel_fb_is_ccs_modifier(modifier))
2126                         return true;
2127                 fallthrough;
2128         default:
2129                 return false;
2130         }
2131 }
2132
2133 static const struct drm_plane_funcs skl_plane_funcs = {
2134         .update_plane = drm_atomic_helper_update_plane,
2135         .disable_plane = drm_atomic_helper_disable_plane,
2136         .destroy = intel_plane_destroy,
2137         .atomic_duplicate_state = intel_plane_duplicate_state,
2138         .atomic_destroy_state = intel_plane_destroy_state,
2139         .format_mod_supported = skl_plane_format_mod_supported,
2140 };
2141
2142 static const struct drm_plane_funcs gen12_plane_funcs = {
2143         .update_plane = drm_atomic_helper_update_plane,
2144         .disable_plane = drm_atomic_helper_disable_plane,
2145         .destroy = intel_plane_destroy,
2146         .atomic_duplicate_state = intel_plane_duplicate_state,
2147         .atomic_destroy_state = intel_plane_destroy_state,
2148         .format_mod_supported = gen12_plane_format_mod_supported,
2149 };
2150
2151 static void
2152 skl_plane_enable_flip_done(struct intel_plane *plane)
2153 {
2154         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2155         enum pipe pipe = plane->pipe;
2156
2157         spin_lock_irq(&i915->irq_lock);
2158         bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2159         spin_unlock_irq(&i915->irq_lock);
2160 }
2161
2162 static void
2163 skl_plane_disable_flip_done(struct intel_plane *plane)
2164 {
2165         struct drm_i915_private *i915 = to_i915(plane->base.dev);
2166         enum pipe pipe = plane->pipe;
2167
2168         spin_lock_irq(&i915->irq_lock);
2169         bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2170         spin_unlock_irq(&i915->irq_lock);
2171 }
2172
2173 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
2174                                  enum pipe pipe, enum plane_id plane_id)
2175 {
2176         /* Wa_22011186057 */
2177         if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2178                 return false;
2179
2180         if (DISPLAY_VER(i915) >= 11)
2181                 return true;
2182
2183         if (IS_GEMINILAKE(i915))
2184                 return pipe != PIPE_C;
2185
2186         return pipe != PIPE_C &&
2187                 (plane_id == PLANE_PRIMARY ||
2188                  plane_id == PLANE_SPRITE0);
2189 }
2190
2191 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
2192                                    enum plane_id plane_id)
2193 {
2194         if (DISPLAY_VER(i915) < 12)
2195                 return false;
2196
2197         /* Wa_14010477008 */
2198         if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
2199                 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
2200                 return false;
2201
2202         /* Wa_22011186057 */
2203         if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2204                 return false;
2205
2206         return plane_id < PLANE_SPRITE4;
2207 }
2208
2209 static u8 skl_get_plane_caps(struct drm_i915_private *i915,
2210                              enum pipe pipe, enum plane_id plane_id)
2211 {
2212         u8 caps = INTEL_PLANE_CAP_TILING_X;
2213
2214         if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
2215                 caps |= INTEL_PLANE_CAP_TILING_Y;
2216         if (DISPLAY_VER(i915) < 12)
2217                 caps |= INTEL_PLANE_CAP_TILING_Yf;
2218         if (HAS_4TILE(i915))
2219                 caps |= INTEL_PLANE_CAP_TILING_4;
2220
2221         if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
2222                 caps |= INTEL_PLANE_CAP_CCS_RC;
2223                 if (DISPLAY_VER(i915) >= 12)
2224                         caps |= INTEL_PLANE_CAP_CCS_RC_CC;
2225         }
2226
2227         if (gen12_plane_has_mc_ccs(i915, plane_id))
2228                 caps |= INTEL_PLANE_CAP_CCS_MC;
2229
2230         return caps;
2231 }
2232
2233 struct intel_plane *
2234 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2235                            enum pipe pipe, enum plane_id plane_id)
2236 {
2237         const struct drm_plane_funcs *plane_funcs;
2238         struct intel_plane *plane;
2239         enum drm_plane_type plane_type;
2240         unsigned int supported_rotations;
2241         unsigned int supported_csc;
2242         const u64 *modifiers;
2243         const u32 *formats;
2244         int num_formats;
2245         int ret;
2246
2247         plane = intel_plane_alloc();
2248         if (IS_ERR(plane))
2249                 return plane;
2250
2251         plane->pipe = pipe;
2252         plane->id = plane_id;
2253         plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2254
2255         intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
2256
2257         if (DISPLAY_VER(dev_priv) >= 11) {
2258                 plane->min_width = icl_plane_min_width;
2259                 if (icl_is_hdr_plane(dev_priv, plane_id))
2260                         plane->max_width = icl_hdr_plane_max_width;
2261                 else
2262                         plane->max_width = icl_sdr_plane_max_width;
2263                 plane->max_height = icl_plane_max_height;
2264                 plane->min_cdclk = icl_plane_min_cdclk;
2265         } else if (DISPLAY_VER(dev_priv) >= 10) {
2266                 plane->max_width = glk_plane_max_width;
2267                 plane->max_height = skl_plane_max_height;
2268                 plane->min_cdclk = glk_plane_min_cdclk;
2269         } else {
2270                 plane->max_width = skl_plane_max_width;
2271                 plane->max_height = skl_plane_max_height;
2272                 plane->min_cdclk = skl_plane_min_cdclk;
2273         }
2274
2275         plane->max_stride = skl_plane_max_stride;
2276         if (DISPLAY_VER(dev_priv) >= 11) {
2277                 plane->update_noarm = icl_plane_update_noarm;
2278                 plane->update_arm = icl_plane_update_arm;
2279                 plane->disable_arm = icl_plane_disable_arm;
2280         } else {
2281                 plane->update_noarm = skl_plane_update_noarm;
2282                 plane->update_arm = skl_plane_update_arm;
2283                 plane->disable_arm = skl_plane_disable_arm;
2284         }
2285         plane->get_hw_state = skl_plane_get_hw_state;
2286         plane->check_plane = skl_plane_check;
2287
2288         if (plane_id == PLANE_PRIMARY) {
2289                 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
2290                                                                    9, 10);
2291                 plane->async_flip = skl_plane_async_flip;
2292                 plane->enable_flip_done = skl_plane_enable_flip_done;
2293                 plane->disable_flip_done = skl_plane_disable_flip_done;
2294         }
2295
2296         if (DISPLAY_VER(dev_priv) >= 11)
2297                 formats = icl_get_plane_formats(dev_priv, pipe,
2298                                                 plane_id, &num_formats);
2299         else if (DISPLAY_VER(dev_priv) >= 10)
2300                 formats = glk_get_plane_formats(dev_priv, pipe,
2301                                                 plane_id, &num_formats);
2302         else
2303                 formats = skl_get_plane_formats(dev_priv, pipe,
2304                                                 plane_id, &num_formats);
2305
2306         if (DISPLAY_VER(dev_priv) >= 12)
2307                 plane_funcs = &gen12_plane_funcs;
2308         else
2309                 plane_funcs = &skl_plane_funcs;
2310
2311         if (plane_id == PLANE_PRIMARY)
2312                 plane_type = DRM_PLANE_TYPE_PRIMARY;
2313         else
2314                 plane_type = DRM_PLANE_TYPE_OVERLAY;
2315
2316         modifiers = intel_fb_plane_get_modifiers(dev_priv,
2317                                                  skl_get_plane_caps(dev_priv, pipe, plane_id));
2318
2319         ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2320                                        0, plane_funcs,
2321                                        formats, num_formats, modifiers,
2322                                        plane_type,
2323                                        "plane %d%c", plane_id + 1,
2324                                        pipe_name(pipe));
2325
2326         kfree(modifiers);
2327
2328         if (ret)
2329                 goto fail;
2330
2331         if (DISPLAY_VER(dev_priv) >= 13)
2332                 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2333         else
2334                 supported_rotations =
2335                         DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2336                         DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2337
2338         if (DISPLAY_VER(dev_priv) >= 11)
2339                 supported_rotations |= DRM_MODE_REFLECT_X;
2340
2341         drm_plane_create_rotation_property(&plane->base,
2342                                            DRM_MODE_ROTATE_0,
2343                                            supported_rotations);
2344
2345         supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
2346
2347         if (DISPLAY_VER(dev_priv) >= 10)
2348                 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
2349
2350         drm_plane_create_color_properties(&plane->base,
2351                                           supported_csc,
2352                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2353                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2354                                           DRM_COLOR_YCBCR_BT709,
2355                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
2356
2357         drm_plane_create_alpha_property(&plane->base);
2358         drm_plane_create_blend_mode_property(&plane->base,
2359                                              BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2360                                              BIT(DRM_MODE_BLEND_PREMULTI) |
2361                                              BIT(DRM_MODE_BLEND_COVERAGE));
2362
2363         drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2364
2365         if (DISPLAY_VER(dev_priv) >= 12)
2366                 drm_plane_enable_fb_damage_clips(&plane->base);
2367
2368         if (DISPLAY_VER(dev_priv) >= 11)
2369                 drm_plane_create_scaling_filter_property(&plane->base,
2370                                                 BIT(DRM_SCALING_FILTER_DEFAULT) |
2371                                                 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
2372
2373         intel_plane_helper_add(plane);
2374
2375         return plane;
2376
2377 fail:
2378         intel_plane_free(plane);
2379
2380         return ERR_PTR(ret);
2381 }
2382
2383 void
2384 skl_get_initial_plane_config(struct intel_crtc *crtc,
2385                              struct intel_initial_plane_config *plane_config)
2386 {
2387         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
2388         struct drm_device *dev = crtc->base.dev;
2389         struct drm_i915_private *dev_priv = to_i915(dev);
2390         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2391         enum plane_id plane_id = plane->id;
2392         enum pipe pipe;
2393         u32 val, base, offset, stride_mult, tiling, alpha;
2394         int fourcc, pixel_format;
2395         unsigned int aligned_height;
2396         struct drm_framebuffer *fb;
2397         struct intel_framebuffer *intel_fb;
2398         static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
2399
2400         if (!plane->get_hw_state(plane, &pipe))
2401                 return;
2402
2403         drm_WARN_ON(dev, pipe != crtc->pipe);
2404
2405         if (crtc_state->bigjoiner_pipes) {
2406                 drm_dbg_kms(&dev_priv->drm,
2407                             "Unsupported bigjoiner configuration for initial FB\n");
2408                 return;
2409         }
2410
2411         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2412         if (!intel_fb) {
2413                 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
2414                 return;
2415         }
2416
2417         fb = &intel_fb->base;
2418
2419         fb->dev = dev;
2420
2421         val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
2422
2423         if (DISPLAY_VER(dev_priv) >= 11)
2424                 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
2425         else
2426                 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
2427
2428         if (DISPLAY_VER(dev_priv) >= 10) {
2429                 u32 color_ctl;
2430
2431                 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
2432                 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
2433         } else {
2434                 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
2435         }
2436
2437         fourcc = skl_format_to_fourcc(pixel_format,
2438                                       val & PLANE_CTL_ORDER_RGBX, alpha);
2439         fb->format = drm_format_info(fourcc);
2440
2441         tiling = val & PLANE_CTL_TILED_MASK;
2442         switch (tiling) {
2443         case PLANE_CTL_TILED_LINEAR:
2444                 fb->modifier = DRM_FORMAT_MOD_LINEAR;
2445                 break;
2446         case PLANE_CTL_TILED_X:
2447                 plane_config->tiling = I915_TILING_X;
2448                 fb->modifier = I915_FORMAT_MOD_X_TILED;
2449                 break;
2450         case PLANE_CTL_TILED_Y:
2451                 plane_config->tiling = I915_TILING_Y;
2452                 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2453                         if (DISPLAY_VER(dev_priv) >= 14)
2454                                 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
2455                         else if (DISPLAY_VER(dev_priv) >= 12)
2456                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
2457                         else
2458                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
2459                 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2460                         if (DISPLAY_VER(dev_priv) >= 14)
2461                                 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
2462                         else
2463                                 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2464                 else
2465                         fb->modifier = I915_FORMAT_MOD_Y_TILED;
2466                 break;
2467         case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
2468                 if (HAS_4TILE(dev_priv)) {
2469                         u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
2470                                       PLANE_CTL_CLEAR_COLOR_DISABLE;
2471
2472                         if ((val & rc_mask) == rc_mask)
2473                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
2474                         else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2475                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
2476                         else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2477                                 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
2478                         else
2479                                 fb->modifier = I915_FORMAT_MOD_4_TILED;
2480                 } else {
2481                         if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2482                                 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
2483                         else
2484                                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
2485                 }
2486                 break;
2487         default:
2488                 MISSING_CASE(tiling);
2489                 goto error;
2490         }
2491
2492         if (!dev_priv->params.enable_dpt &&
2493             intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
2494                 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n");
2495                 goto error;
2496         }
2497
2498         /*
2499          * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
2500          * while i915 HW rotation is clockwise, thats why this swapping.
2501          */
2502         switch (val & PLANE_CTL_ROTATE_MASK) {
2503         case PLANE_CTL_ROTATE_0:
2504                 plane_config->rotation = DRM_MODE_ROTATE_0;
2505                 break;
2506         case PLANE_CTL_ROTATE_90:
2507                 plane_config->rotation = DRM_MODE_ROTATE_270;
2508                 break;
2509         case PLANE_CTL_ROTATE_180:
2510                 plane_config->rotation = DRM_MODE_ROTATE_180;
2511                 break;
2512         case PLANE_CTL_ROTATE_270:
2513                 plane_config->rotation = DRM_MODE_ROTATE_90;
2514                 break;
2515         }
2516
2517         if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
2518                 plane_config->rotation |= DRM_MODE_REFLECT_X;
2519
2520         /* 90/270 degree rotation would require extra work */
2521         if (drm_rotation_90_or_270(plane_config->rotation))
2522                 goto error;
2523
2524         base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
2525         plane_config->base = base;
2526
2527         offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
2528         drm_WARN_ON(&dev_priv->drm, offset != 0);
2529
2530         val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2531         fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
2532         fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
2533
2534         val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
2535         stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
2536
2537         fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
2538
2539         aligned_height = intel_fb_align_height(fb, 0, fb->height);
2540
2541         plane_config->size = fb->pitches[0] * aligned_height;
2542
2543         drm_dbg_kms(&dev_priv->drm,
2544                     "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
2545                     crtc->base.name, plane->base.name, fb->width, fb->height,
2546                     fb->format->cpp[0] * 8, base, fb->pitches[0],
2547                     plane_config->size);
2548
2549         plane_config->fb = intel_fb;
2550         return;
2551
2552 error:
2553         kfree(intel_fb);
2554 }