drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <[email protected]>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Jesse Barnes <[email protected]>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_hdcp_helper.h>
  36 #include <drm/display/drm_hdmi_helper.h>
  37 #include <drm/display/drm_scdc_helper.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_crtc.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/intel_lpe_audio.h>
  42
  43 #include "g4x_hdmi.h"
  44 #include "i915_drv.h"
  45 #include "i915_reg.h"
  46 #include "intel_atomic.h"
  47 #include "intel_audio.h"
  48 #include "intel_connector.h"
  49 #include "intel_cx0_phy.h"
  50 #include "intel_ddi.h"
  51 #include "intel_de.h"
  52 #include "intel_display_types.h"
  53 #include "intel_dp.h"
  54 #include "intel_gmbus.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdcp_regs.h"
  57 #include "intel_hdmi.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_panel.h"
  60 #include "intel_snps_phy.h"
  61
  62 inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
  63 {
  64         return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
  65 }
  66
  67 static void
  68 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  69 {
  70         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
  71         u32 enabled_bits;
  72
  73         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  74
  75         drm_WARN(&dev_priv->drm,
  76                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  77                  "HDMI port enabled, expecting disabled\n");
  78 }
  79
  80 static void
  81 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  82                                      enum transcoder cpu_transcoder)
  83 {
  84         drm_WARN(&dev_priv->drm,
  85                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  86                  TRANS_DDI_FUNC_ENABLE,
  87                  "HDMI transcoder function enabled, expecting disabled\n");
  88 }
  89
  90 static u32 g4x_infoframe_index(unsigned int type)
  91 {
  92         switch (type) {
  93         case HDMI_PACKET_TYPE_GAMUT_METADATA:
  94                 return VIDEO_DIP_SELECT_GAMUT;
  95         case HDMI_INFOFRAME_TYPE_AVI:
  96                 return VIDEO_DIP_SELECT_AVI;
  97         case HDMI_INFOFRAME_TYPE_SPD:
  98                 return VIDEO_DIP_SELECT_SPD;
  99         case HDMI_INFOFRAME_TYPE_VENDOR:
 100                 return VIDEO_DIP_SELECT_VENDOR;
 101         default:
 102                 MISSING_CASE(type);
 103                 return 0;
 104         }
 105 }
 106
 107 static u32 g4x_infoframe_enable(unsigned int type)
 108 {
 109         switch (type) {
 110         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 111                 return VIDEO_DIP_ENABLE_GCP;
 112         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 113                 return VIDEO_DIP_ENABLE_GAMUT;
 114         case DP_SDP_VSC:
 115                 return 0;
 116         case HDMI_INFOFRAME_TYPE_AVI:
 117                 return VIDEO_DIP_ENABLE_AVI;
 118         case HDMI_INFOFRAME_TYPE_SPD:
 119                 return VIDEO_DIP_ENABLE_SPD;
 120         case HDMI_INFOFRAME_TYPE_VENDOR:
 121                 return VIDEO_DIP_ENABLE_VENDOR;
 122         case HDMI_INFOFRAME_TYPE_DRM:
 123                 return 0;
 124         default:
 125                 MISSING_CASE(type);
 126                 return 0;
 127         }
 128 }
 129
 130 static u32 hsw_infoframe_enable(unsigned int type)
 131 {
 132         switch (type) {
 133         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 134                 return VIDEO_DIP_ENABLE_GCP_HSW;
 135         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 136                 return VIDEO_DIP_ENABLE_GMP_HSW;
 137         case DP_SDP_VSC:
 138                 return VIDEO_DIP_ENABLE_VSC_HSW;
 139         case DP_SDP_PPS:
 140                 return VDIP_ENABLE_PPS;
 141         case HDMI_INFOFRAME_TYPE_AVI:
 142                 return VIDEO_DIP_ENABLE_AVI_HSW;
 143         case HDMI_INFOFRAME_TYPE_SPD:
 144                 return VIDEO_DIP_ENABLE_SPD_HSW;
 145         case HDMI_INFOFRAME_TYPE_VENDOR:
 146                 return VIDEO_DIP_ENABLE_VS_HSW;
 147         case HDMI_INFOFRAME_TYPE_DRM:
 148                 return VIDEO_DIP_ENABLE_DRM_GLK;
 149         default:
 150                 MISSING_CASE(type);
 151                 return 0;
 152         }
 153 }
 154
 155 static i915_reg_t
 156 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 157                  enum transcoder cpu_transcoder,
 158                  unsigned int type,
 159                  int i)
 160 {
 161         switch (type) {
 162         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 163                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 164         case DP_SDP_VSC:
 165                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 166         case DP_SDP_PPS:
 167                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 168         case HDMI_INFOFRAME_TYPE_AVI:
 169                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 170         case HDMI_INFOFRAME_TYPE_SPD:
 171                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 172         case HDMI_INFOFRAME_TYPE_VENDOR:
 173                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 174         case HDMI_INFOFRAME_TYPE_DRM:
 175                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 176         default:
 177                 MISSING_CASE(type);
 178                 return INVALID_MMIO_REG;
 179         }
 180 }
 181
 182 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 183                              unsigned int type)
 184 {
 185         switch (type) {
 186         case DP_SDP_VSC:
 187                 return VIDEO_DIP_VSC_DATA_SIZE;
 188         case DP_SDP_PPS:
 189                 return VIDEO_DIP_PPS_DATA_SIZE;
 190         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 191                 if (DISPLAY_VER(dev_priv) >= 11)
 192                         return VIDEO_DIP_GMP_DATA_SIZE;
 193                 else
 194                         return VIDEO_DIP_DATA_SIZE;
 195         default:
 196                 return VIDEO_DIP_DATA_SIZE;
 197         }
 198 }
 199
 200 static void g4x_write_infoframe(struct intel_encoder *encoder,
 201                                 const struct intel_crtc_state *crtc_state,
 202                                 unsigned int type,
 203                                 const void *frame, ssize_t len)
 204 {
 205         const u32 *data = frame;
 206         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 207         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 208         int i;
 209
 210         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 211                  "Writing DIP with CTL reg disabled\n");
 212
 213         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 214         val |= g4x_infoframe_index(type);
 215
 216         val &= ~g4x_infoframe_enable(type);
 217
 218         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 219
 220         for (i = 0; i < len; i += 4) {
 221                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 222                 data++;
 223         }
 224         /* Write every possible data byte to force correct ECC calculation. */
 225         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 226                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 227
 228         val |= g4x_infoframe_enable(type);
 229         val &= ~VIDEO_DIP_FREQ_MASK;
 230         val |= VIDEO_DIP_FREQ_VSYNC;
 231
 232         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 233         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 234 }
 235
 236 static void g4x_read_infoframe(struct intel_encoder *encoder,
 237                                const struct intel_crtc_state *crtc_state,
 238                                unsigned int type,
 239                                void *frame, ssize_t len)
 240 {
 241         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 242         u32 *data = frame;
 243         int i;
 244
 245         intel_de_rmw(dev_priv, VIDEO_DIP_CTL,
 246                      VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 247
 248         for (i = 0; i < len; i += 4)
 249                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 250 }
 251
 252 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 253                                   const struct intel_crtc_state *pipe_config)
 254 {
 255         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 256         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 257
 258         if ((val & VIDEO_DIP_ENABLE) == 0)
 259                 return 0;
 260
 261         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 262                 return 0;
 263
 264         return val & (VIDEO_DIP_ENABLE_AVI |
 265                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 266 }
 267
 268 static void ibx_write_infoframe(struct intel_encoder *encoder,
 269                                 const struct intel_crtc_state *crtc_state,
 270                                 unsigned int type,
 271                                 const void *frame, ssize_t len)
 272 {
 273         const u32 *data = frame;
 274         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 275         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 276         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 277         u32 val = intel_de_read(dev_priv, reg);
 278         int i;
 279
 280         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 281                  "Writing DIP with CTL reg disabled\n");
 282
 283         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 284         val |= g4x_infoframe_index(type);
 285
 286         val &= ~g4x_infoframe_enable(type);
 287
 288         intel_de_write(dev_priv, reg, val);
 289
 290         for (i = 0; i < len; i += 4) {
 291                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 292                                *data);
 293                 data++;
 294         }
 295         /* Write every possible data byte to force correct ECC calculation. */
 296         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 297                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 298
 299         val |= g4x_infoframe_enable(type);
 300         val &= ~VIDEO_DIP_FREQ_MASK;
 301         val |= VIDEO_DIP_FREQ_VSYNC;
 302
 303         intel_de_write(dev_priv, reg, val);
 304         intel_de_posting_read(dev_priv, reg);
 305 }
 306
 307 static void ibx_read_infoframe(struct intel_encoder *encoder,
 308                                const struct intel_crtc_state *crtc_state,
 309                                unsigned int type,
 310                                void *frame, ssize_t len)
 311 {
 312         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 313         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 314         u32 *data = frame;
 315         int i;
 316
 317         intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
 318                      VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 319
 320         for (i = 0; i < len; i += 4)
 321                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 322 }
 323
 324 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 325                                   const struct intel_crtc_state *pipe_config)
 326 {
 327         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 328         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 329         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 330         u32 val = intel_de_read(dev_priv, reg);
 331
 332         if ((val & VIDEO_DIP_ENABLE) == 0)
 333                 return 0;
 334
 335         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 336                 return 0;
 337
 338         return val & (VIDEO_DIP_ENABLE_AVI |
 339                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 340                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 341 }
 342
 343 static void cpt_write_infoframe(struct intel_encoder *encoder,
 344                                 const struct intel_crtc_state *crtc_state,
 345                                 unsigned int type,
 346                                 const void *frame, ssize_t len)
 347 {
 348         const u32 *data = frame;
 349         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 350         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 351         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 352         u32 val = intel_de_read(dev_priv, reg);
 353         int i;
 354
 355         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 356                  "Writing DIP with CTL reg disabled\n");
 357
 358         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 359         val |= g4x_infoframe_index(type);
 360
 361         /* The DIP control register spec says that we need to update the AVI
 362          * infoframe without clearing its enable bit */
 363         if (type != HDMI_INFOFRAME_TYPE_AVI)
 364                 val &= ~g4x_infoframe_enable(type);
 365
 366         intel_de_write(dev_priv, reg, val);
 367
 368         for (i = 0; i < len; i += 4) {
 369                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 370                                *data);
 371                 data++;
 372         }
 373         /* Write every possible data byte to force correct ECC calculation. */
 374         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 375                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 376
 377         val |= g4x_infoframe_enable(type);
 378         val &= ~VIDEO_DIP_FREQ_MASK;
 379         val |= VIDEO_DIP_FREQ_VSYNC;
 380
 381         intel_de_write(dev_priv, reg, val);
 382         intel_de_posting_read(dev_priv, reg);
 383 }
 384
 385 static void cpt_read_infoframe(struct intel_encoder *encoder,
 386                                const struct intel_crtc_state *crtc_state,
 387                                unsigned int type,
 388                                void *frame, ssize_t len)
 389 {
 390         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 391         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 392         u32 *data = frame;
 393         int i;
 394
 395         intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
 396                      VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 397
 398         for (i = 0; i < len; i += 4)
 399                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 400 }
 401
 402 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 403                                   const struct intel_crtc_state *pipe_config)
 404 {
 405         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 406         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 407         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 408
 409         if ((val & VIDEO_DIP_ENABLE) == 0)
 410                 return 0;
 411
 412         return val & (VIDEO_DIP_ENABLE_AVI |
 413                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 414                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 415 }
 416
 417 static void vlv_write_infoframe(struct intel_encoder *encoder,
 418                                 const struct intel_crtc_state *crtc_state,
 419                                 unsigned int type,
 420                                 const void *frame, ssize_t len)
 421 {
 422         const u32 *data = frame;
 423         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 424         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 425         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 426         u32 val = intel_de_read(dev_priv, reg);
 427         int i;
 428
 429         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 430                  "Writing DIP with CTL reg disabled\n");
 431
 432         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 433         val |= g4x_infoframe_index(type);
 434
 435         val &= ~g4x_infoframe_enable(type);
 436
 437         intel_de_write(dev_priv, reg, val);
 438
 439         for (i = 0; i < len; i += 4) {
 440                 intel_de_write(dev_priv,
 441                                VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
 442                 data++;
 443         }
 444         /* Write every possible data byte to force correct ECC calculation. */
 445         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 446                 intel_de_write(dev_priv,
 447                                VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
 448
 449         val |= g4x_infoframe_enable(type);
 450         val &= ~VIDEO_DIP_FREQ_MASK;
 451         val |= VIDEO_DIP_FREQ_VSYNC;
 452
 453         intel_de_write(dev_priv, reg, val);
 454         intel_de_posting_read(dev_priv, reg);
 455 }
 456
 457 static void vlv_read_infoframe(struct intel_encoder *encoder,
 458                                const struct intel_crtc_state *crtc_state,
 459                                unsigned int type,
 460                                void *frame, ssize_t len)
 461 {
 462         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 463         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 464         u32 *data = frame;
 465         int i;
 466
 467         intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe),
 468                      VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 469
 470         for (i = 0; i < len; i += 4)
 471                 *data++ = intel_de_read(dev_priv,
 472                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 473 }
 474
 475 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 476                                   const struct intel_crtc_state *pipe_config)
 477 {
 478         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 479         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 480         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 481
 482         if ((val & VIDEO_DIP_ENABLE) == 0)
 483                 return 0;
 484
 485         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 486                 return 0;
 487
 488         return val & (VIDEO_DIP_ENABLE_AVI |
 489                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 490                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 491 }
 492
 493 void hsw_write_infoframe(struct intel_encoder *encoder,
 494                          const struct intel_crtc_state *crtc_state,
 495                          unsigned int type,
 496                          const void *frame, ssize_t len)
 497 {
 498         const u32 *data = frame;
 499         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 500         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 501         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 502         int data_size;
 503         int i;
 504         u32 val = intel_de_read(dev_priv, ctl_reg);
 505
 506         data_size = hsw_dip_data_size(dev_priv, type);
 507
 508         drm_WARN_ON(&dev_priv->drm, len > data_size);
 509
 510         val &= ~hsw_infoframe_enable(type);
 511         intel_de_write(dev_priv, ctl_reg, val);
 512
 513         for (i = 0; i < len; i += 4) {
 514                 intel_de_write(dev_priv,
 515                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 516                                *data);
 517                 data++;
 518         }
 519         /* Write every possible data byte to force correct ECC calculation. */
 520         for (; i < data_size; i += 4)
 521                 intel_de_write(dev_priv,
 522                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 523                                0);
 524
 525         /* Wa_14013475917 */
 526         if (IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)
 527                 return;
 528
 529         val |= hsw_infoframe_enable(type);
 530         intel_de_write(dev_priv, ctl_reg, val);
 531         intel_de_posting_read(dev_priv, ctl_reg);
 532 }
 533
 534 void hsw_read_infoframe(struct intel_encoder *encoder,
 535                         const struct intel_crtc_state *crtc_state,
 536                         unsigned int type, void *frame, ssize_t len)
 537 {
 538         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 539         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 540         u32 *data = frame;
 541         int i;
 542
 543         for (i = 0; i < len; i += 4)
 544                 *data++ = intel_de_read(dev_priv,
 545                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 546 }
 547
 548 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 549                                   const struct intel_crtc_state *pipe_config)
 550 {
 551         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 552         u32 val = intel_de_read(dev_priv,
 553                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 554         u32 mask;
 555
 556         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 557                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 558                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 559
 560         if (DISPLAY_VER(dev_priv) >= 10)
 561                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 562
 563         return val & mask;
 564 }
 565
 566 static const u8 infoframe_type_to_idx[] = {
 567         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 568         HDMI_PACKET_TYPE_GAMUT_METADATA,
 569         DP_SDP_VSC,
 570         HDMI_INFOFRAME_TYPE_AVI,
 571         HDMI_INFOFRAME_TYPE_SPD,
 572         HDMI_INFOFRAME_TYPE_VENDOR,
 573         HDMI_INFOFRAME_TYPE_DRM,
 574 };
 575
 576 u32 intel_hdmi_infoframe_enable(unsigned int type)
 577 {
 578         int i;
 579
 580         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 581                 if (infoframe_type_to_idx[i] == type)
 582                         return BIT(i);
 583         }
 584
 585         return 0;
 586 }
 587
 588 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 589                                   const struct intel_crtc_state *crtc_state)
 590 {
 591         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 592         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 593         u32 val, ret = 0;
 594         int i;
 595
 596         val = dig_port->infoframes_enabled(encoder, crtc_state);
 597
 598         /* map from hardware bits to dip idx */
 599         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 600                 unsigned int type = infoframe_type_to_idx[i];
 601
 602                 if (HAS_DDI(dev_priv)) {
 603                         if (val & hsw_infoframe_enable(type))
 604                                 ret |= BIT(i);
 605                 } else {
 606                         if (val & g4x_infoframe_enable(type))
 607                                 ret |= BIT(i);
 608                 }
 609         }
 610
 611         return ret;
 612 }
 613
 614 /*
 615  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 616  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 617  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 618  * used for both technologies.
 619  *
 620  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 621  * DW1:       DB3       | DB2 | DB1 | DB0
 622  * DW2:       DB7       | DB6 | DB5 | DB4
 623  * DW3: ...
 624  *
 625  * (HB is Header Byte, DB is Data Byte)
 626  *
 627  * The hdmi pack() functions don't know about that hardware specific hole so we
 628  * trick them by giving an offset into the buffer and moving back the header
 629  * bytes by one.
 630  */
 631 static void intel_write_infoframe(struct intel_encoder *encoder,
 632                                   const struct intel_crtc_state *crtc_state,
 633                                   enum hdmi_infoframe_type type,
 634                                   const union hdmi_infoframe *frame)
 635 {
 636         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 637         u8 buffer[VIDEO_DIP_DATA_SIZE];
 638         ssize_t len;
 639
 640         if ((crtc_state->infoframes.enable &
 641              intel_hdmi_infoframe_enable(type)) == 0)
 642                 return;
 643
 644         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 645                 return;
 646
 647         /* see comment above for the reason for this offset */
 648         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 649         if (drm_WARN_ON(encoder->base.dev, len < 0))
 650                 return;
 651
 652         /* Insert the 'hole' (see big comment above) at position 3 */
 653         memmove(&buffer[0], &buffer[1], 3);
 654         buffer[3] = 0;
 655         len++;
 656
 657         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 658 }
 659
 660 void intel_read_infoframe(struct intel_encoder *encoder,
 661                           const struct intel_crtc_state *crtc_state,
 662                           enum hdmi_infoframe_type type,
 663                           union hdmi_infoframe *frame)
 664 {
 665         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 666         u8 buffer[VIDEO_DIP_DATA_SIZE];
 667         int ret;
 668
 669         if ((crtc_state->infoframes.enable &
 670              intel_hdmi_infoframe_enable(type)) == 0)
 671                 return;
 672
 673         dig_port->read_infoframe(encoder, crtc_state,
 674                                        type, buffer, sizeof(buffer));
 675
 676         /* Fill the 'hole' (see big comment above) at position 3 */
 677         memmove(&buffer[1], &buffer[0], 3);
 678
 679         /* see comment above for the reason for this offset */
 680         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 681         if (ret) {
 682                 drm_dbg_kms(encoder->base.dev,
 683                             "Failed to unpack infoframe type 0x%02x\n", type);
 684                 return;
 685         }
 686
 687         if (frame->any.type != type)
 688                 drm_dbg_kms(encoder->base.dev,
 689                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 690                             frame->any.type, type);
 691 }
 692
 693 static bool
 694 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 695                                  struct intel_crtc_state *crtc_state,
 696                                  struct drm_connector_state *conn_state)
 697 {
 698         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 699         const struct drm_display_mode *adjusted_mode =
 700                 &crtc_state->hw.adjusted_mode;
 701         struct drm_connector *connector = conn_state->connector;
 702         int ret;
 703
 704         if (!crtc_state->has_infoframe)
 705                 return true;
 706
 707         crtc_state->infoframes.enable |=
 708                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 709
 710         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 711                                                        adjusted_mode);
 712         if (ret)
 713                 return false;
 714
 715         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 716                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 717         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 718                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 719         else
 720                 frame->colorspace = HDMI_COLORSPACE_RGB;
 721
 722         drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
 723
 724         /* nonsense combination */
 725         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 726                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 727
 728         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 729                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 730                                                    adjusted_mode,
 731                                                    crtc_state->limited_color_range ?
 732                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 733                                                    HDMI_QUANTIZATION_RANGE_FULL);
 734         } else {
 735                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 736                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 737         }
 738
 739         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 740
 741         /* TODO: handle pixel repetition for YCBCR420 outputs */
 742
 743         ret = hdmi_avi_infoframe_check(frame);
 744         if (drm_WARN_ON(encoder->base.dev, ret))
 745                 return false;
 746
 747         return true;
 748 }
 749
 750 static bool
 751 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 752                                  struct intel_crtc_state *crtc_state,
 753                                  struct drm_connector_state *conn_state)
 754 {
 755         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 756         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 757         int ret;
 758
 759         if (!crtc_state->has_infoframe)
 760                 return true;
 761
 762         crtc_state->infoframes.enable |=
 763                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 764
 765         if (IS_DGFX(i915))
 766                 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
 767         else
 768                 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 769
 770         if (drm_WARN_ON(encoder->base.dev, ret))
 771                 return false;
 772
 773         frame->sdi = HDMI_SPD_SDI_PC;
 774
 775         ret = hdmi_spd_infoframe_check(frame);
 776         if (drm_WARN_ON(encoder->base.dev, ret))
 777                 return false;
 778
 779         return true;
 780 }
 781
 782 static bool
 783 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 784                                   struct intel_crtc_state *crtc_state,
 785                                   struct drm_connector_state *conn_state)
 786 {
 787         struct hdmi_vendor_infoframe *frame =
 788                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 789         const struct drm_display_info *info =
 790                 &conn_state->connector->display_info;
 791         int ret;
 792
 793         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 794                 return true;
 795
 796         crtc_state->infoframes.enable |=
 797                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 798
 799         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 800                                                           conn_state->connector,
 801                                                           &crtc_state->hw.adjusted_mode);
 802         if (drm_WARN_ON(encoder->base.dev, ret))
 803                 return false;
 804
 805         ret = hdmi_vendor_infoframe_check(frame);
 806         if (drm_WARN_ON(encoder->base.dev, ret))
 807                 return false;
 808
 809         return true;
 810 }
 811
 812 static bool
 813 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 814                                  struct intel_crtc_state *crtc_state,
 815                                  struct drm_connector_state *conn_state)
 816 {
 817         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 818         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 819         int ret;
 820
 821         if (DISPLAY_VER(dev_priv) < 10)
 822                 return true;
 823
 824         if (!crtc_state->has_infoframe)
 825                 return true;
 826
 827         if (!conn_state->hdr_output_metadata)
 828                 return true;
 829
 830         crtc_state->infoframes.enable |=
 831                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 832
 833         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 834         if (ret < 0) {
 835                 drm_dbg_kms(&dev_priv->drm,
 836                             "couldn't set HDR metadata in infoframe\n");
 837                 return false;
 838         }
 839
 840         ret = hdmi_drm_infoframe_check(frame);
 841         if (drm_WARN_ON(&dev_priv->drm, ret))
 842                 return false;
 843
 844         return true;
 845 }
 846
 847 static void g4x_set_infoframes(struct intel_encoder *encoder,
 848                                bool enable,
 849                                const struct intel_crtc_state *crtc_state,
 850                                const struct drm_connector_state *conn_state)
 851 {
 852         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 853         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 854         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 855         i915_reg_t reg = VIDEO_DIP_CTL;
 856         u32 val = intel_de_read(dev_priv, reg);
 857         u32 port = VIDEO_DIP_PORT(encoder->port);
 858
 859         assert_hdmi_port_disabled(intel_hdmi);
 860
 861         /* If the registers were not initialized yet, they might be zeroes,
 862          * which means we're selecting the AVI DIP and we're setting its
 863          * frequency to once. This seems to really confuse the HW and make
 864          * things stop working (the register spec says the AVI always needs to
 865          * be sent every VSync). So here we avoid writing to the register more
 866          * than we need and also explicitly select the AVI DIP and explicitly
 867          * set its frequency to every VSync. Avoiding to write it twice seems to
 868          * be enough to solve the problem, but being defensive shouldn't hurt us
 869          * either. */
 870         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 871
 872         if (!enable) {
 873                 if (!(val & VIDEO_DIP_ENABLE))
 874                         return;
 875                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 876                         drm_dbg_kms(&dev_priv->drm,
 877                                     "video DIP still enabled on port %c\n",
 878                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 879                         return;
 880                 }
 881                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 882                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 883                 intel_de_write(dev_priv, reg, val);
 884                 intel_de_posting_read(dev_priv, reg);
 885                 return;
 886         }
 887
 888         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 889                 if (val & VIDEO_DIP_ENABLE) {
 890                         drm_dbg_kms(&dev_priv->drm,
 891                                     "video DIP already enabled on port %c\n",
 892                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 893                         return;
 894                 }
 895                 val &= ~VIDEO_DIP_PORT_MASK;
 896                 val |= port;
 897         }
 898
 899         val |= VIDEO_DIP_ENABLE;
 900         val &= ~(VIDEO_DIP_ENABLE_AVI |
 901                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 902
 903         intel_de_write(dev_priv, reg, val);
 904         intel_de_posting_read(dev_priv, reg);
 905
 906         intel_write_infoframe(encoder, crtc_state,
 907                               HDMI_INFOFRAME_TYPE_AVI,
 908                               &crtc_state->infoframes.avi);
 909         intel_write_infoframe(encoder, crtc_state,
 910                               HDMI_INFOFRAME_TYPE_SPD,
 911                               &crtc_state->infoframes.spd);
 912         intel_write_infoframe(encoder, crtc_state,
 913                               HDMI_INFOFRAME_TYPE_VENDOR,
 914                               &crtc_state->infoframes.hdmi);
 915 }
 916
 917 /*
 918  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 919  *
 920  * From HDMI specification 1.4a:
 921  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 922  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 923  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 924  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 925  *   phase of 0
 926  */
 927 static bool gcp_default_phase_possible(int pipe_bpp,
 928                                        const struct drm_display_mode *mode)
 929 {
 930         unsigned int pixels_per_group;
 931
 932         switch (pipe_bpp) {
 933         case 30:
 934                 /* 4 pixels in 5 clocks */
 935                 pixels_per_group = 4;
 936                 break;
 937         case 36:
 938                 /* 2 pixels in 3 clocks */
 939                 pixels_per_group = 2;
 940                 break;
 941         case 48:
 942                 /* 1 pixel in 2 clocks */
 943                 pixels_per_group = 1;
 944                 break;
 945         default:
 946                 /* phase information not relevant for 8bpc */
 947                 return false;
 948         }
 949
 950         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 951                 mode->crtc_htotal % pixels_per_group == 0 &&
 952                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 953                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 954                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 955                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 956                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 957                  mode->crtc_htotal/2 % pixels_per_group == 0);
 958 }
 959
 960 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 961                                          const struct intel_crtc_state *crtc_state,
 962                                          const struct drm_connector_state *conn_state)
 963 {
 964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 965         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 966         i915_reg_t reg;
 967
 968         if ((crtc_state->infoframes.enable &
 969              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 970                 return false;
 971
 972         if (HAS_DDI(dev_priv))
 973                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 974         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 975                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 976         else if (HAS_PCH_SPLIT(dev_priv))
 977                 reg = TVIDEO_DIP_GCP(crtc->pipe);
 978         else
 979                 return false;
 980
 981         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 982
 983         return true;
 984 }
 985
 986 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 987                                    struct intel_crtc_state *crtc_state)
 988 {
 989         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 990         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 991         i915_reg_t reg;
 992
 993         if ((crtc_state->infoframes.enable &
 994              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 995                 return;
 996
 997         if (HAS_DDI(dev_priv))
 998                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 999         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1000                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1001         else if (HAS_PCH_SPLIT(dev_priv))
1002                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1003         else
1004                 return;
1005
1006         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1007 }
1008
1009 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1010                                              struct intel_crtc_state *crtc_state,
1011                                              struct drm_connector_state *conn_state)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014
1015         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1016                 return;
1017
1018         crtc_state->infoframes.enable |=
1019                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1020
1021         /* Indicate color indication for deep color mode */
1022         if (crtc_state->pipe_bpp > 24)
1023                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1024
1025         /* Enable default_phase whenever the display mode is suitably aligned */
1026         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1027                                        &crtc_state->hw.adjusted_mode))
1028                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1029 }
1030
1031 static void ibx_set_infoframes(struct intel_encoder *encoder,
1032                                bool enable,
1033                                const struct intel_crtc_state *crtc_state,
1034                                const struct drm_connector_state *conn_state)
1035 {
1036         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1037         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1038         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1039         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1040         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1041         u32 val = intel_de_read(dev_priv, reg);
1042         u32 port = VIDEO_DIP_PORT(encoder->port);
1043
1044         assert_hdmi_port_disabled(intel_hdmi);
1045
1046         /* See the big comment in g4x_set_infoframes() */
1047         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1048
1049         if (!enable) {
1050                 if (!(val & VIDEO_DIP_ENABLE))
1051                         return;
1052                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1053                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1054                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1055                 intel_de_write(dev_priv, reg, val);
1056                 intel_de_posting_read(dev_priv, reg);
1057                 return;
1058         }
1059
1060         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1061                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1062                          "DIP already enabled on port %c\n",
1063                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1064                 val &= ~VIDEO_DIP_PORT_MASK;
1065                 val |= port;
1066         }
1067
1068         val |= VIDEO_DIP_ENABLE;
1069         val &= ~(VIDEO_DIP_ENABLE_AVI |
1070                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1071                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1072
1073         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1074                 val |= VIDEO_DIP_ENABLE_GCP;
1075
1076         intel_de_write(dev_priv, reg, val);
1077         intel_de_posting_read(dev_priv, reg);
1078
1079         intel_write_infoframe(encoder, crtc_state,
1080                               HDMI_INFOFRAME_TYPE_AVI,
1081                               &crtc_state->infoframes.avi);
1082         intel_write_infoframe(encoder, crtc_state,
1083                               HDMI_INFOFRAME_TYPE_SPD,
1084                               &crtc_state->infoframes.spd);
1085         intel_write_infoframe(encoder, crtc_state,
1086                               HDMI_INFOFRAME_TYPE_VENDOR,
1087                               &crtc_state->infoframes.hdmi);
1088 }
1089
1090 static void cpt_set_infoframes(struct intel_encoder *encoder,
1091                                bool enable,
1092                                const struct intel_crtc_state *crtc_state,
1093                                const struct drm_connector_state *conn_state)
1094 {
1095         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1096         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1097         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1098         i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1099         u32 val = intel_de_read(dev_priv, reg);
1100
1101         assert_hdmi_port_disabled(intel_hdmi);
1102
1103         /* See the big comment in g4x_set_infoframes() */
1104         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1105
1106         if (!enable) {
1107                 if (!(val & VIDEO_DIP_ENABLE))
1108                         return;
1109                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1110                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1111                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1112                 intel_de_write(dev_priv, reg, val);
1113                 intel_de_posting_read(dev_priv, reg);
1114                 return;
1115         }
1116
1117         /* Set both together, unset both together: see the spec. */
1118         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1119         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1120                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1121
1122         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1123                 val |= VIDEO_DIP_ENABLE_GCP;
1124
1125         intel_de_write(dev_priv, reg, val);
1126         intel_de_posting_read(dev_priv, reg);
1127
1128         intel_write_infoframe(encoder, crtc_state,
1129                               HDMI_INFOFRAME_TYPE_AVI,
1130                               &crtc_state->infoframes.avi);
1131         intel_write_infoframe(encoder, crtc_state,
1132                               HDMI_INFOFRAME_TYPE_SPD,
1133                               &crtc_state->infoframes.spd);
1134         intel_write_infoframe(encoder, crtc_state,
1135                               HDMI_INFOFRAME_TYPE_VENDOR,
1136                               &crtc_state->infoframes.hdmi);
1137 }
1138
1139 static void vlv_set_infoframes(struct intel_encoder *encoder,
1140                                bool enable,
1141                                const struct intel_crtc_state *crtc_state,
1142                                const struct drm_connector_state *conn_state)
1143 {
1144         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1145         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1146         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1147         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1148         u32 val = intel_de_read(dev_priv, reg);
1149         u32 port = VIDEO_DIP_PORT(encoder->port);
1150
1151         assert_hdmi_port_disabled(intel_hdmi);
1152
1153         /* See the big comment in g4x_set_infoframes() */
1154         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1155
1156         if (!enable) {
1157                 if (!(val & VIDEO_DIP_ENABLE))
1158                         return;
1159                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1160                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1161                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1162                 intel_de_write(dev_priv, reg, val);
1163                 intel_de_posting_read(dev_priv, reg);
1164                 return;
1165         }
1166
1167         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1168                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1169                          "DIP already enabled on port %c\n",
1170                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1171                 val &= ~VIDEO_DIP_PORT_MASK;
1172                 val |= port;
1173         }
1174
1175         val |= VIDEO_DIP_ENABLE;
1176         val &= ~(VIDEO_DIP_ENABLE_AVI |
1177                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1178                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1179
1180         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1181                 val |= VIDEO_DIP_ENABLE_GCP;
1182
1183         intel_de_write(dev_priv, reg, val);
1184         intel_de_posting_read(dev_priv, reg);
1185
1186         intel_write_infoframe(encoder, crtc_state,
1187                               HDMI_INFOFRAME_TYPE_AVI,
1188                               &crtc_state->infoframes.avi);
1189         intel_write_infoframe(encoder, crtc_state,
1190                               HDMI_INFOFRAME_TYPE_SPD,
1191                               &crtc_state->infoframes.spd);
1192         intel_write_infoframe(encoder, crtc_state,
1193                               HDMI_INFOFRAME_TYPE_VENDOR,
1194                               &crtc_state->infoframes.hdmi);
1195 }
1196
1197 static void hsw_set_infoframes(struct intel_encoder *encoder,
1198                                bool enable,
1199                                const struct intel_crtc_state *crtc_state,
1200                                const struct drm_connector_state *conn_state)
1201 {
1202         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1203         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1204         u32 val = intel_de_read(dev_priv, reg);
1205
1206         assert_hdmi_transcoder_func_disabled(dev_priv,
1207                                              crtc_state->cpu_transcoder);
1208
1209         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1210                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1211                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1212                  VIDEO_DIP_ENABLE_DRM_GLK);
1213
1214         if (!enable) {
1215                 intel_de_write(dev_priv, reg, val);
1216                 intel_de_posting_read(dev_priv, reg);
1217                 return;
1218         }
1219
1220         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1221                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1222
1223         intel_de_write(dev_priv, reg, val);
1224         intel_de_posting_read(dev_priv, reg);
1225
1226         intel_write_infoframe(encoder, crtc_state,
1227                               HDMI_INFOFRAME_TYPE_AVI,
1228                               &crtc_state->infoframes.avi);
1229         intel_write_infoframe(encoder, crtc_state,
1230                               HDMI_INFOFRAME_TYPE_SPD,
1231                               &crtc_state->infoframes.spd);
1232         intel_write_infoframe(encoder, crtc_state,
1233                               HDMI_INFOFRAME_TYPE_VENDOR,
1234                               &crtc_state->infoframes.hdmi);
1235         intel_write_infoframe(encoder, crtc_state,
1236                               HDMI_INFOFRAME_TYPE_DRM,
1237                               &crtc_state->infoframes.drm);
1238 }
1239
1240 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1241 {
1242         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1243         struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1244
1245         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1246                 return;
1247
1248         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1249                     enable ? "Enabling" : "Disabling");
1250
1251         drm_dp_dual_mode_set_tmds_output(&dev_priv->drm,
1252                                          hdmi->dp_dual_mode.type, ddc, enable);
1253 }
1254
1255 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1256                                 unsigned int offset, void *buffer, size_t size)
1257 {
1258         struct intel_hdmi *hdmi = &dig_port->hdmi;
1259         struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1260         int ret;
1261         u8 start = offset & 0xff;
1262         struct i2c_msg msgs[] = {
1263                 {
1264                         .addr = DRM_HDCP_DDC_ADDR,
1265                         .flags = 0,
1266                         .len = 1,
1267                         .buf = &start,
1268                 },
1269                 {
1270                         .addr = DRM_HDCP_DDC_ADDR,
1271                         .flags = I2C_M_RD,
1272                         .len = size,
1273                         .buf = buffer
1274                 }
1275         };
1276         ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
1277         if (ret == ARRAY_SIZE(msgs))
1278                 return 0;
1279         return ret >= 0 ? -EIO : ret;
1280 }
1281
1282 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1283                                  unsigned int offset, void *buffer, size_t size)
1284 {
1285         struct intel_hdmi *hdmi = &dig_port->hdmi;
1286         struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1287         int ret;
1288         u8 *write_buf;
1289         struct i2c_msg msg;
1290
1291         write_buf = kzalloc(size + 1, GFP_KERNEL);
1292         if (!write_buf)
1293                 return -ENOMEM;
1294
1295         write_buf[0] = offset & 0xff;
1296         memcpy(&write_buf[1], buffer, size);
1297
1298         msg.addr = DRM_HDCP_DDC_ADDR;
1299         msg.flags = 0,
1300         msg.len = size + 1,
1301         msg.buf = write_buf;
1302
1303         ret = i2c_transfer(ddc, &msg, 1);
1304         if (ret == 1)
1305                 ret = 0;
1306         else if (ret >= 0)
1307                 ret = -EIO;
1308
1309         kfree(write_buf);
1310         return ret;
1311 }
1312
1313 static
1314 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1315                                   u8 *an)
1316 {
1317         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1318         struct intel_hdmi *hdmi = &dig_port->hdmi;
1319         struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1320         int ret;
1321
1322         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1323                                     DRM_HDCP_AN_LEN);
1324         if (ret) {
1325                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1326                             ret);
1327                 return ret;
1328         }
1329
1330         ret = intel_gmbus_output_aksv(ddc);
1331         if (ret < 0) {
1332                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1333                 return ret;
1334         }
1335         return 0;
1336 }
1337
1338 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1339                                      u8 *bksv)
1340 {
1341         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1342
1343         int ret;
1344         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1345                                    DRM_HDCP_KSV_LEN);
1346         if (ret)
1347                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1348                             ret);
1349         return ret;
1350 }
1351
1352 static
1353 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1354                                  u8 *bstatus)
1355 {
1356         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1357
1358         int ret;
1359         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1360                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1361         if (ret)
1362                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1363                             ret);
1364         return ret;
1365 }
1366
1367 static
1368 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1369                                      bool *repeater_present)
1370 {
1371         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1372         int ret;
1373         u8 val;
1374
1375         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1376         if (ret) {
1377                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1378                             ret);
1379                 return ret;
1380         }
1381         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1382         return 0;
1383 }
1384
1385 static
1386 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1387                                   u8 *ri_prime)
1388 {
1389         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1390
1391         int ret;
1392         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1393                                    ri_prime, DRM_HDCP_RI_LEN);
1394         if (ret)
1395                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1396                             ret);
1397         return ret;
1398 }
1399
1400 static
1401 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1402                                    bool *ksv_ready)
1403 {
1404         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1405         int ret;
1406         u8 val;
1407
1408         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1409         if (ret) {
1410                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1411                             ret);
1412                 return ret;
1413         }
1414         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1415         return 0;
1416 }
1417
1418 static
1419 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1420                                   int num_downstream, u8 *ksv_fifo)
1421 {
1422         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1423         int ret;
1424         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1425                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1426         if (ret) {
1427                 drm_dbg_kms(&i915->drm,
1428                             "Read ksv fifo over DDC failed (%d)\n", ret);
1429                 return ret;
1430         }
1431         return 0;
1432 }
1433
1434 static
1435 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1436                                       int i, u32 *part)
1437 {
1438         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1439         int ret;
1440
1441         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1442                 return -EINVAL;
1443
1444         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1445                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1446         if (ret)
1447                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1448                             i, ret);
1449         return ret;
1450 }
1451
1452 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1453                                            enum transcoder cpu_transcoder)
1454 {
1455         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1456         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1457         struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1458         u32 scanline;
1459         int ret;
1460
1461         for (;;) {
1462                 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1463                 if (scanline > 100 && scanline < 200)
1464                         break;
1465                 usleep_range(25, 50);
1466         }
1467
1468         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1469                                          false, TRANS_DDI_HDCP_SIGNALLING);
1470         if (ret) {
1471                 drm_err(&dev_priv->drm,
1472                         "Disable HDCP signalling failed (%d)\n", ret);
1473                 return ret;
1474         }
1475
1476         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1477                                          true, TRANS_DDI_HDCP_SIGNALLING);
1478         if (ret) {
1479                 drm_err(&dev_priv->drm,
1480                         "Enable HDCP signalling failed (%d)\n", ret);
1481                 return ret;
1482         }
1483
1484         return 0;
1485 }
1486
1487 static
1488 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1489                                       enum transcoder cpu_transcoder,
1490                                       bool enable)
1491 {
1492         struct intel_hdmi *hdmi = &dig_port->hdmi;
1493         struct intel_connector *connector = hdmi->attached_connector;
1494         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1495         int ret;
1496
1497         if (!enable)
1498                 usleep_range(6, 60); /* Bspec says >= 6us */
1499
1500         ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1501                                          cpu_transcoder, enable,
1502                                          TRANS_DDI_HDCP_SIGNALLING);
1503         if (ret) {
1504                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1505                         enable ? "Enable" : "Disable", ret);
1506                 return ret;
1507         }
1508
1509         /*
1510          * WA: To fix incorrect positioning of the window of
1511          * opportunity and enc_en signalling in KABYLAKE.
1512          */
1513         if (IS_KABYLAKE(dev_priv) && enable)
1514                 return kbl_repositioning_enc_en_signal(connector,
1515                                                        cpu_transcoder);
1516
1517         return 0;
1518 }
1519
1520 static
1521 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1522                                      struct intel_connector *connector)
1523 {
1524         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1525         enum port port = dig_port->base.port;
1526         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1527         int ret;
1528         union {
1529                 u32 reg;
1530                 u8 shim[DRM_HDCP_RI_LEN];
1531         } ri;
1532
1533         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1534         if (ret)
1535                 return false;
1536
1537         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1538
1539         /* Wait for Ri prime match */
1540         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1541                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1542                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1543                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1544                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1545                                                         port)));
1546                 return false;
1547         }
1548         return true;
1549 }
1550
1551 static
1552 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1553                                 struct intel_connector *connector)
1554 {
1555         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1556         int retry;
1557
1558         for (retry = 0; retry < 3; retry++)
1559                 if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1560                         return true;
1561
1562         drm_err(&i915->drm, "Link check failed\n");
1563         return false;
1564 }
1565
1566 struct hdcp2_hdmi_msg_timeout {
1567         u8 msg_id;
1568         u16 timeout;
1569 };
1570
1571 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1572         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1573         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1574         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1575         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1576         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1577 };
1578
1579 static
1580 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1581                                     u8 *rx_status)
1582 {
1583         return intel_hdmi_hdcp_read(dig_port,
1584                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1585                                     rx_status,
1586                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1587 }
1588
1589 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1590 {
1591         int i;
1592
1593         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1594                 if (is_paired)
1595                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1596                 else
1597                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1598         }
1599
1600         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1601                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1602                         return hdcp2_msg_timeout[i].timeout;
1603         }
1604
1605         return -EINVAL;
1606 }
1607
1608 static int
1609 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1610                               u8 msg_id, bool *msg_ready,
1611                               ssize_t *msg_sz)
1612 {
1613         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1614         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1615         int ret;
1616
1617         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1618         if (ret < 0) {
1619                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1620                             ret);
1621                 return ret;
1622         }
1623
1624         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1625                   rx_status[0]);
1626
1627         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1628                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1629                              *msg_sz);
1630         else
1631                 *msg_ready = *msg_sz;
1632
1633         return 0;
1634 }
1635
1636 static ssize_t
1637 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1638                               u8 msg_id, bool paired)
1639 {
1640         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1641         bool msg_ready = false;
1642         int timeout, ret;
1643         ssize_t msg_sz = 0;
1644
1645         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1646         if (timeout < 0)
1647                 return timeout;
1648
1649         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1650                                                              msg_id, &msg_ready,
1651                                                              &msg_sz),
1652                          !ret && msg_ready && msg_sz, timeout * 1000,
1653                          1000, 5 * 1000);
1654         if (ret)
1655                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1656                             msg_id, ret, timeout);
1657
1658         return ret ? ret : msg_sz;
1659 }
1660
1661 static
1662 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
1663                                void *buf, size_t size)
1664 {
1665         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1666         unsigned int offset;
1667
1668         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1669         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1670 }
1671
1672 static
1673 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
1674                               u8 msg_id, void *buf, size_t size)
1675 {
1676         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1677         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1678         struct intel_hdmi *hdmi = &dig_port->hdmi;
1679         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1680         unsigned int offset;
1681         ssize_t ret;
1682
1683         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1684                                             hdcp->is_paired);
1685         if (ret < 0)
1686                 return ret;
1687
1688         /*
1689          * Available msg size should be equal to or lesser than the
1690          * available buffer.
1691          */
1692         if (ret > size) {
1693                 drm_dbg_kms(&i915->drm,
1694                             "msg_sz(%zd) is more than exp size(%zu)\n",
1695                             ret, size);
1696                 return -EINVAL;
1697         }
1698
1699         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1700         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1701         if (ret)
1702                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1703                             msg_id, ret);
1704
1705         return ret;
1706 }
1707
1708 static
1709 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1710                                 struct intel_connector *connector)
1711 {
1712         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1713         int ret;
1714
1715         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1716         if (ret)
1717                 return ret;
1718
1719         /*
1720          * Re-auth request and Link Integrity Failures are represented by
1721          * same bit. i.e reauth_req.
1722          */
1723         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1724                 ret = HDCP_REAUTH_REQUEST;
1725         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1726                 ret = HDCP_TOPOLOGY_CHANGE;
1727
1728         return ret;
1729 }
1730
1731 static
1732 int intel_hdmi_hdcp2_capable(struct intel_connector *connector,
1733                              bool *capable)
1734 {
1735         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1736         u8 hdcp2_version;
1737         int ret;
1738
1739         *capable = false;
1740         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1741                                    &hdcp2_version, sizeof(hdcp2_version));
1742         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1743                 *capable = true;
1744
1745         return ret;
1746 }
1747
1748 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1749         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1750         .read_bksv = intel_hdmi_hdcp_read_bksv,
1751         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1752         .repeater_present = intel_hdmi_hdcp_repeater_present,
1753         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1754         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1755         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1756         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1757         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1758         .check_link = intel_hdmi_hdcp_check_link,
1759         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1760         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1761         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1762         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1763         .protocol = HDCP_PROTOCOL_HDMI,
1764 };
1765
1766 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1767 {
1768         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1769         int max_tmds_clock, vbt_max_tmds_clock;
1770
1771         if (DISPLAY_VER(dev_priv) >= 10)
1772                 max_tmds_clock = 594000;
1773         else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1774                 max_tmds_clock = 300000;
1775         else if (DISPLAY_VER(dev_priv) >= 5)
1776                 max_tmds_clock = 225000;
1777         else
1778                 max_tmds_clock = 165000;
1779
1780         vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1781         if (vbt_max_tmds_clock)
1782                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1783
1784         return max_tmds_clock;
1785 }
1786
1787 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1788                                 const struct drm_connector_state *conn_state)
1789 {
1790         struct intel_connector *connector = hdmi->attached_connector;
1791
1792         return connector->base.display_info.is_hdmi &&
1793                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1794 }
1795
1796 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1797 {
1798         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1799 }
1800
1801 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1802                                  bool respect_downstream_limits,
1803                                  bool has_hdmi_sink)
1804 {
1805         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1806         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1807
1808         if (respect_downstream_limits) {
1809                 struct intel_connector *connector = hdmi->attached_connector;
1810                 const struct drm_display_info *info = &connector->base.display_info;
1811
1812                 if (hdmi->dp_dual_mode.max_tmds_clock)
1813                         max_tmds_clock = min(max_tmds_clock,
1814                                              hdmi->dp_dual_mode.max_tmds_clock);
1815
1816                 if (info->max_tmds_clock)
1817                         max_tmds_clock = min(max_tmds_clock,
1818                                              info->max_tmds_clock);
1819                 else if (!has_hdmi_sink)
1820                         max_tmds_clock = min(max_tmds_clock, 165000);
1821         }
1822
1823         return max_tmds_clock;
1824 }
1825
1826 static enum drm_mode_status
1827 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1828                       int clock, bool respect_downstream_limits,
1829                       bool has_hdmi_sink)
1830 {
1831         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1832         enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1833
1834         if (clock < 25000)
1835                 return MODE_CLOCK_LOW;
1836         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1837                                           has_hdmi_sink))
1838                 return MODE_CLOCK_HIGH;
1839
1840         /* GLK DPLL can't generate 446-480 MHz */
1841         if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1842                 return MODE_CLOCK_RANGE;
1843
1844         /* BXT/GLK DPLL can't generate 223-240 MHz */
1845         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1846             clock > 223333 && clock < 240000)
1847                 return MODE_CLOCK_RANGE;
1848
1849         /* CHV DPLL can't generate 216-240 MHz */
1850         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1851                 return MODE_CLOCK_RANGE;
1852
1853         /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1854         if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1855                 return MODE_CLOCK_RANGE;
1856
1857         /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1858         if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1859                 return MODE_CLOCK_RANGE;
1860
1861         /*
1862          * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1863          * set of link rates.
1864          *
1865          * FIXME: We will hopefully get an algorithmic way of programming
1866          * the MPLLB for HDMI in the future.
1867          */
1868         if (DISPLAY_VER(dev_priv) >= 14)
1869                 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
1870         else if (IS_DG2(dev_priv))
1871                 return intel_snps_phy_check_hdmi_link_rate(clock);
1872
1873         return MODE_OK;
1874 }
1875
1876 int intel_hdmi_tmds_clock(int clock, int bpc,
1877                           enum intel_output_format sink_format)
1878 {
1879         /* YCBCR420 TMDS rate requirement is half the pixel clock */
1880         if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1881                 clock /= 2;
1882
1883         /*
1884          * Need to adjust the port link by:
1885          *  1.5x for 12bpc
1886          *  1.25x for 10bpc
1887          */
1888         return DIV_ROUND_CLOSEST(clock * bpc, 8);
1889 }
1890
1891 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1892 {
1893         switch (bpc) {
1894         case 12:
1895                 return !HAS_GMCH(i915);
1896         case 10:
1897                 return DISPLAY_VER(i915) >= 11;
1898         case 8:
1899                 return true;
1900         default:
1901                 MISSING_CASE(bpc);
1902                 return false;
1903         }
1904 }
1905
1906 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1907                                          int bpc, bool has_hdmi_sink,
1908                                          enum intel_output_format sink_format)
1909 {
1910         const struct drm_display_info *info = &connector->display_info;
1911         const struct drm_hdmi_info *hdmi = &info->hdmi;
1912
1913         switch (bpc) {
1914         case 12:
1915                 if (!has_hdmi_sink)
1916                         return false;
1917
1918                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1919                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1920                 else
1921                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1922         case 10:
1923                 if (!has_hdmi_sink)
1924                         return false;
1925
1926                 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1927                         return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1928                 else
1929                         return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1930         case 8:
1931                 return true;
1932         default:
1933                 MISSING_CASE(bpc);
1934                 return false;
1935         }
1936 }
1937
1938 static enum drm_mode_status
1939 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1940                             bool has_hdmi_sink,
1941                             enum intel_output_format sink_format)
1942 {
1943         struct drm_i915_private *i915 = to_i915(connector->dev);
1944         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1945         enum drm_mode_status status = MODE_OK;
1946         int bpc;
1947
1948         /*
1949          * Try all color depths since valid port clock range
1950          * can have holes. Any mode that can be used with at
1951          * least one color depth is accepted.
1952          */
1953         for (bpc = 12; bpc >= 8; bpc -= 2) {
1954                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1955
1956                 if (!intel_hdmi_source_bpc_possible(i915, bpc))
1957                         continue;
1958
1959                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
1960                         continue;
1961
1962                 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1963                 if (status == MODE_OK)
1964                         return MODE_OK;
1965         }
1966
1967         /* can never happen */
1968         drm_WARN_ON(&i915->drm, status == MODE_OK);
1969
1970         return status;
1971 }
1972
1973 static enum drm_mode_status
1974 intel_hdmi_mode_valid(struct drm_connector *connector,
1975                       struct drm_display_mode *mode)
1976 {
1977         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1978         struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1979         enum drm_mode_status status;
1980         int clock = mode->clock;
1981         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1982         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1983         bool ycbcr_420_only;
1984         enum intel_output_format sink_format;
1985
1986         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1987         if (status != MODE_OK)
1988                 return status;
1989
1990         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1991                 clock *= 2;
1992
1993         if (clock > max_dotclk)
1994                 return MODE_CLOCK_HIGH;
1995
1996         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1997                 if (!has_hdmi_sink)
1998                         return MODE_CLOCK_LOW;
1999                 clock *= 2;
2000         }
2001
2002         /*
2003          * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2004          * enumerated only if FRL is supported. Current platforms do not support
2005          * FRL so prune the higher resolution modes that require doctclock more
2006          * than 600MHz.
2007          */
2008         if (clock > 600000)
2009                 return MODE_CLOCK_HIGH;
2010
2011         ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2012
2013         if (ycbcr_420_only)
2014                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2015         else
2016                 sink_format = INTEL_OUTPUT_FORMAT_RGB;
2017
2018         status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2019         if (status != MODE_OK) {
2020                 if (ycbcr_420_only ||
2021                     !connector->ycbcr_420_allowed ||
2022                     !drm_mode_is_420_also(&connector->display_info, mode))
2023                         return status;
2024
2025                 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2026                 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2027                 if (status != MODE_OK)
2028                         return status;
2029         }
2030
2031         return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2032 }
2033
2034 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2035                              int bpc, bool has_hdmi_sink)
2036 {
2037         struct drm_atomic_state *state = crtc_state->uapi.state;
2038         struct drm_connector_state *connector_state;
2039         struct drm_connector *connector;
2040         int i;
2041
2042         for_each_new_connector_in_state(state, connector, connector_state, i) {
2043                 if (connector_state->crtc != crtc_state->uapi.crtc)
2044                         continue;
2045
2046                 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
2047                                                   crtc_state->sink_format))
2048                         return false;
2049         }
2050
2051         return true;
2052 }
2053
2054 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2055 {
2056         struct drm_i915_private *dev_priv =
2057                 to_i915(crtc_state->uapi.crtc->dev);
2058         const struct drm_display_mode *adjusted_mode =
2059                 &crtc_state->hw.adjusted_mode;
2060
2061         if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2062                 return false;
2063
2064         /* Display Wa_1405510057:icl,ehl */
2065         if (intel_hdmi_is_ycbcr420(crtc_state) &&
2066             bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2067             (adjusted_mode->crtc_hblank_end -
2068              adjusted_mode->crtc_hblank_start) % 8 == 2)
2069                 return false;
2070
2071         return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2072 }
2073
2074 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2075                                   struct intel_crtc_state *crtc_state,
2076                                   int clock, bool respect_downstream_limits)
2077 {
2078         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2079         int bpc;
2080
2081         /*
2082          * pipe_bpp could already be below 8bpc due to FDI
2083          * bandwidth constraints. HDMI minimum is 8bpc however.
2084          */
2085         bpc = max(crtc_state->pipe_bpp / 3, 8);
2086
2087         /*
2088          * We will never exceed downstream TMDS clock limits while
2089          * attempting deep color. If the user insists on forcing an
2090          * out of spec mode they will have to be satisfied with 8bpc.
2091          */
2092         if (!respect_downstream_limits)
2093                 bpc = 8;
2094
2095         for (; bpc >= 8; bpc -= 2) {
2096                 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
2097                                                        crtc_state->sink_format);
2098
2099                 if (hdmi_bpc_possible(crtc_state, bpc) &&
2100                     hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2101                                           respect_downstream_limits,
2102                                           crtc_state->has_hdmi_sink) == MODE_OK)
2103                         return bpc;
2104         }
2105
2106         return -EINVAL;
2107 }
2108
2109 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2110                                     struct intel_crtc_state *crtc_state,
2111                                     bool respect_downstream_limits)
2112 {
2113         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2114         const struct drm_display_mode *adjusted_mode =
2115                 &crtc_state->hw.adjusted_mode;
2116         int bpc, clock = adjusted_mode->crtc_clock;
2117
2118         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2119                 clock *= 2;
2120
2121         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2122                                      respect_downstream_limits);
2123         if (bpc < 0)
2124                 return bpc;
2125
2126         crtc_state->port_clock =
2127                 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2128
2129         /*
2130          * pipe_bpp could already be below 8bpc due to
2131          * FDI bandwidth constraints. We shouldn't bump it
2132          * back up to the HDMI minimum 8bpc in that case.
2133          */
2134         crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2135
2136         drm_dbg_kms(&i915->drm,
2137                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2138                     bpc, crtc_state->pipe_bpp);
2139
2140         return 0;
2141 }
2142
2143 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2144                                     const struct drm_connector_state *conn_state)
2145 {
2146         const struct intel_digital_connector_state *intel_conn_state =
2147                 to_intel_digital_connector_state(conn_state);
2148         const struct drm_display_mode *adjusted_mode =
2149                 &crtc_state->hw.adjusted_mode;
2150
2151         /*
2152          * Our YCbCr output is always limited range.
2153          * crtc_state->limited_color_range only applies to RGB,
2154          * and it must never be set for YCbCr or we risk setting
2155          * some conflicting bits in TRANSCONF which will mess up
2156          * the colors on the monitor.
2157          */
2158         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2159                 return false;
2160
2161         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2162                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2163                 return crtc_state->has_hdmi_sink &&
2164                         drm_default_rgb_quant_range(adjusted_mode) ==
2165                         HDMI_QUANTIZATION_RANGE_LIMITED;
2166         } else {
2167                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2168         }
2169 }
2170
2171 static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2172                                  const struct intel_crtc_state *crtc_state,
2173                                  const struct drm_connector_state *conn_state)
2174 {
2175         struct drm_connector *connector = conn_state->connector;
2176         const struct intel_digital_connector_state *intel_conn_state =
2177                 to_intel_digital_connector_state(conn_state);
2178
2179         if (!crtc_state->has_hdmi_sink)
2180                 return false;
2181
2182         if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2183                 return connector->display_info.has_audio;
2184         else
2185                 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2186 }
2187
2188 static enum intel_output_format
2189 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2190                        struct intel_connector *connector,
2191                        bool ycbcr_420_output)
2192 {
2193         if (!crtc_state->has_hdmi_sink)
2194                 return INTEL_OUTPUT_FORMAT_RGB;
2195
2196         if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2197                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2198         else
2199                 return INTEL_OUTPUT_FORMAT_RGB;
2200 }
2201
2202 static enum intel_output_format
2203 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2204 {
2205         return crtc_state->sink_format;
2206 }
2207
2208 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2209                                             struct intel_crtc_state *crtc_state,
2210                                             const struct drm_connector_state *conn_state,
2211                                             bool respect_downstream_limits)
2212 {
2213         struct intel_connector *connector = to_intel_connector(conn_state->connector);
2214         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2215         const struct drm_display_info *info = &connector->base.display_info;
2216         struct drm_i915_private *i915 = to_i915(connector->base.dev);
2217         bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2218         int ret;
2219
2220         crtc_state->sink_format =
2221                 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2222
2223         if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2224                 drm_dbg_kms(&i915->drm,
2225                             "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2226                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2227         }
2228
2229         crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2230         ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2231         if (ret) {
2232                 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2233                     !crtc_state->has_hdmi_sink ||
2234                     !connector->base.ycbcr_420_allowed ||
2235                     !drm_mode_is_420_also(info, adjusted_mode))
2236                         return ret;
2237
2238                 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2239                 crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2240                 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2241         }
2242
2243         return ret;
2244 }
2245
2246 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2247 {
2248         return crtc_state->uapi.encoder_mask &&
2249                 !is_power_of_2(crtc_state->uapi.encoder_mask);
2250 }
2251
2252 static bool source_supports_scrambling(struct intel_encoder *encoder)
2253 {
2254         /*
2255          * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
2256          * scrambling is supported.
2257          * But there seem to be cases where certain platforms that support
2258          * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
2259          * capped by VBT to less than 340MHz.
2260          *
2261          * In such cases when an HDMI2.0 sink is connected, it creates a
2262          * problem : the platform and the sink both support scrambling but the
2263          * HDMI 1.4 retimer chip doesn't.
2264          *
2265          * So go for scrambling, based on the max tmds clock taking into account,
2266          * restrictions coming from VBT.
2267          */
2268         return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2269 }
2270
2271 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2272                                       const struct intel_crtc_state *crtc_state,
2273                                       const struct drm_connector_state *conn_state)
2274 {
2275         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2276
2277         return intel_has_hdmi_sink(hdmi, conn_state) &&
2278                 !intel_hdmi_is_cloned(crtc_state);
2279 }
2280
2281 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2282                               struct intel_crtc_state *pipe_config,
2283                               struct drm_connector_state *conn_state)
2284 {
2285         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2286         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2287         struct drm_connector *connector = conn_state->connector;
2288         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2289         int ret;
2290
2291         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2292                 return -EINVAL;
2293
2294         if (!connector->interlace_allowed &&
2295             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2296                 return -EINVAL;
2297
2298         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2299
2300         if (pipe_config->has_hdmi_sink)
2301                 pipe_config->has_infoframe = true;
2302
2303         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2304                 pipe_config->pixel_multiplier = 2;
2305
2306         pipe_config->has_audio =
2307                 intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2308                 intel_audio_compute_config(encoder, pipe_config, conn_state);
2309
2310         /*
2311          * Try to respect downstream TMDS clock limits first, if
2312          * that fails assume the user might know something we don't.
2313          */
2314         ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2315         if (ret)
2316                 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2317         if (ret) {
2318                 drm_dbg_kms(&dev_priv->drm,
2319                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2320                             pipe_config->hw.adjusted_mode.crtc_clock);
2321                 return ret;
2322         }
2323
2324         if (intel_hdmi_is_ycbcr420(pipe_config)) {
2325                 ret = intel_panel_fitting(pipe_config, conn_state);
2326                 if (ret)
2327                         return ret;
2328         }
2329
2330         pipe_config->limited_color_range =
2331                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2332
2333         if (conn_state->picture_aspect_ratio)
2334                 adjusted_mode->picture_aspect_ratio =
2335                         conn_state->picture_aspect_ratio;
2336
2337         pipe_config->lane_count = 4;
2338
2339         if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2340                 if (scdc->scrambling.low_rates)
2341                         pipe_config->hdmi_scrambling = true;
2342
2343                 if (pipe_config->port_clock > 340000) {
2344                         pipe_config->hdmi_scrambling = true;
2345                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2346                 }
2347         }
2348
2349         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2350                                          conn_state);
2351
2352         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2353                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2354                 return -EINVAL;
2355         }
2356
2357         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2358                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2359                 return -EINVAL;
2360         }
2361
2362         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2363                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2364                 return -EINVAL;
2365         }
2366
2367         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2368                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2369                 return -EINVAL;
2370         }
2371
2372         return 0;
2373 }
2374
2375 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2376 {
2377         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2378
2379         /*
2380          * Give a hand to buggy BIOSen which forget to turn
2381          * the TMDS output buffers back on after a reboot.
2382          */
2383         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2384 }
2385
2386 static void
2387 intel_hdmi_unset_edid(struct drm_connector *connector)
2388 {
2389         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2390
2391         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2392         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2393
2394         drm_edid_free(to_intel_connector(connector)->detect_edid);
2395         to_intel_connector(connector)->detect_edid = NULL;
2396 }
2397
2398 static void
2399 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2400 {
2401         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2402         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2403         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2404         struct i2c_adapter *ddc = connector->ddc;
2405         enum drm_dp_dual_mode_type type;
2406
2407         type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc);
2408
2409         /*
2410          * Type 1 DVI adaptors are not required to implement any
2411          * registers, so we can't always detect their presence.
2412          * Ideally we should be able to check the state of the
2413          * CONFIG1 pin, but no such luck on our hardware.
2414          *
2415          * The only method left to us is to check the VBT to see
2416          * if the port is a dual mode capable DP port.
2417          */
2418         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2419                 if (!connector->force &&
2420                     intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2421                         drm_dbg_kms(&dev_priv->drm,
2422                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2423                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2424                 } else {
2425                         type = DRM_DP_DUAL_MODE_NONE;
2426                 }
2427         }
2428
2429         if (type == DRM_DP_DUAL_MODE_NONE)
2430                 return;
2431
2432         hdmi->dp_dual_mode.type = type;
2433         hdmi->dp_dual_mode.max_tmds_clock =
2434                 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc);
2435
2436         drm_dbg_kms(&dev_priv->drm,
2437                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2438                     drm_dp_get_dual_mode_type_name(type),
2439                     hdmi->dp_dual_mode.max_tmds_clock);
2440
2441         /* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2442         if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2443             !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2444                 drm_dbg_kms(&dev_priv->drm,
2445                             "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2446                 hdmi->dp_dual_mode.max_tmds_clock = 0;
2447         }
2448 }
2449
2450 static bool
2451 intel_hdmi_set_edid(struct drm_connector *connector)
2452 {
2453         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2454         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2455         struct i2c_adapter *ddc = connector->ddc;
2456         intel_wakeref_t wakeref;
2457         const struct drm_edid *drm_edid;
2458         bool connected = false;
2459
2460         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2461
2462         drm_edid = drm_edid_read_ddc(connector, ddc);
2463
2464         if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
2465                 drm_dbg_kms(&dev_priv->drm,
2466                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2467                 intel_gmbus_force_bit(ddc, true);
2468                 drm_edid = drm_edid_read_ddc(connector, ddc);
2469                 intel_gmbus_force_bit(ddc, false);
2470         }
2471
2472         /* Below we depend on display info having been updated */
2473         drm_edid_connector_update(connector, drm_edid);
2474
2475         to_intel_connector(connector)->detect_edid = drm_edid;
2476
2477         if (drm_edid_is_digital(drm_edid)) {
2478                 intel_hdmi_dp_dual_mode_detect(connector);
2479
2480                 connected = true;
2481         }
2482
2483         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2484
2485         cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2486                                    connector->display_info.source_physical_address);
2487
2488         return connected;
2489 }
2490
2491 static enum drm_connector_status
2492 intel_hdmi_detect(struct drm_connector *connector, bool force)
2493 {
2494         enum drm_connector_status status = connector_status_disconnected;
2495         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2496         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2497         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2498         intel_wakeref_t wakeref;
2499
2500         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2501                     connector->base.id, connector->name);
2502
2503         if (!intel_display_device_enabled(dev_priv))
2504                 return connector_status_disconnected;
2505
2506         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2507
2508         if (DISPLAY_VER(dev_priv) >= 11 &&
2509             !intel_digital_port_connected(encoder))
2510                 goto out;
2511
2512         intel_hdmi_unset_edid(connector);
2513
2514         if (intel_hdmi_set_edid(connector))
2515                 status = connector_status_connected;
2516
2517 out:
2518         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2519
2520         if (status != connector_status_connected)
2521                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2522
2523         return status;
2524 }
2525
2526 static void
2527 intel_hdmi_force(struct drm_connector *connector)
2528 {
2529         struct drm_i915_private *i915 = to_i915(connector->dev);
2530
2531         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2532                     connector->base.id, connector->name);
2533
2534         intel_hdmi_unset_edid(connector);
2535
2536         if (connector->status != connector_status_connected)
2537                 return;
2538
2539         intel_hdmi_set_edid(connector);
2540 }
2541
2542 static int intel_hdmi_get_modes(struct drm_connector *connector)
2543 {
2544         /* drm_edid_connector_update() done in ->detect() or ->force() */
2545         return drm_edid_connector_add_modes(connector);
2546 }
2547
2548 static int
2549 intel_hdmi_connector_register(struct drm_connector *connector)
2550 {
2551         int ret;
2552
2553         ret = intel_connector_register(connector);
2554         if (ret)
2555                 return ret;
2556
2557         return ret;
2558 }
2559
2560 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2561 {
2562         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2563
2564         cec_notifier_conn_unregister(n);
2565
2566         intel_connector_unregister(connector);
2567 }
2568
2569 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2570         .detect = intel_hdmi_detect,
2571         .force = intel_hdmi_force,
2572         .fill_modes = drm_helper_probe_single_connector_modes,
2573         .atomic_get_property = intel_digital_connector_atomic_get_property,
2574         .atomic_set_property = intel_digital_connector_atomic_set_property,
2575         .late_register = intel_hdmi_connector_register,
2576         .early_unregister = intel_hdmi_connector_unregister,
2577         .destroy = intel_connector_destroy,
2578         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2579         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2580 };
2581
2582 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector,
2583                                              struct drm_atomic_state *state)
2584 {
2585         struct drm_i915_private *i915 = to_i915(state->dev);
2586
2587         if (HAS_DDI(i915))
2588                 return intel_digital_connector_atomic_check(connector, state);
2589         else
2590                 return g4x_hdmi_connector_atomic_check(connector, state);
2591 }
2592
2593 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2594         .get_modes = intel_hdmi_get_modes,
2595         .mode_valid = intel_hdmi_mode_valid,
2596         .atomic_check = intel_hdmi_connector_atomic_check,
2597 };
2598
2599 static void
2600 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2601 {
2602         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2603
2604         intel_attach_force_audio_property(connector);
2605         intel_attach_broadcast_rgb_property(connector);
2606         intel_attach_aspect_ratio_property(connector);
2607
2608         intel_attach_hdmi_colorspace_property(connector);
2609         drm_connector_attach_content_type_property(connector);
2610
2611         if (DISPLAY_VER(dev_priv) >= 10)
2612                 drm_connector_attach_hdr_output_metadata_property(connector);
2613
2614         if (!HAS_GMCH(dev_priv))
2615                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2616 }
2617
2618 /*
2619  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2620  * @encoder: intel_encoder
2621  * @connector: drm_connector
2622  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2623  *  or reset the high tmds clock ratio for scrambling
2624  * @scrambling: bool to Indicate if the function needs to set or reset
2625  *  sink scrambling
2626  *
2627  * This function handles scrambling on HDMI 2.0 capable sinks.
2628  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2629  * it enables scrambling. This should be called before enabling the HDMI
2630  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2631  * detect a scrambled clock within 100 ms.
2632  *
2633  * Returns:
2634  * True on success, false on failure.
2635  */
2636 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2637                                        struct drm_connector *connector,
2638                                        bool high_tmds_clock_ratio,
2639                                        bool scrambling)
2640 {
2641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2642         struct drm_scrambling *sink_scrambling =
2643                 &connector->display_info.hdmi.scdc.scrambling;
2644
2645         if (!sink_scrambling->supported)
2646                 return true;
2647
2648         drm_dbg_kms(&dev_priv->drm,
2649                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2650                     connector->base.id, connector->name,
2651                     str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2652
2653         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2654         return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) &&
2655                 drm_scdc_set_scrambling(connector, scrambling);
2656 }
2657
2658 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2659 {
2660         u8 ddc_pin;
2661
2662         switch (port) {
2663         case PORT_B:
2664                 ddc_pin = GMBUS_PIN_DPB;
2665                 break;
2666         case PORT_C:
2667                 ddc_pin = GMBUS_PIN_DPC;
2668                 break;
2669         case PORT_D:
2670                 ddc_pin = GMBUS_PIN_DPD_CHV;
2671                 break;
2672         default:
2673                 MISSING_CASE(port);
2674                 ddc_pin = GMBUS_PIN_DPB;
2675                 break;
2676         }
2677         return ddc_pin;
2678 }
2679
2680 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2681 {
2682         u8 ddc_pin;
2683
2684         switch (port) {
2685         case PORT_B:
2686                 ddc_pin = GMBUS_PIN_1_BXT;
2687                 break;
2688         case PORT_C:
2689                 ddc_pin = GMBUS_PIN_2_BXT;
2690                 break;
2691         default:
2692                 MISSING_CASE(port);
2693                 ddc_pin = GMBUS_PIN_1_BXT;
2694                 break;
2695         }
2696         return ddc_pin;
2697 }
2698
2699 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2700                               enum port port)
2701 {
2702         u8 ddc_pin;
2703
2704         switch (port) {
2705         case PORT_B:
2706                 ddc_pin = GMBUS_PIN_1_BXT;
2707                 break;
2708         case PORT_C:
2709                 ddc_pin = GMBUS_PIN_2_BXT;
2710                 break;
2711         case PORT_D:
2712                 ddc_pin = GMBUS_PIN_4_CNP;
2713                 break;
2714         case PORT_F:
2715                 ddc_pin = GMBUS_PIN_3_BXT;
2716                 break;
2717         default:
2718                 MISSING_CASE(port);
2719                 ddc_pin = GMBUS_PIN_1_BXT;
2720                 break;
2721         }
2722         return ddc_pin;
2723 }
2724
2725 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2726 {
2727         enum phy phy = intel_port_to_phy(dev_priv, port);
2728
2729         if (intel_phy_is_combo(dev_priv, phy))
2730                 return GMBUS_PIN_1_BXT + port;
2731         else if (intel_phy_is_tc(dev_priv, phy))
2732                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2733
2734         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2735         return GMBUS_PIN_2_BXT;
2736 }
2737
2738 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2739 {
2740         enum phy phy = intel_port_to_phy(dev_priv, port);
2741         u8 ddc_pin;
2742
2743         switch (phy) {
2744         case PHY_A:
2745                 ddc_pin = GMBUS_PIN_1_BXT;
2746                 break;
2747         case PHY_B:
2748                 ddc_pin = GMBUS_PIN_2_BXT;
2749                 break;
2750         case PHY_C:
2751                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2752                 break;
2753         default:
2754                 MISSING_CASE(phy);
2755                 ddc_pin = GMBUS_PIN_1_BXT;
2756                 break;
2757         }
2758         return ddc_pin;
2759 }
2760
2761 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2762 {
2763         enum phy phy = intel_port_to_phy(dev_priv, port);
2764
2765         WARN_ON(port == PORT_C);
2766
2767         /*
2768          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2769          * final two outputs use type-c pins, even though they're actually
2770          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2771          * all outputs.
2772          */
2773         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2774                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2775
2776         return GMBUS_PIN_1_BXT + phy;
2777 }
2778
2779 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2780 {
2781         enum phy phy = intel_port_to_phy(i915, port);
2782
2783         drm_WARN_ON(&i915->drm, port == PORT_A);
2784
2785         /*
2786          * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2787          * final two outputs use type-c pins, even though they're actually
2788          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2789          * all outputs.
2790          */
2791         if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2792                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2793
2794         return GMBUS_PIN_1_BXT + phy;
2795 }
2796
2797 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2798 {
2799         return intel_port_to_phy(dev_priv, port) + 1;
2800 }
2801
2802 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2803 {
2804         enum phy phy = intel_port_to_phy(dev_priv, port);
2805
2806         WARN_ON(port == PORT_B || port == PORT_C);
2807
2808         /*
2809          * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2810          * except first combo output.
2811          */
2812         if (phy == PHY_A)
2813                 return GMBUS_PIN_1_BXT;
2814
2815         return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2816 }
2817
2818 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2819                               enum port port)
2820 {
2821         u8 ddc_pin;
2822
2823         switch (port) {
2824         case PORT_B:
2825                 ddc_pin = GMBUS_PIN_DPB;
2826                 break;
2827         case PORT_C:
2828                 ddc_pin = GMBUS_PIN_DPC;
2829                 break;
2830         case PORT_D:
2831                 ddc_pin = GMBUS_PIN_DPD;
2832                 break;
2833         default:
2834                 MISSING_CASE(port);
2835                 ddc_pin = GMBUS_PIN_DPB;
2836                 break;
2837         }
2838         return ddc_pin;
2839 }
2840
2841 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
2842 {
2843         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2844         enum port port = encoder->port;
2845         u8 ddc_pin;
2846
2847         if (IS_ALDERLAKE_S(dev_priv))
2848                 ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2849         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2850                 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2851         else if (IS_ROCKETLAKE(dev_priv))
2852                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2853         else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2854                 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2855         else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
2856                  HAS_PCH_TGP(dev_priv))
2857                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2858         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2859                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2860         else if (HAS_PCH_CNP(dev_priv))
2861                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2862         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2863                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2864         else if (IS_CHERRYVIEW(dev_priv))
2865                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2866         else
2867                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2868
2869         return ddc_pin;
2870 }
2871
2872 static struct intel_encoder *
2873 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2874 {
2875         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2876         struct intel_encoder *other;
2877
2878         for_each_intel_encoder(&i915->drm, other) {
2879                 struct intel_connector *connector;
2880
2881                 if (other == encoder)
2882                         continue;
2883
2884                 if (!intel_encoder_is_dig_port(other))
2885                         continue;
2886
2887                 connector = enc_to_dig_port(other)->hdmi.attached_connector;
2888
2889                 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
2890                         return other;
2891         }
2892
2893         return NULL;
2894 }
2895
2896 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2897 {
2898         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2899         struct intel_encoder *other;
2900         const char *source;
2901         u8 ddc_pin;
2902
2903         ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2904         source = "VBT";
2905
2906         if (!ddc_pin) {
2907                 ddc_pin = intel_hdmi_default_ddc_pin(encoder);
2908                 source = "platform default";
2909         }
2910
2911         if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
2912                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n",
2913                             encoder->base.base.id, encoder->base.name, ddc_pin);
2914                 return 0;
2915         }
2916
2917         other = get_encoder_by_ddc_pin(encoder, ddc_pin);
2918         if (other) {
2919                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n",
2920                             encoder->base.base.id, encoder->base.name, ddc_pin,
2921                             other->base.base.id, other->base.name);
2922                 return 0;
2923         }
2924
2925         drm_dbg_kms(&i915->drm,
2926                     "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n",
2927                     encoder->base.base.id, encoder->base.name,
2928                     ddc_pin, source);
2929
2930         return ddc_pin;
2931 }
2932
2933 void intel_infoframe_init(struct intel_digital_port *dig_port)
2934 {
2935         struct drm_i915_private *dev_priv =
2936                 to_i915(dig_port->base.base.dev);
2937
2938         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2939                 dig_port->write_infoframe = vlv_write_infoframe;
2940                 dig_port->read_infoframe = vlv_read_infoframe;
2941                 dig_port->set_infoframes = vlv_set_infoframes;
2942                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
2943         } else if (IS_G4X(dev_priv)) {
2944                 dig_port->write_infoframe = g4x_write_infoframe;
2945                 dig_port->read_infoframe = g4x_read_infoframe;
2946                 dig_port->set_infoframes = g4x_set_infoframes;
2947                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
2948         } else if (HAS_DDI(dev_priv)) {
2949                 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
2950                         dig_port->write_infoframe = lspcon_write_infoframe;
2951                         dig_port->read_infoframe = lspcon_read_infoframe;
2952                         dig_port->set_infoframes = lspcon_set_infoframes;
2953                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2954                 } else {
2955                         dig_port->write_infoframe = hsw_write_infoframe;
2956                         dig_port->read_infoframe = hsw_read_infoframe;
2957                         dig_port->set_infoframes = hsw_set_infoframes;
2958                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
2959                 }
2960         } else if (HAS_PCH_IBX(dev_priv)) {
2961                 dig_port->write_infoframe = ibx_write_infoframe;
2962                 dig_port->read_infoframe = ibx_read_infoframe;
2963                 dig_port->set_infoframes = ibx_set_infoframes;
2964                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
2965         } else {
2966                 dig_port->write_infoframe = cpt_write_infoframe;
2967                 dig_port->read_infoframe = cpt_read_infoframe;
2968                 dig_port->set_infoframes = cpt_set_infoframes;
2969                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
2970         }
2971 }
2972
2973 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2974                                struct intel_connector *intel_connector)
2975 {
2976         struct drm_connector *connector = &intel_connector->base;
2977         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2978         struct intel_encoder *intel_encoder = &dig_port->base;
2979         struct drm_device *dev = intel_encoder->base.dev;
2980         struct drm_i915_private *dev_priv = to_i915(dev);
2981         enum port port = intel_encoder->port;
2982         struct cec_connector_info conn_info;
2983         u8 ddc_pin;
2984
2985         drm_dbg_kms(&dev_priv->drm,
2986                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
2987                     intel_encoder->base.base.id, intel_encoder->base.name);
2988
2989         if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2990                 return;
2991
2992         if (drm_WARN(dev, dig_port->max_lanes < 4,
2993                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
2994                      dig_port->max_lanes, intel_encoder->base.base.id,
2995                      intel_encoder->base.name))
2996                 return;
2997
2998         ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
2999         if (!ddc_pin)
3000                 return;
3001
3002         drm_connector_init_with_ddc(dev, connector,
3003                                     &intel_hdmi_connector_funcs,
3004                                     DRM_MODE_CONNECTOR_HDMIA,
3005                                     intel_gmbus_get_adapter(dev_priv, ddc_pin));
3006
3007         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3008
3009         if (DISPLAY_VER(dev_priv) < 12)
3010                 connector->interlace_allowed = true;
3011
3012         connector->stereo_allowed = true;
3013
3014         if (DISPLAY_VER(dev_priv) >= 10)
3015                 connector->ycbcr_420_allowed = true;
3016
3017         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3018
3019         if (HAS_DDI(dev_priv))
3020                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3021         else
3022                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3023
3024         intel_hdmi_add_properties(intel_hdmi, connector);
3025
3026         intel_connector_attach_encoder(intel_connector, intel_encoder);
3027         intel_hdmi->attached_connector = intel_connector;
3028
3029         if (is_hdcp_supported(dev_priv, port)) {
3030                 int ret = intel_hdcp_init(intel_connector, dig_port,
3031                                           &intel_hdmi_hdcp_shim);
3032                 if (ret)
3033                         drm_dbg_kms(&dev_priv->drm,
3034                                     "HDCP init failed, skipping.\n");
3035         }
3036
3037         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3038          * 0xd.  Failure to do so will result in spurious interrupts being
3039          * generated on the port when a cable is not attached.
3040          */
3041         if (IS_G45(dev_priv)) {
3042                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
3043                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3044                                (temp & ~0xf) | 0xd);
3045         }
3046
3047         cec_fill_conn_info_from_drm(&conn_info, connector);
3048
3049         intel_hdmi->cec_notifier =
3050                 cec_notifier_conn_register(dev->dev, port_identifier(port),
3051                                            &conn_info);
3052         if (!intel_hdmi->cec_notifier)
3053                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3054 }
3055
3056 /*
3057  * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3058  * @vactive: Vactive of a display mode
3059  *
3060  * @return: appropriate dsc slice height for a given mode.
3061  */
3062 int intel_hdmi_dsc_get_slice_height(int vactive)
3063 {
3064         int slice_height;
3065
3066         /*
3067          * Slice Height determination : HDMI2.1 Section 7.7.5.2
3068          * Select smallest slice height >=96, that results in a valid PPS and
3069          * requires minimum padding lines required for final slice.
3070          *
3071          * Assumption : Vactive is even.
3072          */
3073         for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3074                 if (vactive % slice_height == 0)
3075                         return slice_height;
3076
3077         return 0;
3078 }
3079
3080 /*
3081  * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3082  * and dsc decoder capabilities
3083  *
3084  * @crtc_state: intel crtc_state
3085  * @src_max_slices: maximum slices supported by the DSC encoder
3086  * @src_max_slice_width: maximum slice width supported by DSC encoder
3087  * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3088  * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3089  *
3090  * @return: num of dsc slices that can be supported by the dsc encoder
3091  * and decoder.
3092  */
3093 int
3094 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3095                               int src_max_slices, int src_max_slice_width,
3096                               int hdmi_max_slices, int hdmi_throughput)
3097 {
3098 /* Pixel rates in KPixels/sec */
3099 #define HDMI_DSC_PEAK_PIXEL_RATE                2720000
3100 /*
3101  * Rates at which the source and sink are required to process pixels in each
3102  * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3103  */
3104 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0           340000
3105 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1           400000
3106
3107 /* Spec limits the slice width to 2720 pixels */
3108 #define MAX_HDMI_SLICE_WIDTH                    2720
3109         int kslice_adjust;
3110         int adjusted_clk_khz;
3111         int min_slices;
3112         int target_slices;
3113         int max_throughput; /* max clock freq. in khz per slice */
3114         int max_slice_width;
3115         int slice_width;
3116         int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3117
3118         if (!hdmi_throughput)
3119                 return 0;
3120
3121         /*
3122          * Slice Width determination : HDMI2.1 Section 7.7.5.1
3123          * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3124          * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3125          * dividing adjusted clock value by 10.
3126          */
3127         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3128             crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3129                 kslice_adjust = 10;
3130         else
3131                 kslice_adjust = 5;
3132
3133         /*
3134          * As per spec, the rate at which the source and the sink process
3135          * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3136          * This depends upon the pixel clock rate and output formats
3137          * (kslice adjust).
3138          * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3139          * at max 340MHz, otherwise they can be processed at max 400MHz.
3140          */
3141
3142         adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3143
3144         if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3145                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3146         else
3147                 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3148
3149         /*
3150          * Taking into account the sink's capability for maximum
3151          * clock per slice (in MHz) as read from HF-VSDB.
3152          */
3153         max_throughput = min(max_throughput, hdmi_throughput * 1000);
3154
3155         min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3156         max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3157
3158         /*
3159          * Keep on increasing the num of slices/line, starting from min_slices
3160          * per line till we get such a number, for which the slice_width is
3161          * just less than max_slice_width. The slices/line selected should be
3162          * less than or equal to the max horizontal slices that the combination
3163          * of PCON encoder and HDMI decoder can support.
3164          */
3165         slice_width = max_slice_width;
3166
3167         do {
3168                 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3169                         target_slices = 1;
3170                 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3171                         target_slices = 2;
3172                 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3173                         target_slices = 4;
3174                 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3175                         target_slices = 8;
3176                 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3177                         target_slices = 12;
3178                 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3179                         target_slices = 16;
3180                 else
3181                         return 0;
3182
3183                 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3184                 if (slice_width >= max_slice_width)
3185                         min_slices = target_slices + 1;
3186         } while (slice_width >= max_slice_width);
3187
3188         return target_slices;
3189 }
3190
3191 /*
3192  * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3193  * source and sink capabilities.
3194  *
3195  * @src_fraction_bpp: fractional bpp supported by the source
3196  * @slice_width: dsc slice width supported by the source and sink
3197  * @num_slices: num of slices supported by the source and sink
3198  * @output_format: video output format
3199  * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3200  * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3201  *
3202  * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3203  */
3204 int
3205 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3206                        int output_format, bool hdmi_all_bpp,
3207                        int hdmi_max_chunk_bytes)
3208 {
3209         int max_dsc_bpp, min_dsc_bpp;
3210         int target_bytes;
3211         bool bpp_found = false;
3212         int bpp_decrement_x16;
3213         int bpp_target;
3214         int bpp_target_x16;
3215
3216         /*
3217          * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3218          * Start with the max bpp and keep on decrementing with
3219          * fractional bpp, if supported by PCON DSC encoder
3220          *
3221          * for each bpp we check if no of bytes can be supported by HDMI sink
3222          */
3223
3224         /* Assuming: bpc as 8*/
3225         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3226                 min_dsc_bpp = 6;
3227                 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3228         } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3229                    output_format == INTEL_OUTPUT_FORMAT_RGB) {
3230                 min_dsc_bpp = 8;
3231                 max_dsc_bpp = 3 * 8; /* 3*bpc */
3232         } else {
3233                 /* Assuming 4:2:2 encoding */
3234                 min_dsc_bpp = 7;
3235                 max_dsc_bpp = 2 * 8; /* 2*bpc */
3236         }
3237
3238         /*
3239          * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3240          * Section 7.7.34 : Source shall not enable compressed Video
3241          * Transport with bpp_target settings above 12 bpp unless
3242          * DSC_all_bpp is set to 1.
3243          */
3244         if (!hdmi_all_bpp)
3245                 max_dsc_bpp = min(max_dsc_bpp, 12);
3246
3247         /*
3248          * The Sink has a limit of compressed data in bytes for a scanline,
3249          * as described in max_chunk_bytes field in HFVSDB block of edid.
3250          * The no. of bytes depend on the target bits per pixel that the
3251          * source configures. So we start with the max_bpp and calculate
3252          * the target_chunk_bytes. We keep on decrementing the target_bpp,
3253          * till we get the target_chunk_bytes just less than what the sink's
3254          * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3255          *
3256          * The decrement is according to the fractional support from PCON DSC
3257          * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3258          *
3259          * bpp_target_x16 = bpp_target * 16
3260          * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3261          * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3262          */
3263
3264         bpp_target = max_dsc_bpp;
3265
3266         /* src does not support fractional bpp implies decrement by 16 for bppx16 */
3267         if (!src_fractional_bpp)
3268                 src_fractional_bpp = 1;
3269         bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3270         bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3271
3272         while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3273                 int bpp;
3274
3275                 bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3276                 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3277                 if (target_bytes <= hdmi_max_chunk_bytes) {
3278                         bpp_found = true;
3279                         break;
3280                 }
3281                 bpp_target_x16 -= bpp_decrement_x16;
3282         }
3283         if (bpp_found)
3284                 return bpp_target_x16;
3285
3286         return 0;
3287 }