drivers/gpu/drm/i915/display/intel_fb.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2021 Intel Corporation
   4  */
   5
   6 #include <drm/drm_blend.h>
   7 #include <drm/drm_framebuffer.h>
   8 #include <drm/drm_modeset_helper.h>
   9
  10 #include <linux/dma-fence.h>
  11 #include <linux/dma-resv.h>
  12
  13 #include "i915_drv.h"
  14 #include "intel_display.h"
  15 #include "intel_display_types.h"
  16 #include "intel_dpt.h"
  17 #include "intel_fb.h"
  18 #include "intel_frontbuffer.h"
  19
  20 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
  21
  22 /*
  23  * From the Sky Lake PRM:
  24  * "The Color Control Surface (CCS) contains the compression status of
  25  *  the cache-line pairs. The compression state of the cache-line pair
  26  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
  27  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
  28  *  cache-line-pairs. CCS is always Y tiled."
  29  *
  30  * Since cache line pairs refers to horizontally adjacent cache lines,
  31  * each cache line in the CCS corresponds to an area of 32x16 cache
  32  * lines on the main surface. Since each pixel is 4 bytes, this gives
  33  * us a ratio of one byte in the CCS for each 8x16 pixels in the
  34  * main surface.
  35  */
  36 static const struct drm_format_info skl_ccs_formats[] = {
  37         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
  38           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
  39         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
  40           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
  41         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
  42           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
  43         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
  44           .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
  45 };
  46
  47 /*
  48  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
  49  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
  50  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
  51  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
  52  * the main surface.
  53  */
  54 static const struct drm_format_info gen12_ccs_formats[] = {
  55         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
  56           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  57           .hsub = 1, .vsub = 1, },
  58         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
  59           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  60           .hsub = 1, .vsub = 1, },
  61         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
  62           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  63           .hsub = 1, .vsub = 1, .has_alpha = true },
  64         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
  65           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  66           .hsub = 1, .vsub = 1, .has_alpha = true },
  67         { .format = DRM_FORMAT_YUYV, .num_planes = 2,
  68           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  69           .hsub = 2, .vsub = 1, .is_yuv = true },
  70         { .format = DRM_FORMAT_YVYU, .num_planes = 2,
  71           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  72           .hsub = 2, .vsub = 1, .is_yuv = true },
  73         { .format = DRM_FORMAT_UYVY, .num_planes = 2,
  74           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  75           .hsub = 2, .vsub = 1, .is_yuv = true },
  76         { .format = DRM_FORMAT_VYUY, .num_planes = 2,
  77           .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  78           .hsub = 2, .vsub = 1, .is_yuv = true },
  79         { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
  80           .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
  81           .hsub = 1, .vsub = 1, .is_yuv = true },
  82         { .format = DRM_FORMAT_NV12, .num_planes = 4,
  83           .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
  84           .hsub = 2, .vsub = 2, .is_yuv = true },
  85         { .format = DRM_FORMAT_P010, .num_planes = 4,
  86           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  87           .hsub = 2, .vsub = 2, .is_yuv = true },
  88         { .format = DRM_FORMAT_P012, .num_planes = 4,
  89           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  90           .hsub = 2, .vsub = 2, .is_yuv = true },
  91         { .format = DRM_FORMAT_P016, .num_planes = 4,
  92           .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
  93           .hsub = 2, .vsub = 2, .is_yuv = true },
  94 };
  95
  96 /*
  97  * Same as gen12_ccs_formats[] above, but with additional surface used
  98  * to pass Clear Color information in plane 2 with 64 bits of data.
  99  */
 100 static const struct drm_format_info gen12_ccs_cc_formats[] = {
 101         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
 102           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 103           .hsub = 1, .vsub = 1, },
 104         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
 105           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 106           .hsub = 1, .vsub = 1, },
 107         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
 108           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 109           .hsub = 1, .vsub = 1, .has_alpha = true },
 110         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
 111           .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
 112           .hsub = 1, .vsub = 1, .has_alpha = true },
 113 };
 114
 115 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
 116         { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
 117           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 118           .hsub = 1, .vsub = 1, },
 119         { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
 120           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 121           .hsub = 1, .vsub = 1, },
 122         { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
 123           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 124           .hsub = 1, .vsub = 1, .has_alpha = true },
 125         { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
 126           .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
 127           .hsub = 1, .vsub = 1, .has_alpha = true },
 128 };
 129
 130 struct intel_modifier_desc {
 131         u64 modifier;
 132         struct {
 133                 u8 from;
 134                 u8 until;
 135         } display_ver;
 136 #define DISPLAY_VER_ALL         { 0, -1 }
 137
 138         const struct drm_format_info *formats;
 139         int format_count;
 140 #define FORMAT_OVERRIDE(format_list) \
 141         .formats = format_list, \
 142         .format_count = ARRAY_SIZE(format_list)
 143
 144         u8 plane_caps;
 145
 146         struct {
 147                 u8 cc_planes:3;
 148                 u8 packed_aux_planes:4;
 149                 u8 planar_aux_planes:4;
 150         } ccs;
 151 };
 152
 153 #define INTEL_PLANE_CAP_CCS_MASK        (INTEL_PLANE_CAP_CCS_RC | \
 154                                          INTEL_PLANE_CAP_CCS_RC_CC | \
 155                                          INTEL_PLANE_CAP_CCS_MC)
 156 #define INTEL_PLANE_CAP_TILING_MASK     (INTEL_PLANE_CAP_TILING_X | \
 157                                          INTEL_PLANE_CAP_TILING_Y | \
 158                                          INTEL_PLANE_CAP_TILING_Yf | \
 159                                          INTEL_PLANE_CAP_TILING_4)
 160 #define INTEL_PLANE_CAP_TILING_NONE     0
 161
 162 static const struct intel_modifier_desc intel_modifiers[] = {
 163         {
 164                 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
 165                 .display_ver = { 14, 14 },
 166                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
 167
 168                 .ccs.packed_aux_planes = BIT(1),
 169                 .ccs.planar_aux_planes = BIT(2) | BIT(3),
 170
 171                 FORMAT_OVERRIDE(gen12_ccs_formats),
 172         }, {
 173                 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
 174                 .display_ver = { 14, 14 },
 175                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
 176
 177                 .ccs.packed_aux_planes = BIT(1),
 178
 179                 FORMAT_OVERRIDE(gen12_ccs_formats),
 180         }, {
 181                 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,
 182                 .display_ver = { 14, 14 },
 183                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
 184
 185                 .ccs.cc_planes = BIT(2),
 186                 .ccs.packed_aux_planes = BIT(1),
 187
 188                 FORMAT_OVERRIDE(gen12_ccs_cc_formats),
 189         }, {
 190                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
 191                 .display_ver = { 13, 13 },
 192                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
 193         }, {
 194                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
 195                 .display_ver = { 13, 13 },
 196                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
 197
 198                 .ccs.cc_planes = BIT(1),
 199
 200                 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
 201         }, {
 202                 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
 203                 .display_ver = { 13, 13 },
 204                 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
 205         }, {
 206                 .modifier = I915_FORMAT_MOD_4_TILED,
 207                 .display_ver = { 13, -1 },
 208                 .plane_caps = INTEL_PLANE_CAP_TILING_4,
 209         }, {
 210                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
 211                 .display_ver = { 12, 13 },
 212                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
 213
 214                 .ccs.packed_aux_planes = BIT(1),
 215                 .ccs.planar_aux_planes = BIT(2) | BIT(3),
 216
 217                 FORMAT_OVERRIDE(gen12_ccs_formats),
 218         }, {
 219                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
 220                 .display_ver = { 12, 13 },
 221                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
 222
 223                 .ccs.packed_aux_planes = BIT(1),
 224
 225                 FORMAT_OVERRIDE(gen12_ccs_formats),
 226         }, {
 227                 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
 228                 .display_ver = { 12, 13 },
 229                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,
 230
 231                 .ccs.cc_planes = BIT(2),
 232                 .ccs.packed_aux_planes = BIT(1),
 233
 234                 FORMAT_OVERRIDE(gen12_ccs_cc_formats),
 235         }, {
 236                 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
 237                 .display_ver = { 9, 11 },
 238                 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,
 239
 240                 .ccs.packed_aux_planes = BIT(1),
 241
 242                 FORMAT_OVERRIDE(skl_ccs_formats),
 243         }, {
 244                 .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
 245                 .display_ver = { 9, 11 },
 246                 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
 247
 248                 .ccs.packed_aux_planes = BIT(1),
 249
 250                 FORMAT_OVERRIDE(skl_ccs_formats),
 251         }, {
 252                 .modifier = I915_FORMAT_MOD_Yf_TILED,
 253                 .display_ver = { 9, 11 },
 254                 .plane_caps = INTEL_PLANE_CAP_TILING_Yf,
 255         }, {
 256                 .modifier = I915_FORMAT_MOD_Y_TILED,
 257                 .display_ver = { 9, 13 },
 258                 .plane_caps = INTEL_PLANE_CAP_TILING_Y,
 259         }, {
 260                 .modifier = I915_FORMAT_MOD_X_TILED,
 261                 .display_ver = DISPLAY_VER_ALL,
 262                 .plane_caps = INTEL_PLANE_CAP_TILING_X,
 263         }, {
 264                 .modifier = DRM_FORMAT_MOD_LINEAR,
 265                 .display_ver = DISPLAY_VER_ALL,
 266         },
 267 };
 268
 269 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
 270 {
 271         int i;
 272
 273         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
 274                 if (intel_modifiers[i].modifier == modifier)
 275                         return &intel_modifiers[i];
 276
 277         return NULL;
 278 }
 279
 280 static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
 281 {
 282         const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
 283
 284         if (WARN_ON(!md))
 285                 return &intel_modifiers[0];
 286
 287         return md;
 288 }
 289
 290 static const struct drm_format_info *
 291 lookup_format_info(const struct drm_format_info formats[],
 292                    int num_formats, u32 format)
 293 {
 294         int i;
 295
 296         for (i = 0; i < num_formats; i++) {
 297                 if (formats[i].format == format)
 298                         return &formats[i];
 299         }
 300
 301         return NULL;
 302 }
 303
 304 /**
 305  * intel_fb_get_format_info: Get a modifier specific format information
 306  * @cmd: FB add command structure
 307  *
 308  * Returns:
 309  * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
 310  * or %NULL if the modifier doesn't override the format.
 311  */
 312 const struct drm_format_info *
 313 intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
 314 {
 315         const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
 316
 317         if (!md || !md->formats)
 318                 return NULL;
 319
 320         return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
 321 }
 322
 323 static bool plane_caps_contain_any(u8 caps, u8 mask)
 324 {
 325         return caps & mask;
 326 }
 327
 328 static bool plane_caps_contain_all(u8 caps, u8 mask)
 329 {
 330         return (caps & mask) == mask;
 331 }
 332
 333 /**
 334  * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type
 335  * @modifier: Modifier to check
 336  *
 337  * Returns:
 338  * Returns %true if @modifier is a tiled modifier.
 339  */
 340 bool intel_fb_is_tiled_modifier(u64 modifier)
 341 {
 342         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 343                                       INTEL_PLANE_CAP_TILING_MASK);
 344 }
 345
 346 /**
 347  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
 348  * @modifier: Modifier to check
 349  *
 350  * Returns:
 351  * Returns %true if @modifier is a render, render with color clear or
 352  * media compression modifier.
 353  */
 354 bool intel_fb_is_ccs_modifier(u64 modifier)
 355 {
 356         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 357                                       INTEL_PLANE_CAP_CCS_MASK);
 358 }
 359
 360 /**
 361  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
 362  * @modifier: Modifier to check
 363  *
 364  * Returns:
 365  * Returns %true if @modifier is a render with color clear modifier.
 366  */
 367 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
 368 {
 369         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 370                                       INTEL_PLANE_CAP_CCS_RC_CC);
 371 }
 372
 373 /**
 374  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
 375  * @modifier: Modifier to check
 376  *
 377  * Returns:
 378  * Returns %true if @modifier is a media compression modifier.
 379  */
 380 bool intel_fb_is_mc_ccs_modifier(u64 modifier)
 381 {
 382         return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
 383                                       INTEL_PLANE_CAP_CCS_MC);
 384 }
 385
 386 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
 387                                              u8 display_ver_from, u8 display_ver_until)
 388 {
 389         return md->display_ver.from <= display_ver_until &&
 390                 display_ver_from <= md->display_ver.until;
 391 }
 392
 393 static bool plane_has_modifier(struct drm_i915_private *i915,
 394                                u8 plane_caps,
 395                                const struct intel_modifier_desc *md)
 396 {
 397         if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))
 398                 return false;
 399
 400         if (!plane_caps_contain_all(plane_caps, md->plane_caps))
 401                 return false;
 402
 403         /*
 404          * Separate AuxCCS and Flat CCS modifiers to be run only on platforms
 405          * where supported.
 406          */
 407         if (intel_fb_is_ccs_modifier(md->modifier) &&
 408             HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
 409                 return false;
 410
 411         return true;
 412 }
 413
 414 /**
 415  * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities
 416  * @i915: i915 device instance
 417  * @plane_caps: capabilities for the plane the modifiers are queried for
 418  *
 419  * Returns:
 420  * Returns the list of modifiers allowed by the @i915 platform and @plane_caps.
 421  * The caller must free the returned buffer.
 422  */
 423 u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
 424                                   u8 plane_caps)
 425 {
 426         u64 *list, *p;
 427         int count = 1;          /* +1 for invalid modifier terminator */
 428         int i;
 429
 430         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
 431                 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
 432                         count++;
 433         }
 434
 435         list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
 436         if (drm_WARN_ON(&i915->drm, !list))
 437                 return NULL;
 438
 439         p = list;
 440         for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
 441                 if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
 442                         *p++ = intel_modifiers[i].modifier;
 443         }
 444         *p++ = DRM_FORMAT_MOD_INVALID;
 445
 446         return list;
 447 }
 448
 449 /**
 450  * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
 451  * @plane: Plane to check the modifier support for
 452  * @modifier: The modifier to check the support for
 453  *
 454  * Returns:
 455  * %true if the @modifier is supported on @plane.
 456  */
 457 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
 458 {
 459         int i;
 460
 461         for (i = 0; i < plane->base.modifier_count; i++)
 462                 if (plane->base.modifiers[i] == modifier)
 463                         return true;
 464
 465         return false;
 466 }
 467
 468 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
 469                                      const struct drm_format_info *info)
 470 {
 471         if (!info->is_yuv)
 472                 return false;
 473
 474         if (hweight8(md->ccs.planar_aux_planes) == 2)
 475                 return info->num_planes == 4;
 476         else
 477                 return info->num_planes == 2;
 478 }
 479
 480 /**
 481  * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
 482  * @info: format to check
 483  * @modifier: modifier used with the format
 484  *
 485  * Returns:
 486  * %true if @info / @modifier is YUV semiplanar.
 487  */
 488 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
 489                                          u64 modifier)
 490 {
 491         return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
 492 }
 493
 494 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
 495                              const struct drm_format_info *format)
 496 {
 497         if (format_is_yuv_semiplanar(md, format))
 498                 return md->ccs.planar_aux_planes;
 499         else
 500                 return md->ccs.packed_aux_planes;
 501 }
 502
 503 /**
 504  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
 505  * @fb: Framebuffer
 506  * @color_plane: color plane index to check
 507  *
 508  * Returns:
 509  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
 510  */
 511 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
 512 {
 513         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 514
 515         return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
 516 }
 517
 518 /**
 519  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
 520  * @fb: Framebuffer
 521  * @color_plane: color plane index to check
 522  *
 523  * Returns:
 524  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
 525  */
 526 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
 527 {
 528         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 529
 530         return check_modifier_display_ver_range(md, 12, 14) &&
 531                ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
 532 }
 533
 534 /**
 535  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
 536  * @fb: Framebuffer
 537  *
 538  * Returns:
 539  * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
 540  * framebuffer using a render compression/color clear modifier.
 541  */
 542 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
 543 {
 544         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 545
 546         if (!md->ccs.cc_planes)
 547                 return -1;
 548
 549         drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
 550
 551         return ilog2((int)md->ccs.cc_planes);
 552 }
 553
 554 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
 555 {
 556         return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
 557 }
 558
 559 static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
 560 {
 561         return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
 562                 color_plane == 1;
 563 }
 564
 565 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
 566 {
 567         return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
 568                intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||
 569                is_gen12_ccs_cc_plane(fb, color_plane);
 570 }
 571
 572 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
 573 {
 574         drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
 575                     (main_plane && main_plane >= fb->format->num_planes / 2));
 576
 577         return fb->format->num_planes / 2 + main_plane;
 578 }
 579
 580 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
 581 {
 582         drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
 583                     ccs_plane < fb->format->num_planes / 2);
 584
 585         if (is_gen12_ccs_cc_plane(fb, ccs_plane))
 586                 return 0;
 587
 588         return ccs_plane - fb->format->num_planes / 2;
 589 }
 590
 591 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)
 592 {
 593         int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane);
 594         unsigned int main_stride = fb->base.pitches[main_plane];
 595         unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane);
 596
 597         return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;
 598 }
 599
 600 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 601 {
 602         const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 603         struct drm_i915_private *i915 = to_i915(fb->dev);
 604
 605         if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
 606                 return main_to_ccs_plane(fb, main_plane);
 607         else if (DISPLAY_VER(i915) < 11 &&
 608                  format_is_yuv_semiplanar(md, fb->format))
 609                 return 1;
 610         else
 611                 return 0;
 612 }
 613
 614 unsigned int intel_tile_size(const struct drm_i915_private *i915)
 615 {
 616         return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
 617 }
 618
 619 unsigned int
 620 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 621 {
 622         struct drm_i915_private *dev_priv = to_i915(fb->dev);
 623         unsigned int cpp = fb->format->cpp[color_plane];
 624
 625         switch (fb->modifier) {
 626         case DRM_FORMAT_MOD_LINEAR:
 627                 return intel_tile_size(dev_priv);
 628         case I915_FORMAT_MOD_X_TILED:
 629                 if (DISPLAY_VER(dev_priv) == 2)
 630                         return 128;
 631                 else
 632                         return 512;
 633         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 634         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 635         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 636         case I915_FORMAT_MOD_4_TILED:
 637                 /*
 638                  * Each 4K tile consists of 64B(8*8) subtiles, with
 639                  * same shape as Y Tile(i.e 4*16B OWords)
 640                  */
 641                 return 128;
 642         case I915_FORMAT_MOD_Y_TILED_CCS:
 643                 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 644                         return 128;
 645                 fallthrough;
 646         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
 647         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 648         case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 649         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 650         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 651         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 652                 if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
 653                     is_gen12_ccs_cc_plane(fb, color_plane))
 654                         return 64;
 655                 fallthrough;
 656         case I915_FORMAT_MOD_Y_TILED:
 657                 if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
 658                         return 128;
 659                 else
 660                         return 512;
 661         case I915_FORMAT_MOD_Yf_TILED_CCS:
 662                 if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 663                         return 128;
 664                 fallthrough;
 665         case I915_FORMAT_MOD_Yf_TILED:
 666                 switch (cpp) {
 667                 case 1:
 668                         return 64;
 669                 case 2:
 670                 case 4:
 671                         return 128;
 672                 case 8:
 673                 case 16:
 674                         return 256;
 675                 default:
 676                         MISSING_CASE(cpp);
 677                         return cpp;
 678                 }
 679                 break;
 680         default:
 681                 MISSING_CASE(fb->modifier);
 682                 return cpp;
 683         }
 684 }
 685
 686 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
 687 {
 688         return intel_tile_size(to_i915(fb->dev)) /
 689                 intel_tile_width_bytes(fb, color_plane);
 690 }
 691
 692 /*
 693  * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT
 694  * page tile size.
 695  */
 696 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
 697                             unsigned int *tile_width,
 698                             unsigned int *tile_height)
 699 {
 700         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
 701         unsigned int cpp = fb->format->cpp[color_plane];
 702
 703         *tile_width = tile_width_bytes / cpp;
 704         *tile_height = intel_tile_height(fb, color_plane);
 705 }
 706
 707 /*
 708  * Return the tile dimensions in pixel units, based on the tile block size.
 709  * The block covers the full GTT page sized tile on all tiled surfaces and
 710  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
 711  */
 712 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,
 713                                   unsigned int *tile_width,
 714                                   unsigned int *tile_height)
 715 {
 716         intel_tile_dims(fb, color_plane, tile_width, tile_height);
 717
 718         if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))
 719                 *tile_height = 1;
 720 }
 721
 722 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)
 723 {
 724         unsigned int tile_width, tile_height;
 725
 726         intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
 727
 728         return fb->pitches[color_plane] * tile_height;
 729 }
 730
 731 unsigned int
 732 intel_fb_align_height(const struct drm_framebuffer *fb,
 733                       int color_plane, unsigned int height)
 734 {
 735         unsigned int tile_height = intel_tile_height(fb, color_plane);
 736
 737         return ALIGN(height, tile_height);
 738 }
 739
 740 static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
 741 {
 742         u8 tiling_caps = lookup_modifier(fb_modifier)->plane_caps &
 743                          INTEL_PLANE_CAP_TILING_MASK;
 744
 745         switch (tiling_caps) {
 746         case INTEL_PLANE_CAP_TILING_Y:
 747                 return I915_TILING_Y;
 748         case INTEL_PLANE_CAP_TILING_X:
 749                 return I915_TILING_X;
 750         case INTEL_PLANE_CAP_TILING_4:
 751         case INTEL_PLANE_CAP_TILING_Yf:
 752         case INTEL_PLANE_CAP_TILING_NONE:
 753                 return I915_TILING_NONE;
 754         default:
 755                 MISSING_CASE(tiling_caps);
 756                 return I915_TILING_NONE;
 757         }
 758 }
 759
 760 bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
 761 {
 762         return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR;
 763 }
 764
 765 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
 766 {
 767         return fb && to_i915(fb->dev)->params.enable_dpt &&
 768                 intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
 769 }
 770
 771 unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
 772 {
 773         if (IS_I830(i915))
 774                 return 16 * 1024;
 775         else if (IS_I85X(i915))
 776                 return 256;
 777         else if (IS_I845G(i915) || IS_I865G(i915))
 778                 return 32;
 779         else
 780                 return 4 * 1024;
 781 }
 782
 783 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
 784 {
 785         if (DISPLAY_VER(dev_priv) >= 9)
 786                 return 256 * 1024;
 787         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
 788                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 789                 return 128 * 1024;
 790         else if (DISPLAY_VER(dev_priv) >= 4)
 791                 return 4 * 1024;
 792         else
 793                 return 0;
 794 }
 795
 796 unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 797                                   int color_plane)
 798 {
 799         struct drm_i915_private *dev_priv = to_i915(fb->dev);
 800
 801         if (intel_fb_uses_dpt(fb))
 802                 return 512 * 4096;
 803
 804         /* AUX_DIST needs only 4K alignment */
 805         if (intel_fb_is_ccs_aux_plane(fb, color_plane))
 806                 return 4096;
 807
 808         if (is_semiplanar_uv_plane(fb, color_plane)) {
 809                 /*
 810                  * TODO: cross-check wrt. the bspec stride in bytes * 64 bytes
 811                  * alignment for linear UV planes on all platforms.
 812                  */
 813                 if (DISPLAY_VER(dev_priv) >= 12) {
 814                         if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
 815                                 return intel_linear_alignment(dev_priv);
 816
 817                         return intel_tile_row_size(fb, color_plane);
 818                 }
 819
 820                 return 4096;
 821         }
 822
 823         drm_WARN_ON(&dev_priv->drm, color_plane != 0);
 824
 825         switch (fb->modifier) {
 826         case DRM_FORMAT_MOD_LINEAR:
 827                 return intel_linear_alignment(dev_priv);
 828         case I915_FORMAT_MOD_X_TILED:
 829                 if (HAS_ASYNC_FLIPS(dev_priv))
 830                         return 256 * 1024;
 831                 return 0;
 832         case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
 833         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
 834         case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 835         case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
 836         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
 837         case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
 838                 return 16 * 1024;
 839         case I915_FORMAT_MOD_Y_TILED_CCS:
 840         case I915_FORMAT_MOD_Yf_TILED_CCS:
 841         case I915_FORMAT_MOD_Y_TILED:
 842         case I915_FORMAT_MOD_4_TILED:
 843         case I915_FORMAT_MOD_Yf_TILED:
 844                 return 1 * 1024 * 1024;
 845         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
 846         case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 847         case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 848                 return 16 * 1024;
 849         default:
 850                 MISSING_CASE(fb->modifier);
 851                 return 0;
 852         }
 853 }
 854
 855 void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
 856                                     const struct drm_framebuffer *fb,
 857                                     int color_plane)
 858 {
 859         int main_plane;
 860
 861         if (color_plane == 0) {
 862                 *hsub = 1;
 863                 *vsub = 1;
 864
 865                 return;
 866         }
 867
 868         /*
 869          * TODO: Deduct the subsampling from the char block for all CCS
 870          * formats and planes.
 871          */
 872         if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {
 873                 *hsub = fb->format->hsub;
 874                 *vsub = fb->format->vsub;
 875
 876                 return;
 877         }
 878
 879         main_plane = skl_ccs_to_main_plane(fb, color_plane);
 880         *hsub = drm_format_info_block_width(fb->format, color_plane) /
 881                 drm_format_info_block_width(fb->format, main_plane);
 882
 883         /*
 884          * The min stride check in the core framebuffer_check() function
 885          * assumes that format->hsub applies to every plane except for the
 886          * first plane. That's incorrect for the CCS AUX plane of the first
 887          * plane, but for the above check to pass we must define the block
 888          * width with that subsampling applied to it. Adjust the width here
 889          * accordingly, so we can calculate the actual subsampling factor.
 890          */
 891         if (main_plane == 0)
 892                 *hsub *= fb->format->hsub;
 893
 894         *vsub = 32;
 895 }
 896
 897 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
 898 {
 899         int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ?
 900                          skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
 901         unsigned int main_width = fb->base.width;
 902         unsigned int main_height = fb->base.height;
 903         int main_hsub, main_vsub;
 904         int hsub, vsub;
 905
 906         intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);
 907         intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);
 908
 909         *w = DIV_ROUND_UP(main_width, main_hsub * hsub);
 910         *h = DIV_ROUND_UP(main_height, main_vsub * vsub);
 911 }
 912
 913 static u32 intel_adjust_tile_offset(int *x, int *y,
 914                                     unsigned int tile_width,
 915                                     unsigned int tile_height,
 916                                     unsigned int tile_size,
 917                                     unsigned int pitch_tiles,
 918                                     u32 old_offset,
 919                                     u32 new_offset)
 920 {
 921         unsigned int pitch_pixels = pitch_tiles * tile_width;
 922         unsigned int tiles;
 923
 924         WARN_ON(old_offset & (tile_size - 1));
 925         WARN_ON(new_offset & (tile_size - 1));
 926         WARN_ON(new_offset > old_offset);
 927
 928         tiles = (old_offset - new_offset) / tile_size;
 929
 930         *y += tiles / pitch_tiles * tile_height;
 931         *x += tiles % pitch_tiles * tile_width;
 932
 933         /* minimize x in case it got needlessly big */
 934         *y += *x / pitch_pixels * tile_height;
 935         *x %= pitch_pixels;
 936
 937         return new_offset;
 938 }
 939
 940 static u32 intel_adjust_linear_offset(int *x, int *y,
 941                                       unsigned int cpp,
 942                                       unsigned int pitch,
 943                                       u32 old_offset,
 944                                       u32 new_offset)
 945 {
 946         old_offset += *y * pitch + *x * cpp;
 947
 948         *y = (old_offset - new_offset) / pitch;
 949         *x = ((old_offset - new_offset) - *y * pitch) / cpp;
 950
 951         return new_offset;
 952 }
 953
 954 static u32 intel_adjust_aligned_offset(int *x, int *y,
 955                                        const struct drm_framebuffer *fb,
 956                                        int color_plane,
 957                                        unsigned int rotation,
 958                                        unsigned int pitch,
 959                                        u32 old_offset, u32 new_offset)
 960 {
 961         struct drm_i915_private *i915 = to_i915(fb->dev);
 962         unsigned int cpp = fb->format->cpp[color_plane];
 963
 964         drm_WARN_ON(&i915->drm, new_offset > old_offset);
 965
 966         if (!is_surface_linear(fb, color_plane)) {
 967                 unsigned int tile_size, tile_width, tile_height;
 968                 unsigned int pitch_tiles;
 969
 970                 tile_size = intel_tile_size(i915);
 971                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
 972
 973                 if (drm_rotation_90_or_270(rotation)) {
 974                         pitch_tiles = pitch / tile_height;
 975                         swap(tile_width, tile_height);
 976                 } else {
 977                         pitch_tiles = pitch / (tile_width * cpp);
 978                 }
 979
 980                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
 981                                          tile_size, pitch_tiles,
 982                                          old_offset, new_offset);
 983         } else {
 984                 intel_adjust_linear_offset(x, y, cpp, pitch,
 985                                            old_offset, new_offset);
 986         }
 987
 988         return new_offset;
 989 }
 990
 991 /*
 992  * Adjust the tile offset by moving the difference into
 993  * the x/y offsets.
 994  */
 995 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
 996                                       const struct intel_plane_state *state,
 997                                       int color_plane,
 998                                       u32 old_offset, u32 new_offset)
 999 {
1000         return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
1001                                            state->hw.rotation,
1002                                            state->view.color_plane[color_plane].mapping_stride,
1003                                            old_offset, new_offset);
1004 }
1005
1006 /*
1007  * Computes the aligned offset to the base tile and adjusts
1008  * x, y. bytes per pixel is assumed to be a power-of-two.
1009  *
1010  * In the 90/270 rotated case, x and y are assumed
1011  * to be already rotated to match the rotated GTT view, and
1012  * pitch is the tile_height aligned framebuffer height.
1013  *
1014  * This function is used when computing the derived information
1015  * under intel_framebuffer, so using any of that information
1016  * here is not allowed. Anything under drm_framebuffer can be
1017  * used. This is why the user has to pass in the pitch since it
1018  * is specified in the rotated orientation.
1019  */
1020 static u32 intel_compute_aligned_offset(struct drm_i915_private *i915,
1021                                         int *x, int *y,
1022                                         const struct drm_framebuffer *fb,
1023                                         int color_plane,
1024                                         unsigned int pitch,
1025                                         unsigned int rotation,
1026                                         u32 alignment)
1027 {
1028         unsigned int cpp = fb->format->cpp[color_plane];
1029         u32 offset, offset_aligned;
1030
1031         if (!is_surface_linear(fb, color_plane)) {
1032                 unsigned int tile_size, tile_width, tile_height;
1033                 unsigned int tile_rows, tiles, pitch_tiles;
1034
1035                 tile_size = intel_tile_size(i915);
1036                 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
1037
1038                 if (drm_rotation_90_or_270(rotation)) {
1039                         pitch_tiles = pitch / tile_height;
1040                         swap(tile_width, tile_height);
1041                 } else {
1042                         pitch_tiles = pitch / (tile_width * cpp);
1043                 }
1044
1045                 tile_rows = *y / tile_height;
1046                 *y %= tile_height;
1047
1048                 tiles = *x / tile_width;
1049                 *x %= tile_width;
1050
1051                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1052
1053                 offset_aligned = offset;
1054                 if (alignment)
1055                         offset_aligned = rounddown(offset_aligned, alignment);
1056
1057                 intel_adjust_tile_offset(x, y, tile_width, tile_height,
1058                                          tile_size, pitch_tiles,
1059                                          offset, offset_aligned);
1060         } else {
1061                 offset = *y * pitch + *x * cpp;
1062                 offset_aligned = offset;
1063                 if (alignment) {
1064                         offset_aligned = rounddown(offset_aligned, alignment);
1065                         *y = (offset % alignment) / pitch;
1066                         *x = ((offset % alignment) - *y * pitch) / cpp;
1067                 } else {
1068                         *y = *x = 0;
1069                 }
1070         }
1071
1072         return offset_aligned;
1073 }
1074
1075 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1076                                        const struct intel_plane_state *state,
1077                                        int color_plane)
1078 {
1079         struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane);
1080         struct drm_i915_private *i915 = to_i915(intel_plane->base.dev);
1081         const struct drm_framebuffer *fb = state->hw.fb;
1082         unsigned int rotation = state->hw.rotation;
1083         int pitch = state->view.color_plane[color_plane].mapping_stride;
1084         u32 alignment;
1085
1086         if (intel_plane->id == PLANE_CURSOR)
1087                 alignment = intel_cursor_alignment(i915);
1088         else
1089                 alignment = intel_surf_alignment(fb, color_plane);
1090
1091         return intel_compute_aligned_offset(i915, x, y, fb, color_plane,
1092                                             pitch, rotation, alignment);
1093 }
1094
1095 /* Convert the fb->offset[] into x/y offsets */
1096 static int intel_fb_offset_to_xy(int *x, int *y,
1097                                  const struct drm_framebuffer *fb,
1098                                  int color_plane)
1099 {
1100         struct drm_i915_private *i915 = to_i915(fb->dev);
1101         unsigned int height;
1102         u32 alignment;
1103
1104         if (DISPLAY_VER(i915) >= 12 &&
1105             !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) &&
1106             is_semiplanar_uv_plane(fb, color_plane))
1107                 alignment = intel_tile_row_size(fb, color_plane);
1108         else if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1109                 alignment = intel_tile_size(i915);
1110         else
1111                 alignment = 0;
1112
1113         if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1114                 drm_dbg_kms(&i915->drm,
1115                             "Misaligned offset 0x%08x for color plane %d\n",
1116                             fb->offsets[color_plane], color_plane);
1117                 return -EINVAL;
1118         }
1119
1120         height = drm_format_info_plane_height(fb->format, fb->height, color_plane);
1121         height = ALIGN(height, intel_tile_height(fb, color_plane));
1122
1123         /* Catch potential overflows early */
1124         if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),
1125                             fb->offsets[color_plane])) {
1126                 drm_dbg_kms(&i915->drm,
1127                             "Bad offset 0x%08x or pitch %d for color plane %d\n",
1128                             fb->offsets[color_plane], fb->pitches[color_plane],
1129                             color_plane);
1130                 return -ERANGE;
1131         }
1132
1133         *x = 0;
1134         *y = 0;
1135
1136         intel_adjust_aligned_offset(x, y,
1137                                     fb, color_plane, DRM_MODE_ROTATE_0,
1138                                     fb->pitches[color_plane],
1139                                     fb->offsets[color_plane], 0);
1140
1141         return 0;
1142 }
1143
1144 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1145 {
1146         struct drm_i915_private *i915 = to_i915(fb->dev);
1147         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1148         int main_plane;
1149         int hsub, vsub;
1150         int tile_width, tile_height;
1151         int ccs_x, ccs_y;
1152         int main_x, main_y;
1153
1154         if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1155                 return 0;
1156
1157         /*
1158          * While all the tile dimensions are based on a 2k or 4k GTT page size
1159          * here the main and CCS coordinates must match only within a (64 byte
1160          * on TGL+) block inside the tile.
1161          */
1162         intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height);
1163         intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1164
1165         tile_width *= hsub;
1166         tile_height *= vsub;
1167
1168         ccs_x = (x * hsub) % tile_width;
1169         ccs_y = (y * vsub) % tile_height;
1170
1171         main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1172         main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;
1173         main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;
1174
1175         /*
1176          * CCS doesn't have its own x/y offset register, so the intra CCS tile
1177          * x/y offsets must match between CCS and the main surface.
1178          */
1179         if (main_x != ccs_x || main_y != ccs_y) {
1180                 drm_dbg_kms(&i915->drm,
1181                               "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1182                               main_x, main_y,
1183                               ccs_x, ccs_y,
1184                               intel_fb->normal_view.color_plane[main_plane].x,
1185                               intel_fb->normal_view.color_plane[main_plane].y,
1186                               x, y);
1187                 return -EINVAL;
1188         }
1189
1190         return 0;
1191 }
1192
1193 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1194 {
1195         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1196         struct drm_i915_private *i915 = to_i915(plane->base.dev);
1197         const struct drm_framebuffer *fb = plane_state->hw.fb;
1198         int i;
1199
1200         /* We don't want to deal with remapping with cursors */
1201         if (plane->id == PLANE_CURSOR)
1202                 return false;
1203
1204         /*
1205          * The display engine limits already match/exceed the
1206          * render engine limits, so not much point in remapping.
1207          * Would also need to deal with the fence POT alignment
1208          * and gen2 2KiB GTT tile size.
1209          */
1210         if (DISPLAY_VER(i915) < 4)
1211                 return false;
1212
1213         /*
1214          * The new CCS hash mode isn't compatible with remapping as
1215          * the virtual address of the pages affects the compressed data.
1216          */
1217         if (intel_fb_is_ccs_modifier(fb->modifier))
1218                 return false;
1219
1220         /* Linear needs a page aligned stride for remapping */
1221         if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1222                 unsigned int alignment = intel_tile_size(i915) - 1;
1223
1224                 for (i = 0; i < fb->format->num_planes; i++) {
1225                         if (fb->pitches[i] & alignment)
1226                                 return false;
1227                 }
1228         }
1229
1230         return true;
1231 }
1232
1233 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
1234 {
1235         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1236
1237         return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1238                 intel_fb_uses_dpt(&fb->base);
1239 }
1240
1241 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
1242 {
1243         if (drm_rotation_90_or_270(rotation))
1244                 return fb->rotated_view.color_plane[color_plane].mapping_stride;
1245         else if (intel_fb_needs_pot_stride_remap(fb))
1246                 return fb->remapped_view.color_plane[color_plane].mapping_stride;
1247         else
1248                 return fb->normal_view.color_plane[color_plane].mapping_stride;
1249 }
1250
1251 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1252 {
1253         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1254         const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
1255         unsigned int rotation = plane_state->hw.rotation;
1256         u32 stride, max_stride;
1257
1258         /*
1259          * No remapping for invisible planes since we don't have
1260          * an actual source viewport to remap.
1261          */
1262         if (!plane_state->uapi.visible)
1263                 return false;
1264
1265         if (!intel_plane_can_remap(plane_state))
1266                 return false;
1267
1268         /*
1269          * FIXME: aux plane limits on gen9+ are
1270          * unclear in Bspec, for now no checking.
1271          */
1272         stride = intel_fb_pitch(fb, 0, rotation);
1273         max_stride = plane->max_stride(plane, fb->base.format->format,
1274                                        fb->base.modifier, rotation);
1275
1276         return stride > max_stride;
1277 }
1278
1279 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,
1280                                       int plane_width, int *x, int *y)
1281 {
1282         struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1283         int ret;
1284
1285         ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane);
1286         if (ret) {
1287                 drm_dbg_kms(fb->base.dev,
1288                             "bad fb plane %d offset: 0x%x\n",
1289                             color_plane, fb->base.offsets[color_plane]);
1290                 return ret;
1291         }
1292
1293         ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y);
1294         if (ret)
1295                 return ret;
1296
1297         /*
1298          * The fence (if used) is aligned to the start of the object
1299          * so having the framebuffer wrap around across the edge of the
1300          * fenced region doesn't really work. We have no API to configure
1301          * the fence start offset within the object (nor could we probably
1302          * on gen2/3). So it's just easier if we just require that the
1303          * fb layout agrees with the fence layout. We already check that the
1304          * fb stride matches the fence stride elsewhere.
1305          */
1306         if (color_plane == 0 && i915_gem_object_is_tiled(obj) &&
1307             (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {
1308                 drm_dbg_kms(fb->base.dev,
1309                             "bad fb plane %d offset: 0x%x\n",
1310                             color_plane, fb->base.offsets[color_plane]);
1311                 return -EINVAL;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)
1318 {
1319         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1320         unsigned int tile_size = intel_tile_size(i915);
1321         u32 offset;
1322
1323         offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane,
1324                                               fb->base.pitches[color_plane],
1325                                               DRM_MODE_ROTATE_0,
1326                                               tile_size);
1327
1328         return offset / tile_size;
1329 }
1330
1331 struct fb_plane_view_dims {
1332         unsigned int width, height;
1333         unsigned int tile_width, tile_height;
1334 };
1335
1336 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,
1337                                  unsigned int width, unsigned int height,
1338                                  struct fb_plane_view_dims *dims)
1339 {
1340         dims->width = width;
1341         dims->height = height;
1342
1343         intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height);
1344 }
1345
1346 static unsigned int
1347 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1348                             const struct fb_plane_view_dims *dims)
1349 {
1350         return DIV_ROUND_UP(fb->base.pitches[color_plane],
1351                             dims->tile_width * fb->base.format->cpp[color_plane]);
1352 }
1353
1354 static unsigned int
1355 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1356                             unsigned int pitch_tiles)
1357 {
1358         if (intel_fb_needs_pot_stride_remap(fb)) {
1359                 /*
1360                  * ADL_P, the only platform needing a POT stride has a minimum
1361                  * of 8 main surface tiles.
1362                  */
1363                 return roundup_pow_of_two(max(pitch_tiles, 8u));
1364         } else {
1365                 return pitch_tiles;
1366         }
1367 }
1368
1369 static unsigned int
1370 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
1371                           unsigned int tile_width,
1372                           unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
1373 {
1374         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1375         unsigned int stride_tiles;
1376
1377         if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1378             src_stride_tiles < dst_stride_tiles)
1379                 stride_tiles = src_stride_tiles;
1380         else
1381                 stride_tiles = dst_stride_tiles;
1382
1383         return stride_tiles * tile_width * fb->base.format->cpp[color_plane];
1384 }
1385
1386 static unsigned int
1387 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,
1388                        const struct fb_plane_view_dims *dims,
1389                        int x)
1390 {
1391         return DIV_ROUND_UP(x + dims->width, dims->tile_width);
1392 }
1393
1394 static unsigned int
1395 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,
1396                         const struct fb_plane_view_dims *dims,
1397                         int y)
1398 {
1399         return DIV_ROUND_UP(y + dims->height, dims->tile_height);
1400 }
1401
1402 static unsigned int
1403 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,
1404                         const struct fb_plane_view_dims *dims,
1405                         int x, int y)
1406 {
1407         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1408         unsigned int size;
1409
1410         size = (y + dims->height) * fb->base.pitches[color_plane] +
1411                 x * fb->base.format->cpp[color_plane];
1412
1413         return DIV_ROUND_UP(size, intel_tile_size(i915));
1414 }
1415
1416 #define assign_chk_ovf(i915, var, val) ({ \
1417         drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \
1418         (var) = (val); \
1419 })
1420
1421 #define assign_bfld_chk_ovf(i915, var, val) ({ \
1422         (var) = (val); \
1423         drm_WARN_ON(&(i915)->drm, (var) != (val)); \
1424         (var); \
1425 })
1426
1427 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,
1428                                  const struct fb_plane_view_dims *dims,
1429                                  u32 obj_offset, u32 gtt_offset, int x, int y,
1430                                  struct intel_fb_view *view)
1431 {
1432         struct drm_i915_private *i915 = to_i915(fb->base.dev);
1433         struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];
1434         struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];
1435         unsigned int tile_width = dims->tile_width;
1436         unsigned int tile_height = dims->tile_height;
1437         unsigned int tile_size = intel_tile_size(i915);
1438         struct drm_rect r;
1439         u32 size = 0;
1440
1441         assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset);
1442
1443         if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) {
1444                 remap_info->linear = 1;
1445
1446                 assign_chk_ovf(i915, remap_info->size,
1447                                plane_view_linear_tiles(fb, color_plane, dims, x, y));
1448         } else {
1449                 remap_info->linear = 0;
1450
1451                 assign_chk_ovf(i915, remap_info->src_stride,
1452                                plane_view_src_stride_tiles(fb, color_plane, dims));
1453                 assign_chk_ovf(i915, remap_info->width,
1454                                plane_view_width_tiles(fb, color_plane, dims, x));
1455                 assign_chk_ovf(i915, remap_info->height,
1456                                plane_view_height_tiles(fb, color_plane, dims, y));
1457         }
1458
1459         if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
1460                 drm_WARN_ON(&i915->drm, remap_info->linear);
1461                 check_array_bounds(i915, view->gtt.rotated.plane, color_plane);
1462
1463                 assign_chk_ovf(i915, remap_info->dst_stride,
1464                                plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));
1465
1466                 /* rotate the x/y offsets to match the GTT view */
1467                 drm_rect_init(&r, x, y, dims->width, dims->height);
1468                 drm_rect_rotate(&r,
1469                                 remap_info->width * tile_width,
1470                                 remap_info->height * tile_height,
1471                                 DRM_MODE_ROTATE_270);
1472
1473                 color_plane_info->x = r.x1;
1474                 color_plane_info->y = r.y1;
1475
1476                 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;
1477                 color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1478
1479                 size += remap_info->dst_stride * remap_info->width;
1480
1481                 /* rotate the tile dimensions to match the GTT view */
1482                 swap(tile_width, tile_height);
1483         } else {
1484                 drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);
1485
1486                 check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
1487
1488                 if (view->gtt.remapped.plane_alignment) {
1489                         unsigned int aligned_offset = ALIGN(gtt_offset,
1490                                                             view->gtt.remapped.plane_alignment);
1491
1492                         size += aligned_offset - gtt_offset;
1493                         gtt_offset = aligned_offset;
1494                 }
1495
1496                 color_plane_info->x = x;
1497                 color_plane_info->y = y;
1498
1499                 if (remap_info->linear) {
1500                         color_plane_info->mapping_stride = fb->base.pitches[color_plane];
1501                         color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1502
1503                         size += remap_info->size;
1504                 } else {
1505                         unsigned int dst_stride;
1506
1507                         /*
1508                          * The hardware automagically calculates the CCS AUX surface
1509                          * stride from the main surface stride so can't really remap a
1510                          * smaller subset (unless we'd remap in whole AUX page units).
1511                          */
1512                         if (intel_fb_needs_pot_stride_remap(fb) &&
1513                             intel_fb_is_ccs_modifier(fb->base.modifier))
1514                                 dst_stride = remap_info->src_stride;
1515                         else
1516                                 dst_stride = remap_info->width;
1517
1518                         dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride);
1519
1520                         assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);
1521                         color_plane_info->mapping_stride = dst_stride *
1522                                                            tile_width *
1523                                                            fb->base.format->cpp[color_plane];
1524                         color_plane_info->scanout_stride =
1525                                 plane_view_scanout_stride(fb, color_plane, tile_width,
1526                                                           remap_info->src_stride,
1527                                                           dst_stride);
1528
1529                         size += dst_stride * remap_info->height;
1530                 }
1531         }
1532
1533         /*
1534          * We only keep the x/y offsets, so push all of the gtt offset into
1535          * the x/y offsets.  x,y will hold the first pixel of the framebuffer
1536          * plane from the start of the remapped/rotated gtt mapping.
1537          */
1538         if (remap_info->linear)
1539                 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y,
1540                                            fb->base.format->cpp[color_plane],
1541                                            color_plane_info->mapping_stride,
1542                                            gtt_offset * tile_size, 0);
1543         else
1544                 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y,
1545                                          tile_width, tile_height,
1546                                          tile_size, remap_info->dst_stride,
1547                                          gtt_offset * tile_size, 0);
1548
1549         return size;
1550 }
1551
1552 #undef assign_chk_ovf
1553
1554 /* Return number of tiles @color_plane needs. */
1555 static unsigned int
1556 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
1557                        const struct fb_plane_view_dims *dims,
1558                        int x, int y)
1559 {
1560         unsigned int tiles;
1561
1562         if (is_surface_linear(&fb->base, color_plane)) {
1563                 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);
1564         } else {
1565                 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *
1566                         plane_view_height_tiles(fb, color_plane, dims, y);
1567                 /*
1568                  * If the plane isn't horizontally tile aligned,
1569                  * we need one more tile.
1570                  */
1571                 if (x != 0)
1572                         tiles++;
1573         }
1574
1575         return tiles;
1576 }
1577
1578 static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,
1579                                enum i915_gtt_view_type view_type)
1580 {
1581         memset(view, 0, sizeof(*view));
1582         view->gtt.type = view_type;
1583
1584         if (view_type == I915_GTT_VIEW_REMAPPED &&
1585             (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
1586                 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
1587 }
1588
1589 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
1590 {
1591         if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
1592                 return false;
1593
1594         return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
1595                fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
1596 }
1597
1598 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
1599 {
1600         struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1601         u32 gtt_offset_rotated = 0;
1602         u32 gtt_offset_remapped = 0;
1603         unsigned int max_size = 0;
1604         int i, num_planes = fb->base.format->num_planes;
1605         unsigned int tile_size = intel_tile_size(i915);
1606
1607         intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL);
1608
1609         drm_WARN_ON(&i915->drm,
1610                     intel_fb_supports_90_270_rotation(fb) &&
1611                     intel_fb_needs_pot_stride_remap(fb));
1612
1613         if (intel_fb_supports_90_270_rotation(fb))
1614                 intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED);
1615         if (intel_fb_needs_pot_stride_remap(fb))
1616                 intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);
1617
1618         for (i = 0; i < num_planes; i++) {
1619                 struct fb_plane_view_dims view_dims;
1620                 unsigned int width, height;
1621                 unsigned int size;
1622                 u32 offset;
1623                 int x, y;
1624                 int ret;
1625
1626                 /*
1627                  * Plane 2 of Render Compression with Clear Color fb modifier
1628                  * is consumed by the driver and not passed to DE. Skip the
1629                  * arithmetic related to alignment and offset calculation.
1630                  */
1631                 if (is_gen12_ccs_cc_plane(&fb->base, i)) {
1632                         if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
1633                                 continue;
1634                         else
1635                                 return -EINVAL;
1636                 }
1637
1638                 intel_fb_plane_dims(fb, i, &width, &height);
1639
1640                 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
1641                 if (ret)
1642                         return ret;
1643
1644                 init_plane_view_dims(fb, i, width, height, &view_dims);
1645
1646                 /*
1647                  * First pixel of the framebuffer from
1648                  * the start of the normal gtt mapping.
1649                  */
1650                 fb->normal_view.color_plane[i].x = x;
1651                 fb->normal_view.color_plane[i].y = y;
1652                 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];
1653                 fb->normal_view.color_plane[i].scanout_stride =
1654                         fb->normal_view.color_plane[i].mapping_stride;
1655
1656                 offset = calc_plane_aligned_offset(fb, i, &x, &y);
1657
1658                 if (intel_fb_supports_90_270_rotation(fb))
1659                         gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
1660                                                                     offset, gtt_offset_rotated, x, y,
1661                                                                     &fb->rotated_view);
1662
1663                 if (intel_fb_needs_pot_stride_remap(fb))
1664                         gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,
1665                                                                      offset, gtt_offset_remapped, x, y,
1666                                                                      &fb->remapped_view);
1667
1668                 size = calc_plane_normal_size(fb, i, &view_dims, x, y);
1669                 /* how many tiles in total needed in the bo */
1670                 max_size = max(max_size, offset + size);
1671         }
1672
1673         if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
1674                 drm_dbg_kms(&i915->drm,
1675                             "fb too big for bo (need %llu bytes, have %zu bytes)\n",
1676                             mul_u32_u32(max_size, tile_size), obj->base.size);
1677                 return -EINVAL;
1678         }
1679
1680         return 0;
1681 }
1682
1683 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
1684 {
1685         struct drm_i915_private *i915 =
1686                 to_i915(plane_state->uapi.plane->dev);
1687         struct drm_framebuffer *fb = plane_state->hw.fb;
1688         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1689         unsigned int rotation = plane_state->hw.rotation;
1690         int i, num_planes = fb->format->num_planes;
1691         unsigned int src_x, src_y;
1692         unsigned int src_w, src_h;
1693         u32 gtt_offset = 0;
1694
1695         intel_fb_view_init(i915, &plane_state->view,
1696                            drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :
1697                                                               I915_GTT_VIEW_REMAPPED);
1698
1699         src_x = plane_state->uapi.src.x1 >> 16;
1700         src_y = plane_state->uapi.src.y1 >> 16;
1701         src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1702         src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1703
1704         drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
1705
1706         /* Make src coordinates relative to the viewport */
1707         drm_rect_translate(&plane_state->uapi.src,
1708                            -(src_x << 16), -(src_y << 16));
1709
1710         /* Rotate src coordinates to match rotated GTT view */
1711         if (drm_rotation_90_or_270(rotation))
1712                 drm_rect_rotate(&plane_state->uapi.src,
1713                                 src_w << 16, src_h << 16,
1714                                 DRM_MODE_ROTATE_270);
1715
1716         for (i = 0; i < num_planes; i++) {
1717                 unsigned int hsub = i ? fb->format->hsub : 1;
1718                 unsigned int vsub = i ? fb->format->vsub : 1;
1719                 struct fb_plane_view_dims view_dims;
1720                 unsigned int width, height;
1721                 unsigned int x, y;
1722                 u32 offset;
1723
1724                 x = src_x / hsub;
1725                 y = src_y / vsub;
1726                 width = src_w / hsub;
1727                 height = src_h / vsub;
1728
1729                 init_plane_view_dims(intel_fb, i, width, height, &view_dims);
1730
1731                 /*
1732                  * First pixel of the src viewport from the
1733                  * start of the normal gtt mapping.
1734                  */
1735                 x += intel_fb->normal_view.color_plane[i].x;
1736                 y += intel_fb->normal_view.color_plane[i].y;
1737
1738                 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);
1739
1740                 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims,
1741                                                     offset, gtt_offset, x, y,
1742                                                     &plane_state->view);
1743         }
1744 }
1745
1746 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
1747                         struct intel_fb_view *view)
1748 {
1749         if (drm_rotation_90_or_270(rotation))
1750                 *view = fb->rotated_view;
1751         else if (intel_fb_needs_pot_stride_remap(fb))
1752                 *view = fb->remapped_view;
1753         else
1754                 *view = fb->normal_view;
1755 }
1756
1757 static
1758 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1759                         u32 pixel_format, u64 modifier)
1760 {
1761         /*
1762          * Arbitrary limit for gen4+ chosen to match the
1763          * render engine max stride.
1764          *
1765          * The new CCS hash mode makes remapping impossible
1766          */
1767         if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
1768             intel_fb_modifier_uses_dpt(dev_priv, modifier))
1769                 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1770         else if (DISPLAY_VER(dev_priv) >= 7)
1771                 return 256 * 1024;
1772         else
1773                 return 128 * 1024;
1774 }
1775
1776 static u32
1777 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1778 {
1779         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1780         u32 tile_width;
1781
1782         if (is_surface_linear(fb, color_plane)) {
1783                 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
1784                                                            fb->format->format,
1785                                                            fb->modifier);
1786
1787                 /*
1788                  * To make remapping with linear generally feasible
1789                  * we need the stride to be page aligned.
1790                  */
1791                 if (fb->pitches[color_plane] > max_stride &&
1792                     !intel_fb_is_ccs_modifier(fb->modifier))
1793                         return intel_tile_size(dev_priv);
1794                 else
1795                         return 64;
1796         }
1797
1798         tile_width = intel_tile_width_bytes(fb, color_plane);
1799         if (intel_fb_is_ccs_modifier(fb->modifier)) {
1800                 /*
1801                  * On TGL the surface stride must be 4 tile aligned, mapped by
1802                  * one 64 byte cacheline on the CCS AUX surface.
1803                  */
1804                 if (DISPLAY_VER(dev_priv) >= 12)
1805                         tile_width *= 4;
1806                 /*
1807                  * Display WA #0531: skl,bxt,kbl,glk
1808                  *
1809                  * Render decompression and plane width > 3840
1810                  * combined with horizontal panning requires the
1811                  * plane stride to be a multiple of 4. We'll just
1812                  * require the entire fb to accommodate that to avoid
1813                  * potential runtime errors at plane configuration time.
1814                  */
1815                 else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1816                          color_plane == 0 && fb->width > 3840)
1817                         tile_width *= 4;
1818         }
1819         return tile_width;
1820 }
1821
1822 static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
1823 {
1824         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1825         const struct drm_framebuffer *fb = plane_state->hw.fb;
1826         unsigned int rotation = plane_state->hw.rotation;
1827         u32 stride, max_stride;
1828
1829         /*
1830          * We ignore stride for all invisible planes that
1831          * can be remapped. Otherwise we could end up
1832          * with a false positive when the remapping didn't
1833          * kick in due the plane being invisible.
1834          */
1835         if (intel_plane_can_remap(plane_state) &&
1836             !plane_state->uapi.visible)
1837                 return 0;
1838
1839         /* FIXME other color planes? */
1840         stride = plane_state->view.color_plane[0].mapping_stride;
1841         max_stride = plane->max_stride(plane, fb->format->format,
1842                                        fb->modifier, rotation);
1843
1844         if (stride > max_stride) {
1845                 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
1846                               fb->base.id, stride,
1847                               plane->base.base.id, plane->base.name, max_stride);
1848                 return -EINVAL;
1849         }
1850
1851         return 0;
1852 }
1853
1854 int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
1855 {
1856         const struct intel_framebuffer *fb =
1857                 to_intel_framebuffer(plane_state->hw.fb);
1858         unsigned int rotation = plane_state->hw.rotation;
1859
1860         if (!fb)
1861                 return 0;
1862
1863         if (intel_plane_needs_remap(plane_state)) {
1864                 intel_plane_remap_gtt(plane_state);
1865
1866                 /*
1867                  * Sometimes even remapping can't overcome
1868                  * the stride limitations :( Can happen with
1869                  * big plane sizes and suitably misaligned
1870                  * offsets.
1871                  */
1872                 return intel_plane_check_stride(plane_state);
1873         }
1874
1875         intel_fb_fill_view(fb, rotation, &plane_state->view);
1876
1877         /* Rotate src coordinates to match rotated GTT view */
1878         if (drm_rotation_90_or_270(rotation))
1879                 drm_rect_rotate(&plane_state->uapi.src,
1880                                 fb->base.width << 16, fb->base.height << 16,
1881                                 DRM_MODE_ROTATE_270);
1882
1883         return intel_plane_check_stride(plane_state);
1884 }
1885
1886 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1887 {
1888         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1889
1890         drm_framebuffer_cleanup(fb);
1891
1892         if (intel_fb_uses_dpt(fb))
1893                 intel_dpt_destroy(intel_fb->dpt_vm);
1894
1895         intel_frontbuffer_put(intel_fb->frontbuffer);
1896
1897         kfree(intel_fb);
1898 }
1899
1900 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1901                                                 struct drm_file *file,
1902                                                 unsigned int *handle)
1903 {
1904         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1905         struct drm_i915_private *i915 = to_i915(obj->base.dev);
1906
1907         if (i915_gem_object_is_userptr(obj)) {
1908                 drm_dbg(&i915->drm,
1909                         "attempting to use a userptr for a framebuffer, denied\n");
1910                 return -EINVAL;
1911         }
1912
1913         return drm_gem_handle_create(file, &obj->base, handle);
1914 }
1915
1916 struct frontbuffer_fence_cb {
1917         struct dma_fence_cb base;
1918         struct intel_frontbuffer *front;
1919 };
1920
1921 static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,
1922                                               struct dma_fence_cb *data)
1923 {
1924         struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);
1925
1926         intel_frontbuffer_queue_flush(cb->front);
1927         kfree(cb);
1928         dma_fence_put(dma);
1929 }
1930
1931 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
1932                                         struct drm_file *file,
1933                                         unsigned int flags, unsigned int color,
1934                                         struct drm_clip_rect *clips,
1935                                         unsigned int num_clips)
1936 {
1937         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1938         struct intel_frontbuffer *front = to_intel_frontbuffer(fb);
1939         struct dma_fence *fence;
1940         struct frontbuffer_fence_cb *cb;
1941         int ret = 0;
1942
1943         if (!atomic_read(&front->bits))
1944                 return 0;
1945
1946         if (dma_resv_test_signaled(obj->base.resv, dma_resv_usage_rw(false)))
1947                 goto flush;
1948
1949         ret = dma_resv_get_singleton(obj->base.resv, dma_resv_usage_rw(false),
1950                                      &fence);
1951         if (ret || !fence)
1952                 goto flush;
1953
1954         cb = kmalloc(sizeof(*cb), GFP_KERNEL);
1955         if (!cb) {
1956                 dma_fence_put(fence);
1957                 ret = -ENOMEM;
1958                 goto flush;
1959         }
1960
1961         cb->front = front;
1962
1963         intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB);
1964
1965         ret = dma_fence_add_callback(fence, &cb->base,
1966                                      intel_user_framebuffer_fence_wake);
1967         if (ret) {
1968                 intel_user_framebuffer_fence_wake(fence, &cb->base);
1969                 if (ret == -ENOENT)
1970                         ret = 0;
1971         }
1972
1973         return ret;
1974
1975 flush:
1976         i915_gem_object_flush_if_display(obj);
1977         intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
1978         return ret;
1979 }
1980
1981 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1982         .destroy = intel_user_framebuffer_destroy,
1983         .create_handle = intel_user_framebuffer_create_handle,
1984         .dirty = intel_user_framebuffer_dirty,
1985 };
1986
1987 int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
1988                            struct drm_i915_gem_object *obj,
1989                            struct drm_mode_fb_cmd2 *mode_cmd)
1990 {
1991         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
1992         struct drm_framebuffer *fb = &intel_fb->base;
1993         u32 max_stride;
1994         unsigned int tiling, stride;
1995         int ret = -EINVAL;
1996         int i;
1997
1998         intel_fb->frontbuffer = intel_frontbuffer_get(obj);
1999         if (!intel_fb->frontbuffer)
2000                 return -ENOMEM;
2001
2002         i915_gem_object_lock(obj, NULL);
2003         tiling = i915_gem_object_get_tiling(obj);
2004         stride = i915_gem_object_get_stride(obj);
2005         i915_gem_object_unlock(obj);
2006
2007         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
2008                 /*
2009                  * If there's a fence, enforce that
2010                  * the fb modifier and tiling mode match.
2011                  */
2012                 if (tiling != I915_TILING_NONE &&
2013                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
2014                         drm_dbg_kms(&dev_priv->drm,
2015                                     "tiling_mode doesn't match fb modifier\n");
2016                         goto err;
2017                 }
2018         } else {
2019                 if (tiling == I915_TILING_X) {
2020                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
2021                 } else if (tiling == I915_TILING_Y) {
2022                         drm_dbg_kms(&dev_priv->drm,
2023                                     "No Y tiling for legacy addfb\n");
2024                         goto err;
2025                 }
2026         }
2027
2028         if (!drm_any_plane_has_format(&dev_priv->drm,
2029                                       mode_cmd->pixel_format,
2030                                       mode_cmd->modifier[0])) {
2031                 drm_dbg_kms(&dev_priv->drm,
2032                             "unsupported pixel format %p4cc / modifier 0x%llx\n",
2033                             &mode_cmd->pixel_format, mode_cmd->modifier[0]);
2034                 goto err;
2035         }
2036
2037         /*
2038          * gen2/3 display engine uses the fence if present,
2039          * so the tiling mode must match the fb modifier exactly.
2040          */
2041         if (DISPLAY_VER(dev_priv) < 4 &&
2042             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
2043                 drm_dbg_kms(&dev_priv->drm,
2044                             "tiling_mode must match fb modifier exactly on gen2/3\n");
2045                 goto err;
2046         }
2047
2048         max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
2049                                          mode_cmd->modifier[0]);
2050         if (mode_cmd->pitches[0] > max_stride) {
2051                 drm_dbg_kms(&dev_priv->drm,
2052                             "%s pitch (%u) must be at most %d\n",
2053                             mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
2054                             "tiled" : "linear",
2055                             mode_cmd->pitches[0], max_stride);
2056                 goto err;
2057         }
2058
2059         /*
2060          * If there's a fence, enforce that
2061          * the fb pitch and fence stride match.
2062          */
2063         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
2064                 drm_dbg_kms(&dev_priv->drm,
2065                             "pitch (%d) must match tiling stride (%d)\n",
2066                             mode_cmd->pitches[0], stride);
2067                 goto err;
2068         }
2069
2070         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
2071         if (mode_cmd->offsets[0] != 0) {
2072                 drm_dbg_kms(&dev_priv->drm,
2073                             "plane 0 offset (0x%08x) must be 0\n",
2074                             mode_cmd->offsets[0]);
2075                 goto err;
2076         }
2077
2078         drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
2079
2080         for (i = 0; i < fb->format->num_planes; i++) {
2081                 u32 stride_alignment;
2082
2083                 if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
2084                         drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
2085                                     i);
2086                         goto err;
2087                 }
2088
2089                 stride_alignment = intel_fb_stride_alignment(fb, i);
2090                 if (fb->pitches[i] & (stride_alignment - 1)) {
2091                         drm_dbg_kms(&dev_priv->drm,
2092                                     "plane %d pitch (%d) must be at least %u byte aligned\n",
2093                                     i, fb->pitches[i], stride_alignment);
2094                         goto err;
2095                 }
2096
2097                 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {
2098                         int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
2099
2100                         if (fb->pitches[i] != ccs_aux_stride) {
2101                                 drm_dbg_kms(&dev_priv->drm,
2102                                             "ccs aux plane %d pitch (%d) must be %d\n",
2103                                             i,
2104                                             fb->pitches[i], ccs_aux_stride);
2105                                 goto err;
2106                         }
2107                 }
2108
2109                 fb->obj[i] = &obj->base;
2110         }
2111
2112         ret = intel_fill_fb_info(dev_priv, intel_fb);
2113         if (ret)
2114                 goto err;
2115
2116         if (intel_fb_uses_dpt(fb)) {
2117                 struct i915_address_space *vm;
2118
2119                 vm = intel_dpt_create(intel_fb);
2120                 if (IS_ERR(vm)) {
2121                         drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n");
2122                         ret = PTR_ERR(vm);
2123                         goto err;
2124                 }
2125
2126                 intel_fb->dpt_vm = vm;
2127         }
2128
2129         ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
2130         if (ret) {
2131                 drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
2132                 goto err_free_dpt;
2133         }
2134
2135         return 0;
2136
2137 err_free_dpt:
2138         if (intel_fb_uses_dpt(fb))
2139                 intel_dpt_destroy(intel_fb->dpt_vm);
2140 err:
2141         intel_frontbuffer_put(intel_fb->frontbuffer);
2142         return ret;
2143 }
2144
2145 struct drm_framebuffer *
2146 intel_user_framebuffer_create(struct drm_device *dev,
2147                               struct drm_file *filp,
2148                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
2149 {
2150         struct drm_framebuffer *fb;
2151         struct drm_i915_gem_object *obj;
2152         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2153         struct drm_i915_private *i915;
2154
2155         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
2156         if (!obj)
2157                 return ERR_PTR(-ENOENT);
2158
2159         /* object is backed with LMEM for discrete */
2160         i915 = to_i915(obj->base.dev);
2161         if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
2162                 /* object is "remote", not in local memory */
2163                 i915_gem_object_put(obj);
2164                 drm_dbg_kms(&i915->drm, "framebuffer must reside in local memory\n");
2165                 return ERR_PTR(-EREMOTE);
2166         }
2167
2168         fb = intel_framebuffer_create(obj, &mode_cmd);
2169         i915_gem_object_put(obj);
2170
2171         return fb;
2172 }
2173
2174 struct drm_framebuffer *
2175 intel_framebuffer_create(struct drm_i915_gem_object *obj,
2176                          struct drm_mode_fb_cmd2 *mode_cmd)
2177 {
2178         struct intel_framebuffer *intel_fb;
2179         int ret;
2180
2181         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2182         if (!intel_fb)
2183                 return ERR_PTR(-ENOMEM);
2184
2185         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
2186         if (ret)
2187                 goto err;
2188
2189         return &intel_fb->base;
2190
2191 err:
2192         kfree(intel_fb);
2193         return ERR_PTR(ret);
2194 }