drivers/gpu/drm/i915/display/intel_dpio_phy.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DPIO_PHY_H__
   7 #define __INTEL_DPIO_PHY_H__
   8
   9 #include <linux/types.h>
  10
  11 enum pipe;
  12 enum port;
  13 struct drm_i915_private;
  14 struct intel_crtc_state;
  15 struct intel_digital_port;
  16 struct intel_encoder;
  17
  18 enum dpio_channel {
  19         DPIO_CH0,
  20         DPIO_CH1,
  21 };
  22
  23 enum dpio_phy {
  24         DPIO_PHY0,
  25         DPIO_PHY1,
  26         DPIO_PHY2,
  27 };
  28
  29 #ifdef I915
  30 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
  31                              enum dpio_phy *phy, enum dpio_channel *ch);
  32 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
  33                                    const struct intel_crtc_state *crtc_state);
  34 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
  35 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
  36 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
  37                             enum dpio_phy phy);
  38 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
  39                               enum dpio_phy phy);
  40 u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count);
  41 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
  42                                      u8 lane_lat_optim_mask);
  43 u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
  44
  45 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
  46 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
  47 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);
  48
  49 void chv_set_phy_signal_level(struct intel_encoder *encoder,
  50                               const struct intel_crtc_state *crtc_state,
  51                               u32 deemph_reg_value, u32 margin_reg_value,
  52                               bool uniq_trans_scale);
  53 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
  54                               const struct intel_crtc_state *crtc_state,
  55                               bool reset);
  56 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
  57                             const struct intel_crtc_state *crtc_state);
  58 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
  59                                 const struct intel_crtc_state *crtc_state);
  60 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
  61 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
  62                               const struct intel_crtc_state *old_crtc_state);
  63
  64 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
  65                               const struct intel_crtc_state *crtc_state,
  66                               u32 demph_reg_value, u32 preemph_reg_value,
  67                               u32 uniqtranscale_reg_value, u32 tx3_demph);
  68 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
  69                             const struct intel_crtc_state *crtc_state);
  70 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
  71                                 const struct intel_crtc_state *crtc_state);
  72 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
  73                          const struct intel_crtc_state *old_crtc_state);
  74 #else
  75 static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
  76                                            enum dpio_phy *phy, enum dpio_channel *ch)
  77 {
  78 }
  79 static inline void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
  80                                                  const struct intel_crtc_state *crtc_state)
  81 {
  82 }
  83 static inline void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
  84 {
  85 }
  86 static inline void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
  87 {
  88 }
  89 static inline bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
  90                                           enum dpio_phy phy)
  91 {
  92         return false;
  93 }
  94 static inline bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
  95                                             enum dpio_phy phy)
  96 {
  97         return true;
  98 }
  99 static inline u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
 100 {
 101         return 0;
 102 }
 103 static inline void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
 104                                                    u8 lane_lat_optim_mask)
 105 {
 106 }
 107 static inline u8 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
 108 {
 109         return 0;
 110 }
 111 static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
 112 {
 113         return DPIO_CH0;
 114 }
 115 static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
 116 {
 117         return DPIO_PHY0;
 118 }
 119 static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
 120 {
 121         return DPIO_CH0;
 122 }
 123 static inline void chv_set_phy_signal_level(struct intel_encoder *encoder,
 124                                             const struct intel_crtc_state *crtc_state,
 125                                             u32 deemph_reg_value, u32 margin_reg_value,
 126                                             bool uniq_trans_scale)
 127 {
 128 }
 129 static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 130                                             const struct intel_crtc_state *crtc_state,
 131                                             bool reset)
 132 {
 133 }
 134 static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 135                                           const struct intel_crtc_state *crtc_state)
 136 {
 137 }
 138 static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 139                                               const struct intel_crtc_state *crtc_state)
 140 {
 141 }
 142 static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder)
 143 {
 144 }
 145 static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 146                                             const struct intel_crtc_state *old_crtc_state)
 147 {
 148 }
 149
 150 static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 151                                             const struct intel_crtc_state *crtc_state,
 152                                             u32 demph_reg_value, u32 preemph_reg_value,
 153                                             u32 uniqtranscale_reg_value, u32 tx3_demph)
 154 {
 155 }
 156 static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 157                                           const struct intel_crtc_state *crtc_state)
 158 {
 159 }
 160 static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 161                                               const struct intel_crtc_state *crtc_state)
 162 {
 163 }
 164 static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 165                                        const struct intel_crtc_state *old_crtc_state)
 166 {
 167 }
 168 #endif
 169
 170 #endif /* __INTEL_DPIO_PHY_H__ */