drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "nv.h"
  33 #include "nvd.h"
  34
  35 #include "gc/gc_10_1_0_offset.h"
  36 #include "gc/gc_10_1_0_sh_mask.h"
  37 #include "smuio/smuio_11_0_0_offset.h"
  38 #include "smuio/smuio_11_0_0_sh_mask.h"
  39 #include "navi10_enum.h"
  40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  41
  42 #include "soc15.h"
  43 #include "soc15d.h"
  44 #include "soc15_common.h"
  45 #include "clearstate_gfx10.h"
  46 #include "v10_structs.h"
  47 #include "gfx_v10_0.h"
  48 #include "nbio_v2_3.h"
  49
  50 /*
  51  * Navi10 has two graphic rings to share each graphic pipe.
  52  * 1. Primary ring
  53  * 2. Async ring
  54  */
  55 #define GFX10_NUM_GFX_RINGS_NV1X        1
  56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      2
  57 #define GFX10_MEC_HPD_SIZE      2048
  58
  59 #define F32_CE_PROGRAM_RAM_SIZE         65536
  60 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  61
  62 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  68
  69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  71
  72 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  76
  77 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  79 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 104
 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 109
 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
 114
 115 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 121 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 123 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 125 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 127 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 129 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 131 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 134
 135 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 137 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 139 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 141 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 143 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 145 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 147
 148 #define mmCPG_PSP_DEBUG                         0x5c10
 149 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 150 #define mmCPC_PSP_DEBUG                         0x5c11
 151 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 154
 155 //CC_GC_SA_UNIT_DISABLE
 156 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 160 //GC_USER_SA_UNIT_DISABLE
 161 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 165 //PA_SC_ENHANCE_3
 166 #define mmPA_SC_ENHANCE_3                       0x1085
 167 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 170
 171 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 173
 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 178
 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 181
 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
 184
 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 191
 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 203
 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 210
 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 217
 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 224
 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 231
 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 238
 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
 245
 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
 252
 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
 259
 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
 266
 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
 273
 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 275 {
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 316 };
 317
 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 319 {
 320         /* Pending on emulation bring up */
 321 };
 322
 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 324 {
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469         /* Pending on emulation bring up */
1470 };
1471
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098         /* Pending on emulation bring up */
2099 };
2100
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206         /* Pending on emulation bring up */
3207 };
3208
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252
3253         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3255 };
3256
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283
3284         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3286 };
3287
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3350 };
3351
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474
3475 #define DEFAULT_SH_MEM_CONFIG \
3476         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490                                  struct amdgpu_cu_info *cu_info);
3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493                                    u32 sh_num, u32 instance);
3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495
3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507                                            uint16_t pasid, uint32_t flush_type,
3508                                            bool all_hub, uint8_t dst_sel);
3509
3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 {
3512         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3516         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3517         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521 }
3522
3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524                                  struct amdgpu_ring *ring)
3525 {
3526         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527         uint64_t wptr_addr = ring->wptr_gpu_addr;
3528         uint32_t eng_sel = 0;
3529
3530         switch (ring->funcs->type) {
3531         case AMDGPU_RING_TYPE_COMPUTE:
3532                 eng_sel = 0;
3533                 break;
3534         case AMDGPU_RING_TYPE_GFX:
3535                 eng_sel = 4;
3536                 break;
3537         case AMDGPU_RING_TYPE_MES:
3538                 eng_sel = 5;
3539                 break;
3540         default:
3541                 WARN_ON(1);
3542         }
3543
3544         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 }
3562
3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564                                    struct amdgpu_ring *ring,
3565                                    enum amdgpu_unmap_queues_action action,
3566                                    u64 gpu_addr, u64 seq)
3567 {
3568         struct amdgpu_device *adev = kiq_ring->adev;
3569         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570
3571         if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573                 return;
3574         }
3575
3576         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3579                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582         amdgpu_ring_write(kiq_ring,
3583                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584
3585         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588                 amdgpu_ring_write(kiq_ring, seq);
3589         } else {
3590                 amdgpu_ring_write(kiq_ring, 0);
3591                 amdgpu_ring_write(kiq_ring, 0);
3592                 amdgpu_ring_write(kiq_ring, 0);
3593         }
3594 }
3595
3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597                                    struct amdgpu_ring *ring,
3598                                    u64 addr,
3599                                    u64 seq)
3600 {
3601         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602
3603         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604         amdgpu_ring_write(kiq_ring,
3605                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607                           PACKET3_QUERY_STATUS_COMMAND(2));
3608         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 }
3616
3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618                                 uint16_t pasid, uint32_t flush_type,
3619                                 bool all_hub)
3620 {
3621         gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 }
3623
3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625         .kiq_set_resources = gfx10_kiq_set_resources,
3626         .kiq_map_queues = gfx10_kiq_map_queues,
3627         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628         .kiq_query_status = gfx10_kiq_query_status,
3629         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630         .set_resources_size = 8,
3631         .map_queues_size = 7,
3632         .unmap_queues_size = 6,
3633         .query_status_size = 7,
3634         .invalidate_tlbs_size = 2,
3635 };
3636
3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 {
3639         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 }
3641
3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 {
3644         switch (adev->ip_versions[GC_HWIP][0]) {
3645         case IP_VERSION(10, 1, 10):
3646                 soc15_program_register_sequence(adev,
3647                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3648                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649                 break;
3650         case IP_VERSION(10, 1, 1):
3651                 soc15_program_register_sequence(adev,
3652                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3653                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654                 break;
3655         case IP_VERSION(10, 1, 2):
3656                 soc15_program_register_sequence(adev,
3657                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3658                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659                 break;
3660         default:
3661                 break;
3662         }
3663 }
3664
3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 {
3667         switch (adev->ip_versions[GC_HWIP][0]) {
3668         case IP_VERSION(10, 1, 10):
3669                 soc15_program_register_sequence(adev,
3670                                                 golden_settings_gc_10_1,
3671                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672                 soc15_program_register_sequence(adev,
3673                                                 golden_settings_gc_10_0_nv10,
3674                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675                 break;
3676         case IP_VERSION(10, 1, 1):
3677                 soc15_program_register_sequence(adev,
3678                                                 golden_settings_gc_10_1_1,
3679                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680                 soc15_program_register_sequence(adev,
3681                                                 golden_settings_gc_10_1_nv14,
3682                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683                 break;
3684         case IP_VERSION(10, 1, 2):
3685                 soc15_program_register_sequence(adev,
3686                                                 golden_settings_gc_10_1_2,
3687                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688                 soc15_program_register_sequence(adev,
3689                                                 golden_settings_gc_10_1_2_nv12,
3690                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691                 break;
3692         case IP_VERSION(10, 3, 0):
3693                 soc15_program_register_sequence(adev,
3694                                                 golden_settings_gc_10_3,
3695                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696                 soc15_program_register_sequence(adev,
3697                                                 golden_settings_gc_10_3_sienna_cichlid,
3698                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699                 break;
3700         case IP_VERSION(10, 3, 2):
3701                 soc15_program_register_sequence(adev,
3702                                                 golden_settings_gc_10_3_2,
3703                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704                 break;
3705         case IP_VERSION(10, 3, 1):
3706                 soc15_program_register_sequence(adev,
3707                                                 golden_settings_gc_10_3_vangogh,
3708                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709                 break;
3710         case IP_VERSION(10, 3, 3):
3711                 soc15_program_register_sequence(adev,
3712                                                 golden_settings_gc_10_3_3,
3713                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714                 break;
3715         case IP_VERSION(10, 3, 4):
3716                 soc15_program_register_sequence(adev,
3717                                                 golden_settings_gc_10_3_4,
3718                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719                 break;
3720         case IP_VERSION(10, 3, 5):
3721                 soc15_program_register_sequence(adev,
3722                                                 golden_settings_gc_10_3_5,
3723                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724                 break;
3725         case IP_VERSION(10, 1, 3):
3726         case IP_VERSION(10, 1, 4):
3727                 soc15_program_register_sequence(adev,
3728                                                 golden_settings_gc_10_0_cyan_skillfish,
3729                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730                 break;
3731         case IP_VERSION(10, 3, 6):
3732                 soc15_program_register_sequence(adev,
3733                                                 golden_settings_gc_10_3_6,
3734                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735                 break;
3736         case IP_VERSION(10, 3, 7):
3737                 soc15_program_register_sequence(adev,
3738                                                 golden_settings_gc_10_3_7,
3739                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740                 break;
3741         default:
3742                 break;
3743         }
3744         gfx_v10_0_init_spm_golden_registers(adev);
3745 }
3746
3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748                                        bool wc, uint32_t reg, uint32_t val)
3749 {
3750         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753         amdgpu_ring_write(ring, reg);
3754         amdgpu_ring_write(ring, 0);
3755         amdgpu_ring_write(ring, val);
3756 }
3757
3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759                                   int mem_space, int opt, uint32_t addr0,
3760                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3761                                   uint32_t inv)
3762 {
3763         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764         amdgpu_ring_write(ring,
3765                           /* memory (1) or register (0) */
3766                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3769                            WAIT_REG_MEM_ENGINE(eng_sel)));
3770
3771         if (mem_space)
3772                 BUG_ON(addr0 & 0x3); /* Dword align */
3773         amdgpu_ring_write(ring, addr0);
3774         amdgpu_ring_write(ring, addr1);
3775         amdgpu_ring_write(ring, ref);
3776         amdgpu_ring_write(ring, mask);
3777         amdgpu_ring_write(ring, inv); /* poll interval */
3778 }
3779
3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 {
3782         struct amdgpu_device *adev = ring->adev;
3783         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3784         uint32_t tmp = 0;
3785         unsigned i;
3786         int r;
3787
3788         WREG32(scratch, 0xCAFEDEAD);
3789         r = amdgpu_ring_alloc(ring, 3);
3790         if (r) {
3791                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3792                           ring->idx, r);
3793                 return r;
3794         }
3795
3796         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3797         amdgpu_ring_write(ring, scratch -
3798                           PACKET3_SET_UCONFIG_REG_START);
3799         amdgpu_ring_write(ring, 0xDEADBEEF);
3800         amdgpu_ring_commit(ring);
3801
3802         for (i = 0; i < adev->usec_timeout; i++) {
3803                 tmp = RREG32(scratch);
3804                 if (tmp == 0xDEADBEEF)
3805                         break;
3806                 if (amdgpu_emu_mode == 1)
3807                         msleep(1);
3808                 else
3809                         udelay(1);
3810         }
3811
3812         if (i >= adev->usec_timeout)
3813                 r = -ETIMEDOUT;
3814
3815         return r;
3816 }
3817
3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819 {
3820         struct amdgpu_device *adev = ring->adev;
3821         struct amdgpu_ib ib;
3822         struct dma_fence *f = NULL;
3823         unsigned index;
3824         uint64_t gpu_addr;
3825         volatile uint32_t *cpu_ptr;
3826         long r;
3827
3828         memset(&ib, 0, sizeof(ib));
3829
3830         if (ring->is_mes_queue) {
3831                 uint32_t padding, offset;
3832
3833                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834                 padding = amdgpu_mes_ctx_get_offs(ring,
3835                                                   AMDGPU_MES_CTX_PADDING_OFFS);
3836
3837                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3838                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3839
3840                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3841                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3842                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3843         } else {
3844                 r = amdgpu_device_wb_get(adev, &index);
3845                 if (r)
3846                         return r;
3847
3848                 gpu_addr = adev->wb.gpu_addr + (index * 4);
3849                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3850                 cpu_ptr = &adev->wb.wb[index];
3851
3852                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853                 if (r) {
3854                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3855                         goto err1;
3856                 }
3857         }
3858
3859         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3860         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3861         ib.ptr[2] = lower_32_bits(gpu_addr);
3862         ib.ptr[3] = upper_32_bits(gpu_addr);
3863         ib.ptr[4] = 0xDEADBEEF;
3864         ib.length_dw = 5;
3865
3866         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3867         if (r)
3868                 goto err2;
3869
3870         r = dma_fence_wait_timeout(f, false, timeout);
3871         if (r == 0) {
3872                 r = -ETIMEDOUT;
3873                 goto err2;
3874         } else if (r < 0) {
3875                 goto err2;
3876         }
3877
3878         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3879                 r = 0;
3880         else
3881                 r = -EINVAL;
3882 err2:
3883         if (!ring->is_mes_queue)
3884                 amdgpu_ib_free(adev, &ib, NULL);
3885         dma_fence_put(f);
3886 err1:
3887         if (!ring->is_mes_queue)
3888                 amdgpu_device_wb_free(adev, index);
3889         return r;
3890 }
3891
3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893 {
3894         release_firmware(adev->gfx.pfp_fw);
3895         adev->gfx.pfp_fw = NULL;
3896         release_firmware(adev->gfx.me_fw);
3897         adev->gfx.me_fw = NULL;
3898         release_firmware(adev->gfx.ce_fw);
3899         adev->gfx.ce_fw = NULL;
3900         release_firmware(adev->gfx.rlc_fw);
3901         adev->gfx.rlc_fw = NULL;
3902         release_firmware(adev->gfx.mec_fw);
3903         adev->gfx.mec_fw = NULL;
3904         release_firmware(adev->gfx.mec2_fw);
3905         adev->gfx.mec2_fw = NULL;
3906
3907         kfree(adev->gfx.rlc.register_list_format);
3908 }
3909
3910 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911 {
3912         adev->gfx.cp_fw_write_wait = false;
3913
3914         switch (adev->ip_versions[GC_HWIP][0]) {
3915         case IP_VERSION(10, 1, 10):
3916         case IP_VERSION(10, 1, 2):
3917         case IP_VERSION(10, 1, 1):
3918         case IP_VERSION(10, 1, 3):
3919         case IP_VERSION(10, 1, 4):
3920                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921                     (adev->gfx.me_feature_version >= 27) &&
3922                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923                     (adev->gfx.pfp_feature_version >= 27) &&
3924                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925                     (adev->gfx.mec_feature_version >= 27))
3926                         adev->gfx.cp_fw_write_wait = true;
3927                 break;
3928         case IP_VERSION(10, 3, 0):
3929         case IP_VERSION(10, 3, 2):
3930         case IP_VERSION(10, 3, 1):
3931         case IP_VERSION(10, 3, 4):
3932         case IP_VERSION(10, 3, 5):
3933         case IP_VERSION(10, 3, 6):
3934         case IP_VERSION(10, 3, 3):
3935         case IP_VERSION(10, 3, 7):
3936                 adev->gfx.cp_fw_write_wait = true;
3937                 break;
3938         default:
3939                 break;
3940         }
3941
3942         if (!adev->gfx.cp_fw_write_wait)
3943                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3944 }
3945
3946
3947 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3948 {
3949         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3950
3951         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3952         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3953         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3954         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3955         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3956         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3957         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3958         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3959         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3960         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3961         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3962         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3963         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3964         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3965                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3966 }
3967
3968 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3969 {
3970         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3971
3972         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3973         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3974         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3975         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3976         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3977 }
3978
3979 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3980 {
3981         bool ret = false;
3982
3983         switch (adev->pdev->revision) {
3984         case 0xc2:
3985         case 0xc3:
3986                 ret = true;
3987                 break;
3988         default:
3989                 ret = false;
3990                 break;
3991         }
3992
3993         return ret ;
3994 }
3995
3996 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3997 {
3998         switch (adev->ip_versions[GC_HWIP][0]) {
3999         case IP_VERSION(10, 1, 10):
4000                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4001                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4002                 break;
4003         default:
4004                 break;
4005         }
4006 }
4007
4008 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4009 {
4010         const char *chip_name;
4011         char fw_name[40];
4012         char *wks = "";
4013         int err;
4014         struct amdgpu_firmware_info *info = NULL;
4015         const struct common_firmware_header *header = NULL;
4016         const struct gfx_firmware_header_v1_0 *cp_hdr;
4017         const struct rlc_firmware_header_v2_0 *rlc_hdr;
4018         unsigned int *tmp = NULL;
4019         unsigned int i = 0;
4020         uint16_t version_major;
4021         uint16_t version_minor;
4022
4023         DRM_DEBUG("\n");
4024
4025         switch (adev->ip_versions[GC_HWIP][0]) {
4026         case IP_VERSION(10, 1, 10):
4027                 chip_name = "navi10";
4028                 break;
4029         case IP_VERSION(10, 1, 1):
4030                 chip_name = "navi14";
4031                 if (!(adev->pdev->device == 0x7340 &&
4032                       adev->pdev->revision != 0x00))
4033                         wks = "_wks";
4034                 break;
4035         case IP_VERSION(10, 1, 2):
4036                 chip_name = "navi12";
4037                 break;
4038         case IP_VERSION(10, 3, 0):
4039                 chip_name = "sienna_cichlid";
4040                 break;
4041         case IP_VERSION(10, 3, 2):
4042                 chip_name = "navy_flounder";
4043                 break;
4044         case IP_VERSION(10, 3, 1):
4045                 chip_name = "vangogh";
4046                 break;
4047         case IP_VERSION(10, 3, 4):
4048                 chip_name = "dimgrey_cavefish";
4049                 break;
4050         case IP_VERSION(10, 3, 5):
4051                 chip_name = "beige_goby";
4052                 break;
4053         case IP_VERSION(10, 3, 3):
4054                 chip_name = "yellow_carp";
4055                 break;
4056         case IP_VERSION(10, 3, 6):
4057                 chip_name = "gc_10_3_6";
4058                 break;
4059         case IP_VERSION(10, 1, 3):
4060         case IP_VERSION(10, 1, 4):
4061                 chip_name = "cyan_skillfish2";
4062                 break;
4063         case IP_VERSION(10, 3, 7):
4064                 chip_name = "gc_10_3_7";
4065                 break;
4066         default:
4067                 BUG();
4068         }
4069
4070         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4071         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4072         if (err)
4073                 goto out;
4074         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4075         if (err)
4076                 goto out;
4077         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4078         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4079         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4080
4081         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4082         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4083         if (err)
4084                 goto out;
4085         err = amdgpu_ucode_validate(adev->gfx.me_fw);
4086         if (err)
4087                 goto out;
4088         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4089         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4090         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4091
4092         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4093         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4094         if (err)
4095                 goto out;
4096         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4097         if (err)
4098                 goto out;
4099         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4100         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4101         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4102
4103         if (!amdgpu_sriov_vf(adev)) {
4104                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4105                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4106                 if (err)
4107                         goto out;
4108                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4109                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4110                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4111                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4112
4113                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4114                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4115                 adev->gfx.rlc.save_and_restore_offset =
4116                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
4117                 adev->gfx.rlc.clear_state_descriptor_offset =
4118                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4119                 adev->gfx.rlc.avail_scratch_ram_locations =
4120                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4121                 adev->gfx.rlc.reg_restore_list_size =
4122                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
4123                 adev->gfx.rlc.reg_list_format_start =
4124                         le32_to_cpu(rlc_hdr->reg_list_format_start);
4125                 adev->gfx.rlc.reg_list_format_separate_start =
4126                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4127                 adev->gfx.rlc.starting_offsets_start =
4128                         le32_to_cpu(rlc_hdr->starting_offsets_start);
4129                 adev->gfx.rlc.reg_list_format_size_bytes =
4130                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4131                 adev->gfx.rlc.reg_list_size_bytes =
4132                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4133                 adev->gfx.rlc.register_list_format =
4134                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4135                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4136                 if (!adev->gfx.rlc.register_list_format) {
4137                         err = -ENOMEM;
4138                         goto out;
4139                 }
4140
4141                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4142                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4143                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4144                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4145
4146                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4147
4148                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4149                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4150                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4151                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4152
4153                 if (version_major == 2) {
4154                         if (version_minor >= 1)
4155                                 gfx_v10_0_init_rlc_ext_microcode(adev);
4156                         if (version_minor == 2)
4157                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4158                 }
4159         }
4160
4161         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4162         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4163         if (err)
4164                 goto out;
4165         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4166         if (err)
4167                 goto out;
4168         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4169         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4170         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4171
4172         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4173         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4174         if (!err) {
4175                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4176                 if (err)
4177                         goto out;
4178                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4179                 adev->gfx.mec2_fw->data;
4180                 adev->gfx.mec2_fw_version =
4181                 le32_to_cpu(cp_hdr->header.ucode_version);
4182                 adev->gfx.mec2_feature_version =
4183                 le32_to_cpu(cp_hdr->ucode_feature_version);
4184         } else {
4185                 err = 0;
4186                 adev->gfx.mec2_fw = NULL;
4187         }
4188
4189         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4190                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4191                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4192                 info->fw = adev->gfx.pfp_fw;
4193                 header = (const struct common_firmware_header *)info->fw->data;
4194                 adev->firmware.fw_size +=
4195                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4196
4197                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4198                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4199                 info->fw = adev->gfx.me_fw;
4200                 header = (const struct common_firmware_header *)info->fw->data;
4201                 adev->firmware.fw_size +=
4202                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4203
4204                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4205                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4206                 info->fw = adev->gfx.ce_fw;
4207                 header = (const struct common_firmware_header *)info->fw->data;
4208                 adev->firmware.fw_size +=
4209                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4210
4211                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4212                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4213                 info->fw = adev->gfx.rlc_fw;
4214                 if (info->fw) {
4215                         header = (const struct common_firmware_header *)info->fw->data;
4216                         adev->firmware.fw_size +=
4217                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4218                 }
4219                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4220                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4221                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4222                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4223                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4224                         info->fw = adev->gfx.rlc_fw;
4225                         adev->firmware.fw_size +=
4226                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4227
4228                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4229                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4230                         info->fw = adev->gfx.rlc_fw;
4231                         adev->firmware.fw_size +=
4232                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4233
4234                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4235                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4236                         info->fw = adev->gfx.rlc_fw;
4237                         adev->firmware.fw_size +=
4238                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4239
4240                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4241                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4242                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4243                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4244                                 info->fw = adev->gfx.rlc_fw;
4245                                 adev->firmware.fw_size +=
4246                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4247
4248                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4249                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4250                                 info->fw = adev->gfx.rlc_fw;
4251                                 adev->firmware.fw_size +=
4252                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4253                         }
4254                 }
4255
4256                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4257                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4258                 info->fw = adev->gfx.mec_fw;
4259                 header = (const struct common_firmware_header *)info->fw->data;
4260                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4261                 adev->firmware.fw_size +=
4262                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4263                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4264
4265                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4266                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4267                 info->fw = adev->gfx.mec_fw;
4268                 adev->firmware.fw_size +=
4269                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4270
4271                 if (adev->gfx.mec2_fw) {
4272                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4273                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4274                         info->fw = adev->gfx.mec2_fw;
4275                         header = (const struct common_firmware_header *)info->fw->data;
4276                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4277                         adev->firmware.fw_size +=
4278                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4279                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4280                                       PAGE_SIZE);
4281                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4282                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4283                         info->fw = adev->gfx.mec2_fw;
4284                         adev->firmware.fw_size +=
4285                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4286                                       PAGE_SIZE);
4287                 }
4288         }
4289
4290         gfx_v10_0_check_fw_write_wait(adev);
4291 out:
4292         if (err) {
4293                 dev_err(adev->dev,
4294                         "gfx10: Failed to load firmware \"%s\"\n",
4295                         fw_name);
4296                 release_firmware(adev->gfx.pfp_fw);
4297                 adev->gfx.pfp_fw = NULL;
4298                 release_firmware(adev->gfx.me_fw);
4299                 adev->gfx.me_fw = NULL;
4300                 release_firmware(adev->gfx.ce_fw);
4301                 adev->gfx.ce_fw = NULL;
4302                 release_firmware(adev->gfx.rlc_fw);
4303                 adev->gfx.rlc_fw = NULL;
4304                 release_firmware(adev->gfx.mec_fw);
4305                 adev->gfx.mec_fw = NULL;
4306                 release_firmware(adev->gfx.mec2_fw);
4307                 adev->gfx.mec2_fw = NULL;
4308         }
4309
4310         gfx_v10_0_check_gfxoff_flag(adev);
4311
4312         return err;
4313 }
4314
4315 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4316 {
4317         u32 count = 0;
4318         const struct cs_section_def *sect = NULL;
4319         const struct cs_extent_def *ext = NULL;
4320
4321         /* begin clear state */
4322         count += 2;
4323         /* context control state */
4324         count += 3;
4325
4326         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4327                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4328                         if (sect->id == SECT_CONTEXT)
4329                                 count += 2 + ext->reg_count;
4330                         else
4331                                 return 0;
4332                 }
4333         }
4334
4335         /* set PA_SC_TILE_STEERING_OVERRIDE */
4336         count += 3;
4337         /* end clear state */
4338         count += 2;
4339         /* clear state */
4340         count += 2;
4341
4342         return count;
4343 }
4344
4345 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4346                                     volatile u32 *buffer)
4347 {
4348         u32 count = 0, i;
4349         const struct cs_section_def *sect = NULL;
4350         const struct cs_extent_def *ext = NULL;
4351         int ctx_reg_offset;
4352
4353         if (adev->gfx.rlc.cs_data == NULL)
4354                 return;
4355         if (buffer == NULL)
4356                 return;
4357
4358         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4359         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4360
4361         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4362         buffer[count++] = cpu_to_le32(0x80000000);
4363         buffer[count++] = cpu_to_le32(0x80000000);
4364
4365         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4366                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4367                         if (sect->id == SECT_CONTEXT) {
4368                                 buffer[count++] =
4369                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4370                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4371                                                 PACKET3_SET_CONTEXT_REG_START);
4372                                 for (i = 0; i < ext->reg_count; i++)
4373                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4374                         } else {
4375                                 return;
4376                         }
4377                 }
4378         }
4379
4380         ctx_reg_offset =
4381                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4382         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4383         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4384         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4385
4386         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4387         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4388
4389         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4390         buffer[count++] = cpu_to_le32(0);
4391 }
4392
4393 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4394 {
4395         /* clear state block */
4396         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4397                         &adev->gfx.rlc.clear_state_gpu_addr,
4398                         (void **)&adev->gfx.rlc.cs_ptr);
4399
4400         /* jump table block */
4401         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4402                         &adev->gfx.rlc.cp_table_gpu_addr,
4403                         (void **)&adev->gfx.rlc.cp_table_ptr);
4404 }
4405
4406 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4407 {
4408         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4409
4410         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4411         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4412         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4413         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4414         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4415         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4416         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4417         switch (adev->ip_versions[GC_HWIP][0]) {
4418                 case IP_VERSION(10, 3, 0):
4419                         reg_access_ctrl->spare_int =
4420                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4421                         break;
4422                 default:
4423                         reg_access_ctrl->spare_int =
4424                                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4425                         break;
4426         }
4427         adev->gfx.rlc.rlcg_reg_access_supported = true;
4428 }
4429
4430 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4431 {
4432         const struct cs_section_def *cs_data;
4433         int r;
4434
4435         adev->gfx.rlc.cs_data = gfx10_cs_data;
4436
4437         cs_data = adev->gfx.rlc.cs_data;
4438
4439         if (cs_data) {
4440                 /* init clear state block */
4441                 r = amdgpu_gfx_rlc_init_csb(adev);
4442                 if (r)
4443                         return r;
4444         }
4445
4446         /* init spm vmid with 0xf */
4447         if (adev->gfx.rlc.funcs->update_spm_vmid)
4448                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4449
4450
4451         return 0;
4452 }
4453
4454 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4455 {
4456         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4457         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4458 }
4459
4460 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4461 {
4462         int r;
4463
4464         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4465
4466         amdgpu_gfx_graphics_queue_acquire(adev);
4467
4468         r = gfx_v10_0_init_microcode(adev);
4469         if (r)
4470                 DRM_ERROR("Failed to load gfx firmware!\n");
4471
4472         return r;
4473 }
4474
4475 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4476 {
4477         int r;
4478         u32 *hpd;
4479         const __le32 *fw_data = NULL;
4480         unsigned fw_size;
4481         u32 *fw = NULL;
4482         size_t mec_hpd_size;
4483
4484         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4485
4486         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4487
4488         /* take ownership of the relevant compute queues */
4489         amdgpu_gfx_compute_queue_acquire(adev);
4490         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4491
4492         if (mec_hpd_size) {
4493                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4494                                               AMDGPU_GEM_DOMAIN_GTT,
4495                                               &adev->gfx.mec.hpd_eop_obj,
4496                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4497                                               (void **)&hpd);
4498                 if (r) {
4499                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4500                         gfx_v10_0_mec_fini(adev);
4501                         return r;
4502                 }
4503
4504                 memset(hpd, 0, mec_hpd_size);
4505
4506                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4507                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4508         }
4509
4510         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4511                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4512
4513                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4514                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4515                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4516
4517                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4518                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4519                                               &adev->gfx.mec.mec_fw_obj,
4520                                               &adev->gfx.mec.mec_fw_gpu_addr,
4521                                               (void **)&fw);
4522                 if (r) {
4523                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4524                         gfx_v10_0_mec_fini(adev);
4525                         return r;
4526                 }
4527
4528                 memcpy(fw, fw_data, fw_size);
4529
4530                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4531                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4532         }
4533
4534         return 0;
4535 }
4536
4537 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4538 {
4539         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4540                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4541                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4542         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4543 }
4544
4545 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4546                            uint32_t thread, uint32_t regno,
4547                            uint32_t num, uint32_t *out)
4548 {
4549         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4550                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4551                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4552                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4553                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4554         while (num--)
4555                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4556 }
4557
4558 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4559 {
4560         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4561          * field when performing a select_se_sh so it should be
4562          * zero here */
4563         WARN_ON(simd != 0);
4564
4565         /* type 2 wave data */
4566         dst[(*no_fields)++] = 2;
4567         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4568         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4569         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4570         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4571         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4572         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4573         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4574         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4575         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4576         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4577         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4578         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4579         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4580         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4581         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4582         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4583 }
4584
4585 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4586                                      uint32_t wave, uint32_t start,
4587                                      uint32_t size, uint32_t *dst)
4588 {
4589         WARN_ON(simd != 0);
4590
4591         wave_read_regs(
4592                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4593                 dst);
4594 }
4595
4596 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4597                                       uint32_t wave, uint32_t thread,
4598                                       uint32_t start, uint32_t size,
4599                                       uint32_t *dst)
4600 {
4601         wave_read_regs(
4602                 adev, wave, thread,
4603                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4604 }
4605
4606 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4607                                        u32 me, u32 pipe, u32 q, u32 vm)
4608 {
4609         nv_grbm_select(adev, me, pipe, q, vm);
4610 }
4611
4612 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4613                                           bool enable)
4614 {
4615         uint32_t data, def;
4616
4617         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4618
4619         if (enable)
4620                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4621         else
4622                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4623
4624         if (data != def)
4625                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4626 }
4627
4628 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4629         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4630         .select_se_sh = &gfx_v10_0_select_se_sh,
4631         .read_wave_data = &gfx_v10_0_read_wave_data,
4632         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4633         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4634         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4635         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4636         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4637 };
4638
4639 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4640 {
4641         u32 gb_addr_config;
4642
4643         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4644
4645         switch (adev->ip_versions[GC_HWIP][0]) {
4646         case IP_VERSION(10, 1, 10):
4647         case IP_VERSION(10, 1, 1):
4648         case IP_VERSION(10, 1, 2):
4649                 adev->gfx.config.max_hw_contexts = 8;
4650                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4651                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4652                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4653                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4654                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4655                 break;
4656         case IP_VERSION(10, 3, 0):
4657         case IP_VERSION(10, 3, 2):
4658         case IP_VERSION(10, 3, 1):
4659         case IP_VERSION(10, 3, 4):
4660         case IP_VERSION(10, 3, 5):
4661         case IP_VERSION(10, 3, 6):
4662         case IP_VERSION(10, 3, 3):
4663         case IP_VERSION(10, 3, 7):
4664                 adev->gfx.config.max_hw_contexts = 8;
4665                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4666                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4667                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4668                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4669                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4670                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4671                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4672                 break;
4673         case IP_VERSION(10, 1, 3):
4674         case IP_VERSION(10, 1, 4):
4675                 adev->gfx.config.max_hw_contexts = 8;
4676                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4677                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4678                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4679                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4680                 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4681                 break;
4682         default:
4683                 BUG();
4684                 break;
4685         }
4686
4687         adev->gfx.config.gb_addr_config = gb_addr_config;
4688
4689         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4690                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4691                                       GB_ADDR_CONFIG, NUM_PIPES);
4692
4693         adev->gfx.config.max_tile_pipes =
4694                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4695
4696         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4697                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4698                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4699         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4700                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4701                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4702         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4703                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4704                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4705         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4706                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4707                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4708 }
4709
4710 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4711                                    int me, int pipe, int queue)
4712 {
4713         struct amdgpu_ring *ring;
4714         unsigned int irq_type;
4715         unsigned int hw_prio;
4716
4717         ring = &adev->gfx.gfx_ring[ring_id];
4718
4719         ring->me = me;
4720         ring->pipe = pipe;
4721         ring->queue = queue;
4722
4723         ring->ring_obj = NULL;
4724         ring->use_doorbell = true;
4725
4726         if (!ring_id)
4727                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4728         else
4729                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4730         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4731
4732         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4733         hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4734                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4735         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4736                                 hw_prio, NULL);
4737 }
4738
4739 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4740                                        int mec, int pipe, int queue)
4741 {
4742         unsigned irq_type;
4743         struct amdgpu_ring *ring;
4744         unsigned int hw_prio;
4745
4746         ring = &adev->gfx.compute_ring[ring_id];
4747
4748         /* mec0 is me1 */
4749         ring->me = mec + 1;
4750         ring->pipe = pipe;
4751         ring->queue = queue;
4752
4753         ring->ring_obj = NULL;
4754         ring->use_doorbell = true;
4755         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4756         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4757                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4758         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4759
4760         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4761                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4762                 + ring->pipe;
4763         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4764                         AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4765         /* type-2 packets are deprecated on MEC, use type-3 instead */
4766         return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4767                              hw_prio, NULL);
4768 }
4769
4770 static int gfx_v10_0_sw_init(void *handle)
4771 {
4772         int i, j, k, r, ring_id = 0;
4773         struct amdgpu_kiq *kiq;
4774         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4775
4776         switch (adev->ip_versions[GC_HWIP][0]) {
4777         case IP_VERSION(10, 1, 10):
4778         case IP_VERSION(10, 1, 1):
4779         case IP_VERSION(10, 1, 2):
4780         case IP_VERSION(10, 1, 3):
4781         case IP_VERSION(10, 1, 4):
4782                 adev->gfx.me.num_me = 1;
4783                 adev->gfx.me.num_pipe_per_me = 1;
4784                 adev->gfx.me.num_queue_per_pipe = 1;
4785                 adev->gfx.mec.num_mec = 2;
4786                 adev->gfx.mec.num_pipe_per_mec = 4;
4787                 adev->gfx.mec.num_queue_per_pipe = 8;
4788                 break;
4789         case IP_VERSION(10, 3, 0):
4790         case IP_VERSION(10, 3, 2):
4791         case IP_VERSION(10, 3, 1):
4792         case IP_VERSION(10, 3, 4):
4793         case IP_VERSION(10, 3, 5):
4794         case IP_VERSION(10, 3, 6):
4795         case IP_VERSION(10, 3, 3):
4796         case IP_VERSION(10, 3, 7):
4797                 adev->gfx.me.num_me = 1;
4798                 adev->gfx.me.num_pipe_per_me = 2;
4799                 adev->gfx.me.num_queue_per_pipe = 1;
4800                 adev->gfx.mec.num_mec = 2;
4801                 adev->gfx.mec.num_pipe_per_mec = 4;
4802                 adev->gfx.mec.num_queue_per_pipe = 4;
4803                 break;
4804         default:
4805                 adev->gfx.me.num_me = 1;
4806                 adev->gfx.me.num_pipe_per_me = 1;
4807                 adev->gfx.me.num_queue_per_pipe = 1;
4808                 adev->gfx.mec.num_mec = 1;
4809                 adev->gfx.mec.num_pipe_per_mec = 4;
4810                 adev->gfx.mec.num_queue_per_pipe = 8;
4811                 break;
4812         }
4813
4814         /* KIQ event */
4815         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4816                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4817                               &adev->gfx.kiq.irq);
4818         if (r)
4819                 return r;
4820
4821         /* EOP Event */
4822         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4823                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4824                               &adev->gfx.eop_irq);
4825         if (r)
4826                 return r;
4827
4828         /* Privileged reg */
4829         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4830                               &adev->gfx.priv_reg_irq);
4831         if (r)
4832                 return r;
4833
4834         /* Privileged inst */
4835         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4836                               &adev->gfx.priv_inst_irq);
4837         if (r)
4838                 return r;
4839
4840         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4841
4842         r = gfx_v10_0_me_init(adev);
4843         if (r)
4844                 return r;
4845
4846         if (adev->gfx.rlc.funcs) {
4847                 if (adev->gfx.rlc.funcs->init) {
4848                         r = adev->gfx.rlc.funcs->init(adev);
4849                         if (r) {
4850                                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4851                                 return r;
4852                         }
4853                 }
4854         }
4855
4856         r = gfx_v10_0_mec_init(adev);
4857         if (r) {
4858                 DRM_ERROR("Failed to init MEC BOs!\n");
4859                 return r;
4860         }
4861
4862         /* set up the gfx ring */
4863         for (i = 0; i < adev->gfx.me.num_me; i++) {
4864                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4865                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4866                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4867                                         continue;
4868
4869                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4870                                                             i, k, j);
4871                                 if (r)
4872                                         return r;
4873                                 ring_id++;
4874                         }
4875                 }
4876         }
4877
4878         ring_id = 0;
4879         /* set up the compute queues - allocate horizontally across pipes */
4880         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4881                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4882                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4883                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4884                                                                      j))
4885                                         continue;
4886
4887                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4888                                                                 i, k, j);
4889                                 if (r)
4890                                         return r;
4891
4892                                 ring_id++;
4893                         }
4894                 }
4895         }
4896
4897         if (!adev->enable_mes_kiq) {
4898                 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4899                 if (r) {
4900                         DRM_ERROR("Failed to init KIQ BOs!\n");
4901                         return r;
4902                 }
4903
4904                 kiq = &adev->gfx.kiq;
4905                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4906                 if (r)
4907                         return r;
4908         }
4909
4910         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4911         if (r)
4912                 return r;
4913
4914         /* allocate visible FB for rlc auto-loading fw */
4915         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4916                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4917                 if (r)
4918                         return r;
4919         }
4920
4921         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4922
4923         gfx_v10_0_gpu_early_init(adev);
4924
4925         return 0;
4926 }
4927
4928 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4929 {
4930         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4931                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4932                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4933 }
4934
4935 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4936 {
4937         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4938                               &adev->gfx.ce.ce_fw_gpu_addr,
4939                               (void **)&adev->gfx.ce.ce_fw_ptr);
4940 }
4941
4942 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4943 {
4944         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4945                               &adev->gfx.me.me_fw_gpu_addr,
4946                               (void **)&adev->gfx.me.me_fw_ptr);
4947 }
4948
4949 static int gfx_v10_0_sw_fini(void *handle)
4950 {
4951         int i;
4952         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4953
4954         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4955                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4956         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4957                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4958
4959         amdgpu_gfx_mqd_sw_fini(adev);
4960
4961         if (!adev->enable_mes_kiq) {
4962                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4963                 amdgpu_gfx_kiq_fini(adev);
4964         }
4965
4966         gfx_v10_0_pfp_fini(adev);
4967         gfx_v10_0_ce_fini(adev);
4968         gfx_v10_0_me_fini(adev);
4969         gfx_v10_0_rlc_fini(adev);
4970         gfx_v10_0_mec_fini(adev);
4971
4972         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4973                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4974
4975         gfx_v10_0_free_microcode(adev);
4976
4977         return 0;
4978 }
4979
4980 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4981                                    u32 sh_num, u32 instance)
4982 {
4983         u32 data;
4984
4985         if (instance == 0xffffffff)
4986                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4987                                      INSTANCE_BROADCAST_WRITES, 1);
4988         else
4989                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4990                                      instance);
4991
4992         if (se_num == 0xffffffff)
4993                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4994                                      1);
4995         else
4996                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4997
4998         if (sh_num == 0xffffffff)
4999                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5000                                      1);
5001         else
5002                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5003
5004         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5005 }
5006
5007 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5008 {
5009         u32 data, mask;
5010
5011         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5012         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5013
5014         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5015         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5016
5017         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5018                                          adev->gfx.config.max_sh_per_se);
5019
5020         return (~data) & mask;
5021 }
5022
5023 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5024 {
5025         int i, j;
5026         u32 data;
5027         u32 active_rbs = 0;
5028         u32 bitmap;
5029         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5030                                         adev->gfx.config.max_sh_per_se;
5031
5032         mutex_lock(&adev->grbm_idx_mutex);
5033         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5034                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5035                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
5036                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5037                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5038                                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5039                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5040                                 continue;
5041                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5042                         data = gfx_v10_0_get_rb_active_bitmap(adev);
5043                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5044                                                rb_bitmap_width_per_sh);
5045                 }
5046         }
5047         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5048         mutex_unlock(&adev->grbm_idx_mutex);
5049
5050         adev->gfx.config.backend_enable_mask = active_rbs;
5051         adev->gfx.config.num_rbs = hweight32(active_rbs);
5052 }
5053
5054 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5055 {
5056         uint32_t num_sc;
5057         uint32_t enabled_rb_per_sh;
5058         uint32_t active_rb_bitmap;
5059         uint32_t num_rb_per_sc;
5060         uint32_t num_packer_per_sc;
5061         uint32_t pa_sc_tile_steering_override;
5062
5063         /* for ASICs that integrates GFX v10.3
5064          * pa_sc_tile_steering_override should be set to 0 */
5065         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5066                 return 0;
5067
5068         /* init num_sc */
5069         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5070                         adev->gfx.config.num_sc_per_sh;
5071         /* init num_rb_per_sc */
5072         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5073         enabled_rb_per_sh = hweight32(active_rb_bitmap);
5074         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5075         /* init num_packer_per_sc */
5076         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5077
5078         pa_sc_tile_steering_override = 0;
5079         pa_sc_tile_steering_override |=
5080                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5081                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5082         pa_sc_tile_steering_override |=
5083                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5084                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5085         pa_sc_tile_steering_override |=
5086                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5087                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5088
5089         return pa_sc_tile_steering_override;
5090 }
5091
5092 #define DEFAULT_SH_MEM_BASES    (0x6000)
5093
5094 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5095 {
5096         int i;
5097         uint32_t sh_mem_bases;
5098
5099         /*
5100          * Configure apertures:
5101          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5102          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5103          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5104          */
5105         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5106
5107         mutex_lock(&adev->srbm_mutex);
5108         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5109                 nv_grbm_select(adev, 0, 0, 0, i);
5110                 /* CP and shaders */
5111                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5112                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5113         }
5114         nv_grbm_select(adev, 0, 0, 0, 0);
5115         mutex_unlock(&adev->srbm_mutex);
5116
5117         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5118            access. These should be enabled by FW for target VMIDs. */
5119         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5120                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5121                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5122                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5123                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5124         }
5125 }
5126
5127 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5128 {
5129         int vmid;
5130
5131         /*
5132          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5133          * access. Compute VMIDs should be enabled by FW for target VMIDs,
5134          * the driver can enable them for graphics. VMID0 should maintain
5135          * access so that HWS firmware can save/restore entries.
5136          */
5137         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5138                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5139                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5140                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5141                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5142         }
5143 }
5144
5145
5146 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5147 {
5148         int i, j, k;
5149         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5150         u32 tmp, wgp_active_bitmap = 0;
5151         u32 gcrd_targets_disable_tcp = 0;
5152         u32 utcl_invreq_disable = 0;
5153         /*
5154          * GCRD_TARGETS_DISABLE field contains
5155          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5156          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5157          */
5158         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5159                 2 * max_wgp_per_sh + /* TCP */
5160                 max_wgp_per_sh + /* SQC */
5161                 4); /* GL1C */
5162         /*
5163          * UTCL1_UTCL0_INVREQ_DISABLE field contains
5164          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5165          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5166          */
5167         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5168                 2 * max_wgp_per_sh + /* TCP */
5169                 2 * max_wgp_per_sh + /* SQC */
5170                 4 + /* RMI */
5171                 1); /* SQG */
5172
5173         mutex_lock(&adev->grbm_idx_mutex);
5174         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5175                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5176                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5177                         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5178                         /*
5179                          * Set corresponding TCP bits for the inactive WGPs in
5180                          * GCRD_SA_TARGETS_DISABLE
5181                          */
5182                         gcrd_targets_disable_tcp = 0;
5183                         /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5184                         utcl_invreq_disable = 0;
5185
5186                         for (k = 0; k < max_wgp_per_sh; k++) {
5187                                 if (!(wgp_active_bitmap & (1 << k))) {
5188                                         gcrd_targets_disable_tcp |= 3 << (2 * k);
5189                                         gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5190                                         utcl_invreq_disable |= (3 << (2 * k)) |
5191                                                 (3 << (2 * (max_wgp_per_sh + k)));
5192                                 }
5193                         }
5194
5195                         tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5196                         /* only override TCP & SQC bits */
5197                         tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5198                         tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5199                         WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5200
5201                         tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5202                         /* only override TCP & SQC bits */
5203                         tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5204                         tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5205                         WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5206                 }
5207         }
5208
5209         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5210         mutex_unlock(&adev->grbm_idx_mutex);
5211 }
5212
5213 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5214 {
5215         /* TCCs are global (not instanced). */
5216         uint32_t tcc_disable;
5217
5218         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5219                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5220                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5221         } else {
5222                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5223                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5224         }
5225
5226         adev->gfx.config.tcc_disabled_mask =
5227                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5228                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5229 }
5230
5231 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5232 {
5233         u32 tmp;
5234         int i;
5235
5236         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5237
5238         gfx_v10_0_setup_rb(adev);
5239         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5240         gfx_v10_0_get_tcc_info(adev);
5241         adev->gfx.config.pa_sc_tile_steering_override =
5242                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5243
5244         /* XXX SH_MEM regs */
5245         /* where to put LDS, scratch, GPUVM in FSA64 space */
5246         mutex_lock(&adev->srbm_mutex);
5247         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5248                 nv_grbm_select(adev, 0, 0, 0, i);
5249                 /* CP and shaders */
5250                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5251                 if (i != 0) {
5252                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5253                                 (adev->gmc.private_aperture_start >> 48));
5254                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5255                                 (adev->gmc.shared_aperture_start >> 48));
5256                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5257                 }
5258         }
5259         nv_grbm_select(adev, 0, 0, 0, 0);
5260
5261         mutex_unlock(&adev->srbm_mutex);
5262
5263         gfx_v10_0_init_compute_vmid(adev);
5264         gfx_v10_0_init_gds_vmid(adev);
5265
5266 }
5267
5268 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5269                                                bool enable)
5270 {
5271         u32 tmp;
5272
5273         if (amdgpu_sriov_vf(adev))
5274                 return;
5275
5276         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5277
5278         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5279                             enable ? 1 : 0);
5280         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5281                             enable ? 1 : 0);
5282         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5283                             enable ? 1 : 0);
5284         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5285                             enable ? 1 : 0);
5286
5287         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5288 }
5289
5290 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5291 {
5292         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5293
5294         /* csib */
5295         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5296                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5297                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5298                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5299                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5300                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5301         } else {
5302                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5303                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5304                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5305                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5306                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5307         }
5308         return 0;
5309 }
5310
5311 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5312 {
5313         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5314
5315         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5316         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5317 }
5318
5319 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5320 {
5321         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5322         udelay(50);
5323         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5324         udelay(50);
5325 }
5326
5327 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5328                                              bool enable)
5329 {
5330         uint32_t rlc_pg_cntl;
5331
5332         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5333
5334         if (!enable) {
5335                 /* RLC_PG_CNTL[23] = 0 (default)
5336                  * RLC will wait for handshake acks with SMU
5337                  * GFXOFF will be enabled
5338                  * RLC_PG_CNTL[23] = 1
5339                  * RLC will not issue any message to SMU
5340                  * hence no handshake between SMU & RLC
5341                  * GFXOFF will be disabled
5342                  */
5343                 rlc_pg_cntl |= 0x800000;
5344         } else
5345                 rlc_pg_cntl &= ~0x800000;
5346         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5347 }
5348
5349 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5350 {
5351         /* TODO: enable rlc & smu handshake until smu
5352          * and gfxoff feature works as expected */
5353         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5354                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5355
5356         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5357         udelay(50);
5358 }
5359
5360 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5361 {
5362         uint32_t tmp;
5363
5364         /* enable Save Restore Machine */
5365         tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5366         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5367         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5368         WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5369 }
5370
5371 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5372 {
5373         const struct rlc_firmware_header_v2_0 *hdr;
5374         const __le32 *fw_data;
5375         unsigned i, fw_size;
5376
5377         if (!adev->gfx.rlc_fw)
5378                 return -EINVAL;
5379
5380         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5381         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5382
5383         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5384                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5385         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5386
5387         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5388                      RLCG_UCODE_LOADING_START_ADDRESS);
5389
5390         for (i = 0; i < fw_size; i++)
5391                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5392                              le32_to_cpup(fw_data++));
5393
5394         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5395
5396         return 0;
5397 }
5398
5399 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5400 {
5401         int r;
5402
5403         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5404                 adev->psp.autoload_supported) {
5405
5406                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5407                 if (r)
5408                         return r;
5409
5410                 gfx_v10_0_init_csb(adev);
5411
5412                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5413                         gfx_v10_0_rlc_enable_srm(adev);
5414         } else {
5415                 if (amdgpu_sriov_vf(adev)) {
5416                         gfx_v10_0_init_csb(adev);
5417                         return 0;
5418                 }
5419
5420                 adev->gfx.rlc.funcs->stop(adev);
5421
5422                 /* disable CG */
5423                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5424
5425                 /* disable PG */
5426                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5427
5428                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5429                         /* legacy rlc firmware loading */
5430                         r = gfx_v10_0_rlc_load_microcode(adev);
5431                         if (r)
5432                                 return r;
5433                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5434                         /* rlc backdoor autoload firmware */
5435                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5436                         if (r)
5437                                 return r;
5438                 }
5439
5440                 gfx_v10_0_init_csb(adev);
5441
5442                 adev->gfx.rlc.funcs->start(adev);
5443
5444                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5445                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5446                         if (r)
5447                                 return r;
5448                 }
5449         }
5450         return 0;
5451 }
5452
5453 static struct {
5454         FIRMWARE_ID     id;
5455         unsigned int    offset;
5456         unsigned int    size;
5457 } rlc_autoload_info[FIRMWARE_ID_MAX];
5458
5459 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5460 {
5461         int ret;
5462         RLC_TABLE_OF_CONTENT *rlc_toc;
5463
5464         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5465                                         AMDGPU_GEM_DOMAIN_GTT,
5466                                         &adev->gfx.rlc.rlc_toc_bo,
5467                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5468                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5469         if (ret) {
5470                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5471                 return ret;
5472         }
5473
5474         /* Copy toc from psp sos fw to rlc toc buffer */
5475         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5476
5477         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5478         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5479                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5480                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5481                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5482                         /* Offset needs 4KB alignment */
5483                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5484                 }
5485
5486                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5487                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5488                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5489
5490                 rlc_toc++;
5491         }
5492
5493         return 0;
5494 }
5495
5496 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5497 {
5498         uint32_t total_size = 0;
5499         FIRMWARE_ID id;
5500         int ret;
5501
5502         ret = gfx_v10_0_parse_rlc_toc(adev);
5503         if (ret) {
5504                 dev_err(adev->dev, "failed to parse rlc toc\n");
5505                 return 0;
5506         }
5507
5508         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5509                 total_size += rlc_autoload_info[id].size;
5510
5511         /* In case the offset in rlc toc ucode is aligned */
5512         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5513                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5514                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5515
5516         return total_size;
5517 }
5518
5519 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5520 {
5521         int r;
5522         uint32_t total_size;
5523
5524         total_size = gfx_v10_0_calc_toc_total_size(adev);
5525
5526         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5527                                       AMDGPU_GEM_DOMAIN_GTT,
5528                                       &adev->gfx.rlc.rlc_autoload_bo,
5529                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5530                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5531         if (r) {
5532                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5533                 return r;
5534         }
5535
5536         return 0;
5537 }
5538
5539 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5540 {
5541         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5542                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5543                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5544         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5545                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5546                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5547 }
5548
5549 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5550                                                        FIRMWARE_ID id,
5551                                                        const void *fw_data,
5552                                                        uint32_t fw_size)
5553 {
5554         uint32_t toc_offset;
5555         uint32_t toc_fw_size;
5556         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5557
5558         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5559                 return;
5560
5561         toc_offset = rlc_autoload_info[id].offset;
5562         toc_fw_size = rlc_autoload_info[id].size;
5563
5564         if (fw_size == 0)
5565                 fw_size = toc_fw_size;
5566
5567         if (fw_size > toc_fw_size)
5568                 fw_size = toc_fw_size;
5569
5570         memcpy(ptr + toc_offset, fw_data, fw_size);
5571
5572         if (fw_size < toc_fw_size)
5573                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5574 }
5575
5576 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5577 {
5578         void *data;
5579         uint32_t size;
5580
5581         data = adev->gfx.rlc.rlc_toc_buf;
5582         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5583
5584         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5585                                                    FIRMWARE_ID_RLC_TOC,
5586                                                    data, size);
5587 }
5588
5589 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5590 {
5591         const __le32 *fw_data;
5592         uint32_t fw_size;
5593         const struct gfx_firmware_header_v1_0 *cp_hdr;
5594         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5595
5596         /* pfp ucode */
5597         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5598                 adev->gfx.pfp_fw->data;
5599         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5600                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5601         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5602         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5603                                                    FIRMWARE_ID_CP_PFP,
5604                                                    fw_data, fw_size);
5605
5606         /* ce ucode */
5607         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5608                 adev->gfx.ce_fw->data;
5609         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5610                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5611         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5612         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5613                                                    FIRMWARE_ID_CP_CE,
5614                                                    fw_data, fw_size);
5615
5616         /* me ucode */
5617         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5618                 adev->gfx.me_fw->data;
5619         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5620                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5621         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5622         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5623                                                    FIRMWARE_ID_CP_ME,
5624                                                    fw_data, fw_size);
5625
5626         /* rlc ucode */
5627         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5628                 adev->gfx.rlc_fw->data;
5629         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5630                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5631         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5632         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5633                                                    FIRMWARE_ID_RLC_G_UCODE,
5634                                                    fw_data, fw_size);
5635
5636         /* mec1 ucode */
5637         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5638                 adev->gfx.mec_fw->data;
5639         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5640                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5641         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5642                 cp_hdr->jt_size * 4;
5643         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5644                                                    FIRMWARE_ID_CP_MEC,
5645                                                    fw_data, fw_size);
5646         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5647 }
5648
5649 /* Temporarily put sdma part here */
5650 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5651 {
5652         const __le32 *fw_data;
5653         uint32_t fw_size;
5654         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5655         int i;
5656
5657         for (i = 0; i < adev->sdma.num_instances; i++) {
5658                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5659                         adev->sdma.instance[i].fw->data;
5660                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5661                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5662                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5663
5664                 if (i == 0) {
5665                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5666                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5667                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5668                                 FIRMWARE_ID_SDMA0_JT,
5669                                 (uint32_t *)fw_data +
5670                                 sdma_hdr->jt_offset,
5671                                 sdma_hdr->jt_size * 4);
5672                 } else if (i == 1) {
5673                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5674                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5675                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5676                                 FIRMWARE_ID_SDMA1_JT,
5677                                 (uint32_t *)fw_data +
5678                                 sdma_hdr->jt_offset,
5679                                 sdma_hdr->jt_size * 4);
5680                 }
5681         }
5682 }
5683
5684 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5685 {
5686         uint32_t rlc_g_offset, rlc_g_size, tmp;
5687         uint64_t gpu_addr;
5688
5689         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5690         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5691         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5692
5693         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5694         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5695         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5696
5697         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5698         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5699         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5700
5701         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5702         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5703                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5704                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5705                 return -EINVAL;
5706         }
5707
5708         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5709         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5710                 DRM_ERROR("RLC ROM should halt itself\n");
5711                 return -EINVAL;
5712         }
5713
5714         return 0;
5715 }
5716
5717 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5718 {
5719         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5720         uint32_t tmp;
5721         int i;
5722         uint64_t addr;
5723
5724         /* Trigger an invalidation of the L1 instruction caches */
5725         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5726         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5727         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5728
5729         /* Wait for invalidation complete */
5730         for (i = 0; i < usec_timeout; i++) {
5731                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5732                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5733                         INVALIDATE_CACHE_COMPLETE))
5734                         break;
5735                 udelay(1);
5736         }
5737
5738         if (i >= usec_timeout) {
5739                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5740                 return -EINVAL;
5741         }
5742
5743         /* Program me ucode address into intruction cache address register */
5744         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5745                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5746         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5747                         lower_32_bits(addr) & 0xFFFFF000);
5748         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5749                         upper_32_bits(addr));
5750
5751         return 0;
5752 }
5753
5754 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5755 {
5756         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5757         uint32_t tmp;
5758         int i;
5759         uint64_t addr;
5760
5761         /* Trigger an invalidation of the L1 instruction caches */
5762         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5763         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5764         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5765
5766         /* Wait for invalidation complete */
5767         for (i = 0; i < usec_timeout; i++) {
5768                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5769                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5770                         INVALIDATE_CACHE_COMPLETE))
5771                         break;
5772                 udelay(1);
5773         }
5774
5775         if (i >= usec_timeout) {
5776                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5777                 return -EINVAL;
5778         }
5779
5780         /* Program ce ucode address into intruction cache address register */
5781         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5782                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5783         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5784                         lower_32_bits(addr) & 0xFFFFF000);
5785         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5786                         upper_32_bits(addr));
5787
5788         return 0;
5789 }
5790
5791 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5792 {
5793         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5794         uint32_t tmp;
5795         int i;
5796         uint64_t addr;
5797
5798         /* Trigger an invalidation of the L1 instruction caches */
5799         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5800         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5801         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5802
5803         /* Wait for invalidation complete */
5804         for (i = 0; i < usec_timeout; i++) {
5805                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5806                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5807                         INVALIDATE_CACHE_COMPLETE))
5808                         break;
5809                 udelay(1);
5810         }
5811
5812         if (i >= usec_timeout) {
5813                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5814                 return -EINVAL;
5815         }
5816
5817         /* Program pfp ucode address into intruction cache address register */
5818         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5819                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5820         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5821                         lower_32_bits(addr) & 0xFFFFF000);
5822         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5823                         upper_32_bits(addr));
5824
5825         return 0;
5826 }
5827
5828 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5829 {
5830         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5831         uint32_t tmp;
5832         int i;
5833         uint64_t addr;
5834
5835         /* Trigger an invalidation of the L1 instruction caches */
5836         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5837         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5838         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5839
5840         /* Wait for invalidation complete */
5841         for (i = 0; i < usec_timeout; i++) {
5842                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5843                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5844                         INVALIDATE_CACHE_COMPLETE))
5845                         break;
5846                 udelay(1);
5847         }
5848
5849         if (i >= usec_timeout) {
5850                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5851                 return -EINVAL;
5852         }
5853
5854         /* Program mec1 ucode address into intruction cache address register */
5855         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5856                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5857         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5858                         lower_32_bits(addr) & 0xFFFFF000);
5859         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5860                         upper_32_bits(addr));
5861
5862         return 0;
5863 }
5864
5865 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5866 {
5867         uint32_t cp_status;
5868         uint32_t bootload_status;
5869         int i, r;
5870
5871         for (i = 0; i < adev->usec_timeout; i++) {
5872                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5873                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5874                 if ((cp_status == 0) &&
5875                     (REG_GET_FIELD(bootload_status,
5876                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5877                         break;
5878                 }
5879                 udelay(1);
5880         }
5881
5882         if (i >= adev->usec_timeout) {
5883                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5884                 return -ETIMEDOUT;
5885         }
5886
5887         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5888                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5889                 if (r)
5890                         return r;
5891
5892                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5893                 if (r)
5894                         return r;
5895
5896                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5897                 if (r)
5898                         return r;
5899
5900                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5901                 if (r)
5902                         return r;
5903         }
5904
5905         return 0;
5906 }
5907
5908 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5909 {
5910         int i;
5911         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5912
5913         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5914         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5915         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5916
5917         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5918                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5919         } else {
5920                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5921         }
5922
5923         for (i = 0; i < adev->usec_timeout; i++) {
5924                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5925                         break;
5926                 udelay(1);
5927         }
5928
5929         if (i >= adev->usec_timeout)
5930                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5931
5932         return 0;
5933 }
5934
5935 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5936 {
5937         int r;
5938         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5939         const __le32 *fw_data;
5940         unsigned i, fw_size;
5941         uint32_t tmp;
5942         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5943
5944         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5945                 adev->gfx.pfp_fw->data;
5946
5947         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5948
5949         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5950                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5951         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5952
5953         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5954                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5955                                       &adev->gfx.pfp.pfp_fw_obj,
5956                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5957                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5958         if (r) {
5959                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5960                 gfx_v10_0_pfp_fini(adev);
5961                 return r;
5962         }
5963
5964         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5965
5966         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5967         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5968
5969         /* Trigger an invalidation of the L1 instruction caches */
5970         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5971         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5972         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5973
5974         /* Wait for invalidation complete */
5975         for (i = 0; i < usec_timeout; i++) {
5976                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5977                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5978                         INVALIDATE_CACHE_COMPLETE))
5979                         break;
5980                 udelay(1);
5981         }
5982
5983         if (i >= usec_timeout) {
5984                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5985                 return -EINVAL;
5986         }
5987
5988         if (amdgpu_emu_mode == 1)
5989                 adev->hdp.funcs->flush_hdp(adev, NULL);
5990
5991         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5992         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5993         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5994         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5995         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5996         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5997         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5998                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5999         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6000                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6001
6002         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6003
6004         for (i = 0; i < pfp_hdr->jt_size; i++)
6005                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6006                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6007
6008         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6009
6010         return 0;
6011 }
6012
6013 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6014 {
6015         int r;
6016         const struct gfx_firmware_header_v1_0 *ce_hdr;
6017         const __le32 *fw_data;
6018         unsigned i, fw_size;
6019         uint32_t tmp;
6020         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6021
6022         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6023                 adev->gfx.ce_fw->data;
6024
6025         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6026
6027         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6028                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6029         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6030
6031         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6032                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6033                                       &adev->gfx.ce.ce_fw_obj,
6034                                       &adev->gfx.ce.ce_fw_gpu_addr,
6035                                       (void **)&adev->gfx.ce.ce_fw_ptr);
6036         if (r) {
6037                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6038                 gfx_v10_0_ce_fini(adev);
6039                 return r;
6040         }
6041
6042         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6043
6044         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6045         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6046
6047         /* Trigger an invalidation of the L1 instruction caches */
6048         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6049         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6050         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6051
6052         /* Wait for invalidation complete */
6053         for (i = 0; i < usec_timeout; i++) {
6054                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6055                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6056                         INVALIDATE_CACHE_COMPLETE))
6057                         break;
6058                 udelay(1);
6059         }
6060
6061         if (i >= usec_timeout) {
6062                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6063                 return -EINVAL;
6064         }
6065
6066         if (amdgpu_emu_mode == 1)
6067                 adev->hdp.funcs->flush_hdp(adev, NULL);
6068
6069         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6070         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6071         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6072         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6073         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6074         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6075                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6076         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6077                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6078
6079         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6080
6081         for (i = 0; i < ce_hdr->jt_size; i++)
6082                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6083                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6084
6085         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6086
6087         return 0;
6088 }
6089
6090 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6091 {
6092         int r;
6093         const struct gfx_firmware_header_v1_0 *me_hdr;
6094         const __le32 *fw_data;
6095         unsigned i, fw_size;
6096         uint32_t tmp;
6097         uint32_t usec_timeout = 50000;  /* wait for 50ms */
6098
6099         me_hdr = (const struct gfx_firmware_header_v1_0 *)
6100                 adev->gfx.me_fw->data;
6101
6102         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6103
6104         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6105                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6106         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6107
6108         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6109                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6110                                       &adev->gfx.me.me_fw_obj,
6111                                       &adev->gfx.me.me_fw_gpu_addr,
6112                                       (void **)&adev->gfx.me.me_fw_ptr);
6113         if (r) {
6114                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6115                 gfx_v10_0_me_fini(adev);
6116                 return r;
6117         }
6118
6119         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6120
6121         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6122         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6123
6124         /* Trigger an invalidation of the L1 instruction caches */
6125         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6126         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6127         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6128
6129         /* Wait for invalidation complete */
6130         for (i = 0; i < usec_timeout; i++) {
6131                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6132                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6133                         INVALIDATE_CACHE_COMPLETE))
6134                         break;
6135                 udelay(1);
6136         }
6137
6138         if (i >= usec_timeout) {
6139                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6140                 return -EINVAL;
6141         }
6142
6143         if (amdgpu_emu_mode == 1)
6144                 adev->hdp.funcs->flush_hdp(adev, NULL);
6145
6146         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6147         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6148         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6149         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6150         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6151         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6152                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6153         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6154                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6155
6156         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6157
6158         for (i = 0; i < me_hdr->jt_size; i++)
6159                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6160                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6161
6162         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6163
6164         return 0;
6165 }
6166
6167 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6168 {
6169         int r;
6170
6171         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6172                 return -EINVAL;
6173
6174         gfx_v10_0_cp_gfx_enable(adev, false);
6175
6176         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6177         if (r) {
6178                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6179                 return r;
6180         }
6181
6182         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6183         if (r) {
6184                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6185                 return r;
6186         }
6187
6188         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6189         if (r) {
6190                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6191                 return r;
6192         }
6193
6194         return 0;
6195 }
6196
6197 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6198 {
6199         struct amdgpu_ring *ring;
6200         const struct cs_section_def *sect = NULL;
6201         const struct cs_extent_def *ext = NULL;
6202         int r, i;
6203         int ctx_reg_offset;
6204
6205         /* init the CP */
6206         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6207                      adev->gfx.config.max_hw_contexts - 1);
6208         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6209
6210         gfx_v10_0_cp_gfx_enable(adev, true);
6211
6212         ring = &adev->gfx.gfx_ring[0];
6213         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6214         if (r) {
6215                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6216                 return r;
6217         }
6218
6219         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6220         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6221
6222         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6223         amdgpu_ring_write(ring, 0x80000000);
6224         amdgpu_ring_write(ring, 0x80000000);
6225
6226         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6227                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6228                         if (sect->id == SECT_CONTEXT) {
6229                                 amdgpu_ring_write(ring,
6230                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
6231                                                           ext->reg_count));
6232                                 amdgpu_ring_write(ring, ext->reg_index -
6233                                                   PACKET3_SET_CONTEXT_REG_START);
6234                                 for (i = 0; i < ext->reg_count; i++)
6235                                         amdgpu_ring_write(ring, ext->extent[i]);
6236                         }
6237                 }
6238         }
6239
6240         ctx_reg_offset =
6241                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6242         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6243         amdgpu_ring_write(ring, ctx_reg_offset);
6244         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6245
6246         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6247         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6248
6249         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6250         amdgpu_ring_write(ring, 0);
6251
6252         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6253         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6254         amdgpu_ring_write(ring, 0x8000);
6255         amdgpu_ring_write(ring, 0x8000);
6256
6257         amdgpu_ring_commit(ring);
6258
6259         /* submit cs packet to copy state 0 to next available state */
6260         if (adev->gfx.num_gfx_rings > 1) {
6261                 /* maximum supported gfx ring is 2 */
6262                 ring = &adev->gfx.gfx_ring[1];
6263                 r = amdgpu_ring_alloc(ring, 2);
6264                 if (r) {
6265                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6266                         return r;
6267                 }
6268
6269                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6270                 amdgpu_ring_write(ring, 0);
6271
6272                 amdgpu_ring_commit(ring);
6273         }
6274         return 0;
6275 }
6276
6277 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6278                                          CP_PIPE_ID pipe)
6279 {
6280         u32 tmp;
6281
6282         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6283         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6284
6285         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6286 }
6287
6288 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6289                                           struct amdgpu_ring *ring)
6290 {
6291         u32 tmp;
6292
6293         if (!amdgpu_async_gfx_ring) {
6294                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6295                 if (ring->use_doorbell) {
6296                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6297                                                 DOORBELL_OFFSET, ring->doorbell_index);
6298                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6299                                                 DOORBELL_EN, 1);
6300                 } else {
6301                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6302                                                 DOORBELL_EN, 0);
6303                 }
6304                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6305         }
6306         switch (adev->ip_versions[GC_HWIP][0]) {
6307         case IP_VERSION(10, 3, 0):
6308         case IP_VERSION(10, 3, 2):
6309         case IP_VERSION(10, 3, 1):
6310         case IP_VERSION(10, 3, 4):
6311         case IP_VERSION(10, 3, 5):
6312         case IP_VERSION(10, 3, 6):
6313         case IP_VERSION(10, 3, 3):
6314         case IP_VERSION(10, 3, 7):
6315                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6316                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6317                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6318
6319                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6320                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6321                 break;
6322         default:
6323                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6324                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6325                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6326
6327                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6328                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6329                 break;
6330         }
6331 }
6332
6333 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6334 {
6335         struct amdgpu_ring *ring;
6336         u32 tmp;
6337         u32 rb_bufsz;
6338         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6339         u32 i;
6340
6341         /* Set the write pointer delay */
6342         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6343
6344         /* set the RB to use vmid 0 */
6345         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6346
6347         /* Init gfx ring 0 for pipe 0 */
6348         mutex_lock(&adev->srbm_mutex);
6349         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6350
6351         /* Set ring buffer size */
6352         ring = &adev->gfx.gfx_ring[0];
6353         rb_bufsz = order_base_2(ring->ring_size / 8);
6354         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6355         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6356 #ifdef __BIG_ENDIAN
6357         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6358 #endif
6359         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6360
6361         /* Initialize the ring buffer's write pointers */
6362         ring->wptr = 0;
6363         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6364         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6365
6366         /* set the wb address wether it's enabled or not */
6367         rptr_addr = ring->rptr_gpu_addr;
6368         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6369         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6370                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6371
6372         wptr_gpu_addr = ring->wptr_gpu_addr;
6373         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6374                      lower_32_bits(wptr_gpu_addr));
6375         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6376                      upper_32_bits(wptr_gpu_addr));
6377
6378         mdelay(1);
6379         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6380
6381         rb_addr = ring->gpu_addr >> 8;
6382         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6383         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6384
6385         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6386
6387         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6388         mutex_unlock(&adev->srbm_mutex);
6389
6390         /* Init gfx ring 1 for pipe 1 */
6391         if (adev->gfx.num_gfx_rings > 1) {
6392                 mutex_lock(&adev->srbm_mutex);
6393                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6394                 /* maximum supported gfx ring is 2 */
6395                 ring = &adev->gfx.gfx_ring[1];
6396                 rb_bufsz = order_base_2(ring->ring_size / 8);
6397                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6398                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6399                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6400                 /* Initialize the ring buffer's write pointers */
6401                 ring->wptr = 0;
6402                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6403                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6404                 /* Set the wb address wether it's enabled or not */
6405                 rptr_addr = ring->rptr_gpu_addr;
6406                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6407                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6408                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6409                 wptr_gpu_addr = ring->wptr_gpu_addr;
6410                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6411                              lower_32_bits(wptr_gpu_addr));
6412                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6413                              upper_32_bits(wptr_gpu_addr));
6414
6415                 mdelay(1);
6416                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6417
6418                 rb_addr = ring->gpu_addr >> 8;
6419                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6420                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6421                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6422
6423                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6424                 mutex_unlock(&adev->srbm_mutex);
6425         }
6426         /* Switch to pipe 0 */
6427         mutex_lock(&adev->srbm_mutex);
6428         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6429         mutex_unlock(&adev->srbm_mutex);
6430
6431         /* start the ring */
6432         gfx_v10_0_cp_gfx_start(adev);
6433
6434         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6435                 ring = &adev->gfx.gfx_ring[i];
6436                 ring->sched.ready = true;
6437         }
6438
6439         return 0;
6440 }
6441
6442 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6443 {
6444         if (enable) {
6445                 switch (adev->ip_versions[GC_HWIP][0]) {
6446                 case IP_VERSION(10, 3, 0):
6447                 case IP_VERSION(10, 3, 2):
6448                 case IP_VERSION(10, 3, 1):
6449                 case IP_VERSION(10, 3, 4):
6450                 case IP_VERSION(10, 3, 5):
6451                 case IP_VERSION(10, 3, 6):
6452                 case IP_VERSION(10, 3, 3):
6453                 case IP_VERSION(10, 3, 7):
6454                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6455                         break;
6456                 default:
6457                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6458                         break;
6459                 }
6460         } else {
6461                 switch (adev->ip_versions[GC_HWIP][0]) {
6462                 case IP_VERSION(10, 3, 0):
6463                 case IP_VERSION(10, 3, 2):
6464                 case IP_VERSION(10, 3, 1):
6465                 case IP_VERSION(10, 3, 4):
6466                 case IP_VERSION(10, 3, 5):
6467                 case IP_VERSION(10, 3, 6):
6468                 case IP_VERSION(10, 3, 3):
6469                 case IP_VERSION(10, 3, 7):
6470                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6471                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6472                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6473                         break;
6474                 default:
6475                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6476                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6477                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6478                         break;
6479                 }
6480                 adev->gfx.kiq.ring.sched.ready = false;
6481         }
6482         udelay(50);
6483 }
6484
6485 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6486 {
6487         const struct gfx_firmware_header_v1_0 *mec_hdr;
6488         const __le32 *fw_data;
6489         unsigned i;
6490         u32 tmp;
6491         u32 usec_timeout = 50000; /* Wait for 50 ms */
6492
6493         if (!adev->gfx.mec_fw)
6494                 return -EINVAL;
6495
6496         gfx_v10_0_cp_compute_enable(adev, false);
6497
6498         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6499         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6500
6501         fw_data = (const __le32 *)
6502                 (adev->gfx.mec_fw->data +
6503                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6504
6505         /* Trigger an invalidation of the L1 instruction caches */
6506         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6507         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6508         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6509
6510         /* Wait for invalidation complete */
6511         for (i = 0; i < usec_timeout; i++) {
6512                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6513                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6514                                        INVALIDATE_CACHE_COMPLETE))
6515                         break;
6516                 udelay(1);
6517         }
6518
6519         if (i >= usec_timeout) {
6520                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6521                 return -EINVAL;
6522         }
6523
6524         if (amdgpu_emu_mode == 1)
6525                 adev->hdp.funcs->flush_hdp(adev, NULL);
6526
6527         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6528         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6529         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6530         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6531         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6532
6533         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6534                      0xFFFFF000);
6535         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6536                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6537
6538         /* MEC1 */
6539         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6540
6541         for (i = 0; i < mec_hdr->jt_size; i++)
6542                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6543                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6544
6545         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6546
6547         /*
6548          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6549          * different microcode than MEC1.
6550          */
6551
6552         return 0;
6553 }
6554
6555 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6556 {
6557         uint32_t tmp;
6558         struct amdgpu_device *adev = ring->adev;
6559
6560         /* tell RLC which is KIQ queue */
6561         switch (adev->ip_versions[GC_HWIP][0]) {
6562         case IP_VERSION(10, 3, 0):
6563         case IP_VERSION(10, 3, 2):
6564         case IP_VERSION(10, 3, 1):
6565         case IP_VERSION(10, 3, 4):
6566         case IP_VERSION(10, 3, 5):
6567         case IP_VERSION(10, 3, 6):
6568         case IP_VERSION(10, 3, 3):
6569         case IP_VERSION(10, 3, 7):
6570                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6571                 tmp &= 0xffffff00;
6572                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6573                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6574                 tmp |= 0x80;
6575                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6576                 break;
6577         default:
6578                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6579                 tmp &= 0xffffff00;
6580                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6581                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6582                 tmp |= 0x80;
6583                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6584                 break;
6585         }
6586 }
6587
6588 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6589                                            struct v10_gfx_mqd *mqd,
6590                                            struct amdgpu_mqd_prop *prop)
6591 {
6592         bool priority = 0;
6593         u32 tmp;
6594
6595         /* set up default queue priority level
6596          * 0x0 = low priority, 0x1 = high priority
6597          */
6598         if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6599                 priority = 1;
6600
6601         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6602         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6603         mqd->cp_gfx_hqd_queue_priority = tmp;
6604 }
6605
6606 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6607                                   struct amdgpu_mqd_prop *prop)
6608 {
6609         struct v10_gfx_mqd *mqd = m;
6610         uint64_t hqd_gpu_addr, wb_gpu_addr;
6611         uint32_t tmp;
6612         uint32_t rb_bufsz;
6613
6614         /* set up gfx hqd wptr */
6615         mqd->cp_gfx_hqd_wptr = 0;
6616         mqd->cp_gfx_hqd_wptr_hi = 0;
6617
6618         /* set the pointer to the MQD */
6619         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6620         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6621
6622         /* set up mqd control */
6623         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6624         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6625         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6626         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6627         mqd->cp_gfx_mqd_control = tmp;
6628
6629         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6630         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6631         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6632         mqd->cp_gfx_hqd_vmid = 0;
6633
6634         /* set up gfx queue priority */
6635         gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6636
6637         /* set up time quantum */
6638         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6639         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6640         mqd->cp_gfx_hqd_quantum = tmp;
6641
6642         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6643         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6644         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6645         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6646
6647         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6648         wb_gpu_addr = prop->rptr_gpu_addr;
6649         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6650         mqd->cp_gfx_hqd_rptr_addr_hi =
6651                 upper_32_bits(wb_gpu_addr) & 0xffff;
6652
6653         /* set up rb_wptr_poll addr */
6654         wb_gpu_addr = prop->wptr_gpu_addr;
6655         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6656         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6657
6658         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6659         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6660         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6661         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6662         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6663 #ifdef __BIG_ENDIAN
6664         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6665 #endif
6666         mqd->cp_gfx_hqd_cntl = tmp;
6667
6668         /* set up cp_doorbell_control */
6669         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6670         if (prop->use_doorbell) {
6671                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6672                                     DOORBELL_OFFSET, prop->doorbell_index);
6673                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6674                                     DOORBELL_EN, 1);
6675         } else
6676                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6677                                     DOORBELL_EN, 0);
6678         mqd->cp_rb_doorbell_control = tmp;
6679
6680         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6681         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6682
6683         /* active the queue */
6684         mqd->cp_gfx_hqd_active = 1;
6685
6686         return 0;
6687 }
6688
6689 #ifdef BRING_UP_DEBUG
6690 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6691 {
6692         struct amdgpu_device *adev = ring->adev;
6693         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6694
6695         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6696         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6697         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6698
6699         /* set GFX_MQD_BASE */
6700         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6701         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6702
6703         /* set GFX_MQD_CONTROL */
6704         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6705
6706         /* set GFX_HQD_VMID to 0 */
6707         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6708
6709         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6710                         mqd->cp_gfx_hqd_queue_priority);
6711         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6712
6713         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6714         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6715         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6716
6717         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6718         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6719         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6720
6721         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6722         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6723
6724         /* set RB_WPTR_POLL_ADDR */
6725         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6726         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6727
6728         /* set RB_DOORBELL_CONTROL */
6729         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6730
6731         /* active the queue */
6732         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6733
6734         return 0;
6735 }
6736 #endif
6737
6738 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6739 {
6740         struct amdgpu_device *adev = ring->adev;
6741         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6742         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6743
6744         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6745                 memset((void *)mqd, 0, sizeof(*mqd));
6746                 mutex_lock(&adev->srbm_mutex);
6747                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6748                 amdgpu_ring_init_mqd(ring);
6749
6750                 /*
6751                  * if there are 2 gfx rings, set the lower doorbell
6752                  * range of the first ring, otherwise the range of
6753                  * the second ring will override the first ring
6754                  */
6755                 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6756                         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6757
6758 #ifdef BRING_UP_DEBUG
6759                 gfx_v10_0_gfx_queue_init_register(ring);
6760 #endif
6761                 nv_grbm_select(adev, 0, 0, 0, 0);
6762                 mutex_unlock(&adev->srbm_mutex);
6763                 if (adev->gfx.me.mqd_backup[mqd_idx])
6764                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6765         } else if (amdgpu_in_reset(adev)) {
6766                 /* reset mqd with the backup copy */
6767                 if (adev->gfx.me.mqd_backup[mqd_idx])
6768                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6769                 /* reset the ring */
6770                 ring->wptr = 0;
6771                 *ring->wptr_cpu_addr = 0;
6772                 amdgpu_ring_clear_ring(ring);
6773 #ifdef BRING_UP_DEBUG
6774                 mutex_lock(&adev->srbm_mutex);
6775                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6776                 gfx_v10_0_gfx_queue_init_register(ring);
6777                 nv_grbm_select(adev, 0, 0, 0, 0);
6778                 mutex_unlock(&adev->srbm_mutex);
6779 #endif
6780         } else {
6781                 amdgpu_ring_clear_ring(ring);
6782         }
6783
6784         return 0;
6785 }
6786
6787 #ifndef BRING_UP_DEBUG
6788 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6789 {
6790         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6791         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6792         int r, i;
6793
6794         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6795                 return -EINVAL;
6796
6797         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6798                                         adev->gfx.num_gfx_rings);
6799         if (r) {
6800                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6801                 return r;
6802         }
6803
6804         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6805                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6806
6807         return amdgpu_ring_test_helper(kiq_ring);
6808 }
6809 #endif
6810
6811 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6812 {
6813         int r, i;
6814         struct amdgpu_ring *ring;
6815
6816         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6817                 ring = &adev->gfx.gfx_ring[i];
6818
6819                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6820                 if (unlikely(r != 0))
6821                         goto done;
6822
6823                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6824                 if (!r) {
6825                         r = gfx_v10_0_gfx_init_queue(ring);
6826                         amdgpu_bo_kunmap(ring->mqd_obj);
6827                         ring->mqd_ptr = NULL;
6828                 }
6829                 amdgpu_bo_unreserve(ring->mqd_obj);
6830                 if (r)
6831                         goto done;
6832         }
6833 #ifndef BRING_UP_DEBUG
6834         r = gfx_v10_0_kiq_enable_kgq(adev);
6835         if (r)
6836                 goto done;
6837 #endif
6838         r = gfx_v10_0_cp_gfx_start(adev);
6839         if (r)
6840                 goto done;
6841
6842         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6843                 ring = &adev->gfx.gfx_ring[i];
6844                 ring->sched.ready = true;
6845         }
6846 done:
6847         return r;
6848 }
6849
6850 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6851                                       struct amdgpu_mqd_prop *prop)
6852 {
6853         struct v10_compute_mqd *mqd = m;
6854         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6855         uint32_t tmp;
6856
6857         mqd->header = 0xC0310800;
6858         mqd->compute_pipelinestat_enable = 0x00000001;
6859         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6860         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6861         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6862         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6863         mqd->compute_misc_reserved = 0x00000003;
6864
6865         eop_base_addr = prop->eop_gpu_addr >> 8;
6866         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6867         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6868
6869         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6870         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6871         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6872                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6873
6874         mqd->cp_hqd_eop_control = tmp;
6875
6876         /* enable doorbell? */
6877         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6878
6879         if (prop->use_doorbell) {
6880                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6881                                     DOORBELL_OFFSET, prop->doorbell_index);
6882                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6883                                     DOORBELL_EN, 1);
6884                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6885                                     DOORBELL_SOURCE, 0);
6886                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6887                                     DOORBELL_HIT, 0);
6888         } else {
6889                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6890                                     DOORBELL_EN, 0);
6891         }
6892
6893         mqd->cp_hqd_pq_doorbell_control = tmp;
6894
6895         /* disable the queue if it's active */
6896         mqd->cp_hqd_dequeue_request = 0;
6897         mqd->cp_hqd_pq_rptr = 0;
6898         mqd->cp_hqd_pq_wptr_lo = 0;
6899         mqd->cp_hqd_pq_wptr_hi = 0;
6900
6901         /* set the pointer to the MQD */
6902         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6903         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6904
6905         /* set MQD vmid to 0 */
6906         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6907         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6908         mqd->cp_mqd_control = tmp;
6909
6910         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6911         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6912         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6913         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6914
6915         /* set up the HQD, this is similar to CP_RB0_CNTL */
6916         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6917         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6918                             (order_base_2(prop->queue_size / 4) - 1));
6919         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6920                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6921 #ifdef __BIG_ENDIAN
6922         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6923 #endif
6924         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6925         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6926         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6927         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6928         mqd->cp_hqd_pq_control = tmp;
6929
6930         /* set the wb address whether it's enabled or not */
6931         wb_gpu_addr = prop->rptr_gpu_addr;
6932         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6933         mqd->cp_hqd_pq_rptr_report_addr_hi =
6934                 upper_32_bits(wb_gpu_addr) & 0xffff;
6935
6936         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6937         wb_gpu_addr = prop->wptr_gpu_addr;
6938         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6939         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6940
6941         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6942         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6943
6944         /* set the vmid for the queue */
6945         mqd->cp_hqd_vmid = 0;
6946
6947         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6948         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6949         mqd->cp_hqd_persistent_state = tmp;
6950
6951         /* set MIN_IB_AVAIL_SIZE */
6952         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6953         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6954         mqd->cp_hqd_ib_control = tmp;
6955
6956         /* set static priority for a compute queue/ring */
6957         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6958         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6959
6960         mqd->cp_hqd_active = prop->hqd_active;
6961
6962         return 0;
6963 }
6964
6965 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6966 {
6967         struct amdgpu_device *adev = ring->adev;
6968         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6969         int j;
6970
6971         /* inactivate the queue */
6972         if (amdgpu_sriov_vf(adev))
6973                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6974
6975         /* disable wptr polling */
6976         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6977
6978         /* disable the queue if it's active */
6979         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6980                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6981                 for (j = 0; j < adev->usec_timeout; j++) {
6982                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6983                                 break;
6984                         udelay(1);
6985                 }
6986                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6987                        mqd->cp_hqd_dequeue_request);
6988                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6989                        mqd->cp_hqd_pq_rptr);
6990                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6991                        mqd->cp_hqd_pq_wptr_lo);
6992                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6993                        mqd->cp_hqd_pq_wptr_hi);
6994         }
6995
6996         /* disable doorbells */
6997         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6998
6999         /* write the EOP addr */
7000         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7001                mqd->cp_hqd_eop_base_addr_lo);
7002         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7003                mqd->cp_hqd_eop_base_addr_hi);
7004
7005         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7006         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7007                mqd->cp_hqd_eop_control);
7008
7009         /* set the pointer to the MQD */
7010         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7011                mqd->cp_mqd_base_addr_lo);
7012         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7013                mqd->cp_mqd_base_addr_hi);
7014
7015         /* set MQD vmid to 0 */
7016         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7017                mqd->cp_mqd_control);
7018
7019         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7020         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7021                mqd->cp_hqd_pq_base_lo);
7022         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7023                mqd->cp_hqd_pq_base_hi);
7024
7025         /* set up the HQD, this is similar to CP_RB0_CNTL */
7026         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7027                mqd->cp_hqd_pq_control);
7028
7029         /* set the wb address whether it's enabled or not */
7030         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7031                 mqd->cp_hqd_pq_rptr_report_addr_lo);
7032         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7033                 mqd->cp_hqd_pq_rptr_report_addr_hi);
7034
7035         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7036         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7037                mqd->cp_hqd_pq_wptr_poll_addr_lo);
7038         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7039                mqd->cp_hqd_pq_wptr_poll_addr_hi);
7040
7041         /* enable the doorbell if requested */
7042         if (ring->use_doorbell) {
7043                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7044                         (adev->doorbell_index.kiq * 2) << 2);
7045                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7046                         (adev->doorbell_index.userqueue_end * 2) << 2);
7047         }
7048
7049         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7050                mqd->cp_hqd_pq_doorbell_control);
7051
7052         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7053         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7054                mqd->cp_hqd_pq_wptr_lo);
7055         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7056                mqd->cp_hqd_pq_wptr_hi);
7057
7058         /* set the vmid for the queue */
7059         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7060
7061         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7062                mqd->cp_hqd_persistent_state);
7063
7064         /* activate the queue */
7065         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7066                mqd->cp_hqd_active);
7067
7068         if (ring->use_doorbell)
7069                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7070
7071         return 0;
7072 }
7073
7074 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7075 {
7076         struct amdgpu_device *adev = ring->adev;
7077         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7078         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7079
7080         gfx_v10_0_kiq_setting(ring);
7081
7082         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7083                 /* reset MQD to a clean status */
7084                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7085                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7086
7087                 /* reset ring buffer */
7088                 ring->wptr = 0;
7089                 amdgpu_ring_clear_ring(ring);
7090
7091                 mutex_lock(&adev->srbm_mutex);
7092                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7093                 gfx_v10_0_kiq_init_register(ring);
7094                 nv_grbm_select(adev, 0, 0, 0, 0);
7095                 mutex_unlock(&adev->srbm_mutex);
7096         } else {
7097                 memset((void *)mqd, 0, sizeof(*mqd));
7098                 mutex_lock(&adev->srbm_mutex);
7099                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7100                 amdgpu_ring_init_mqd(ring);
7101                 gfx_v10_0_kiq_init_register(ring);
7102                 nv_grbm_select(adev, 0, 0, 0, 0);
7103                 mutex_unlock(&adev->srbm_mutex);
7104
7105                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7106                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7107         }
7108
7109         return 0;
7110 }
7111
7112 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7113 {
7114         struct amdgpu_device *adev = ring->adev;
7115         struct v10_compute_mqd *mqd = ring->mqd_ptr;
7116         int mqd_idx = ring - &adev->gfx.compute_ring[0];
7117
7118         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7119                 memset((void *)mqd, 0, sizeof(*mqd));
7120                 mutex_lock(&adev->srbm_mutex);
7121                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7122                 amdgpu_ring_init_mqd(ring);
7123                 nv_grbm_select(adev, 0, 0, 0, 0);
7124                 mutex_unlock(&adev->srbm_mutex);
7125
7126                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7127                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7128         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7129                 /* reset MQD to a clean status */
7130                 if (adev->gfx.mec.mqd_backup[mqd_idx])
7131                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7132
7133                 /* reset ring buffer */
7134                 ring->wptr = 0;
7135                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7136                 amdgpu_ring_clear_ring(ring);
7137         } else {
7138                 amdgpu_ring_clear_ring(ring);
7139         }
7140
7141         return 0;
7142 }
7143
7144 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7145 {
7146         struct amdgpu_ring *ring;
7147         int r;
7148
7149         ring = &adev->gfx.kiq.ring;
7150
7151         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7152         if (unlikely(r != 0))
7153                 return r;
7154
7155         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7156         if (unlikely(r != 0))
7157                 return r;
7158
7159         gfx_v10_0_kiq_init_queue(ring);
7160         amdgpu_bo_kunmap(ring->mqd_obj);
7161         ring->mqd_ptr = NULL;
7162         amdgpu_bo_unreserve(ring->mqd_obj);
7163         ring->sched.ready = true;
7164         return 0;
7165 }
7166
7167 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7168 {
7169         struct amdgpu_ring *ring = NULL;
7170         int r = 0, i;
7171
7172         gfx_v10_0_cp_compute_enable(adev, true);
7173
7174         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7175                 ring = &adev->gfx.compute_ring[i];
7176
7177                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7178                 if (unlikely(r != 0))
7179                         goto done;
7180                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7181                 if (!r) {
7182                         r = gfx_v10_0_kcq_init_queue(ring);
7183                         amdgpu_bo_kunmap(ring->mqd_obj);
7184                         ring->mqd_ptr = NULL;
7185                 }
7186                 amdgpu_bo_unreserve(ring->mqd_obj);
7187                 if (r)
7188                         goto done;
7189         }
7190
7191         r = amdgpu_gfx_enable_kcq(adev);
7192 done:
7193         return r;
7194 }
7195
7196 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7197 {
7198         int r, i;
7199         struct amdgpu_ring *ring;
7200
7201         if (!(adev->flags & AMD_IS_APU))
7202                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7203
7204         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7205                 /* legacy firmware loading */
7206                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7207                 if (r)
7208                         return r;
7209
7210                 r = gfx_v10_0_cp_compute_load_microcode(adev);
7211                 if (r)
7212                         return r;
7213         }
7214
7215         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7216                 r = amdgpu_mes_kiq_hw_init(adev);
7217         else
7218                 r = gfx_v10_0_kiq_resume(adev);
7219         if (r)
7220                 return r;
7221
7222         r = gfx_v10_0_kcq_resume(adev);
7223         if (r)
7224                 return r;
7225
7226         if (!amdgpu_async_gfx_ring) {
7227                 r = gfx_v10_0_cp_gfx_resume(adev);
7228                 if (r)
7229                         return r;
7230         } else {
7231                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7232                 if (r)
7233                         return r;
7234         }
7235
7236         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7237                 ring = &adev->gfx.gfx_ring[i];
7238                 r = amdgpu_ring_test_helper(ring);
7239                 if (r)
7240                         return r;
7241         }
7242
7243         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7244                 ring = &adev->gfx.compute_ring[i];
7245                 r = amdgpu_ring_test_helper(ring);
7246                 if (r)
7247                         return r;
7248         }
7249
7250         return 0;
7251 }
7252
7253 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7254 {
7255         gfx_v10_0_cp_gfx_enable(adev, enable);
7256         gfx_v10_0_cp_compute_enable(adev, enable);
7257 }
7258
7259 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7260 {
7261         uint32_t data, pattern = 0xDEADBEEF;
7262
7263         /* check if mmVGT_ESGS_RING_SIZE_UMD
7264          * has been remapped to mmVGT_ESGS_RING_SIZE */
7265         switch (adev->ip_versions[GC_HWIP][0]) {
7266         case IP_VERSION(10, 3, 0):
7267         case IP_VERSION(10, 3, 2):
7268         case IP_VERSION(10, 3, 4):
7269         case IP_VERSION(10, 3, 5):
7270                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7271                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7272                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7273
7274                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7275                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7276                         return true;
7277                 } else {
7278                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7279                         return false;
7280                 }
7281                 break;
7282         case IP_VERSION(10, 3, 1):
7283         case IP_VERSION(10, 3, 3):
7284         case IP_VERSION(10, 3, 6):
7285         case IP_VERSION(10, 3, 7):
7286                 return true;
7287         default:
7288                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7289                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7290                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7291
7292                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7293                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7294                         return true;
7295                 } else {
7296                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7297                         return false;
7298                 }
7299                 break;
7300         }
7301 }
7302
7303 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7304 {
7305         uint32_t data;
7306
7307         if (amdgpu_sriov_vf(adev))
7308                 return;
7309
7310         /* initialize cam_index to 0
7311          * index will auto-inc after each data writting */
7312         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7313
7314         switch (adev->ip_versions[GC_HWIP][0]) {
7315         case IP_VERSION(10, 3, 0):
7316         case IP_VERSION(10, 3, 2):
7317         case IP_VERSION(10, 3, 1):
7318         case IP_VERSION(10, 3, 4):
7319         case IP_VERSION(10, 3, 5):
7320         case IP_VERSION(10, 3, 6):
7321         case IP_VERSION(10, 3, 3):
7322         case IP_VERSION(10, 3, 7):
7323                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7324                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7325                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7326                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7327                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7328                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7329                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7330
7331                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7332                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7333                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7334                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7335                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7336                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7337                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7338
7339                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7340                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7341                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7342                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7343                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7344                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7345                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7346
7347                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7348                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7349                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7350                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7351                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7352                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7353                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7354
7355                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7356                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7357                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7358                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7359                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7360                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7361                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7362
7363                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7364                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7365                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7366                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7367                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7368                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7369                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7370
7371                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7372                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7373                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7374                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7375                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7376                 break;
7377         default:
7378                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7379                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7380                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7381                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7382                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7383                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7384                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7385
7386                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7387                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7388                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7389                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7390                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7391                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7392                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7393
7394                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7395                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7396                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7397                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7398                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7399                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7400                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7401
7402                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7403                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7404                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7405                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7406                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7407                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7408                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7409
7410                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7411                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7412                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7413                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7414                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7415                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7416                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7417
7418                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7419                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7420                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7421                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7422                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7423                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7424                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7425
7426                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7427                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7428                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7429                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7430                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7431                 break;
7432         }
7433
7434         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7435         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7436 }
7437
7438 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7439 {
7440         uint32_t data;
7441         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7442         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7443         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7444
7445         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7446         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7447         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7448 }
7449
7450 static int gfx_v10_0_hw_init(void *handle)
7451 {
7452         int r;
7453         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7454
7455         if (!amdgpu_emu_mode)
7456                 gfx_v10_0_init_golden_registers(adev);
7457
7458         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7459                 /**
7460                  * For gfx 10, rlc firmware loading relies on smu firmware is
7461                  * loaded firstly, so in direct type, it has to load smc ucode
7462                  * here before rlc.
7463                  */
7464                 if (!(adev->flags & AMD_IS_APU)) {
7465                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
7466                         if (r)
7467                                 return r;
7468                 }
7469                 gfx_v10_0_disable_gpa_mode(adev);
7470         }
7471
7472         /* if GRBM CAM not remapped, set up the remapping */
7473         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7474                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7475
7476         gfx_v10_0_constants_init(adev);
7477
7478         r = gfx_v10_0_rlc_resume(adev);
7479         if (r)
7480                 return r;
7481
7482         /*
7483          * init golden registers and rlc resume may override some registers,
7484          * reconfig them here
7485          */
7486         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7487             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7488             adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7489                 gfx_v10_0_tcp_harvest(adev);
7490
7491         r = gfx_v10_0_cp_resume(adev);
7492         if (r)
7493                 return r;
7494
7495         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7496                 gfx_v10_3_program_pbb_mode(adev);
7497
7498         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7499                 gfx_v10_3_set_power_brake_sequence(adev);
7500
7501         return r;
7502 }
7503
7504 #ifndef BRING_UP_DEBUG
7505 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7506 {
7507         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7508         struct amdgpu_ring *kiq_ring = &kiq->ring;
7509         int i;
7510
7511         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7512                 return -EINVAL;
7513
7514         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7515                                         adev->gfx.num_gfx_rings))
7516                 return -ENOMEM;
7517
7518         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7519                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7520                                            PREEMPT_QUEUES, 0, 0);
7521
7522         return amdgpu_ring_test_helper(kiq_ring);
7523 }
7524 #endif
7525
7526 static int gfx_v10_0_hw_fini(void *handle)
7527 {
7528         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7529         int r;
7530         uint32_t tmp;
7531
7532         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7533         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7534
7535         if (!adev->no_hw_access) {
7536 #ifndef BRING_UP_DEBUG
7537                 if (amdgpu_async_gfx_ring) {
7538                         r = gfx_v10_0_kiq_disable_kgq(adev);
7539                         if (r)
7540                                 DRM_ERROR("KGQ disable failed\n");
7541                 }
7542 #endif
7543                 if (amdgpu_gfx_disable_kcq(adev))
7544                         DRM_ERROR("KCQ disable failed\n");
7545         }
7546
7547         if (amdgpu_sriov_vf(adev)) {
7548                 gfx_v10_0_cp_gfx_enable(adev, false);
7549                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7550                 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7551                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7552                         tmp &= 0xffffff00;
7553                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7554                 } else {
7555                         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7556                         tmp &= 0xffffff00;
7557                         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7558                 }
7559
7560                 return 0;
7561         }
7562         gfx_v10_0_cp_enable(adev, false);
7563         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7564
7565         return 0;
7566 }
7567
7568 static int gfx_v10_0_suspend(void *handle)
7569 {
7570         return gfx_v10_0_hw_fini(handle);
7571 }
7572
7573 static int gfx_v10_0_resume(void *handle)
7574 {
7575         return gfx_v10_0_hw_init(handle);
7576 }
7577
7578 static bool gfx_v10_0_is_idle(void *handle)
7579 {
7580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7581
7582         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7583                                 GRBM_STATUS, GUI_ACTIVE))
7584                 return false;
7585         else
7586                 return true;
7587 }
7588
7589 static int gfx_v10_0_wait_for_idle(void *handle)
7590 {
7591         unsigned i;
7592         u32 tmp;
7593         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7594
7595         for (i = 0; i < adev->usec_timeout; i++) {
7596                 /* read MC_STATUS */
7597                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7598                         GRBM_STATUS__GUI_ACTIVE_MASK;
7599
7600                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7601                         return 0;
7602                 udelay(1);
7603         }
7604         return -ETIMEDOUT;
7605 }
7606
7607 static int gfx_v10_0_soft_reset(void *handle)
7608 {
7609         u32 grbm_soft_reset = 0;
7610         u32 tmp;
7611         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7612
7613         /* GRBM_STATUS */
7614         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7615         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7616                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7617                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7618                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7619                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7620                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7621                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7622                                                 1);
7623                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7624                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7625                                                 1);
7626         }
7627
7628         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7629                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7630                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7631                                                 1);
7632         }
7633
7634         /* GRBM_STATUS2 */
7635         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7636         switch (adev->ip_versions[GC_HWIP][0]) {
7637         case IP_VERSION(10, 3, 0):
7638         case IP_VERSION(10, 3, 2):
7639         case IP_VERSION(10, 3, 1):
7640         case IP_VERSION(10, 3, 4):
7641         case IP_VERSION(10, 3, 5):
7642         case IP_VERSION(10, 3, 6):
7643         case IP_VERSION(10, 3, 3):
7644                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7645                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7646                                                         GRBM_SOFT_RESET,
7647                                                         SOFT_RESET_RLC,
7648                                                         1);
7649                 break;
7650         default:
7651                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7652                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7653                                                         GRBM_SOFT_RESET,
7654                                                         SOFT_RESET_RLC,
7655                                                         1);
7656                 break;
7657         }
7658
7659         if (grbm_soft_reset) {
7660                 /* stop the rlc */
7661                 gfx_v10_0_rlc_stop(adev);
7662
7663                 /* Disable GFX parsing/prefetching */
7664                 gfx_v10_0_cp_gfx_enable(adev, false);
7665
7666                 /* Disable MEC parsing/prefetching */
7667                 gfx_v10_0_cp_compute_enable(adev, false);
7668
7669                 if (grbm_soft_reset) {
7670                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7671                         tmp |= grbm_soft_reset;
7672                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7673                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7674                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7675
7676                         udelay(50);
7677
7678                         tmp &= ~grbm_soft_reset;
7679                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7680                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7681                 }
7682
7683                 /* Wait a little for things to settle down */
7684                 udelay(50);
7685         }
7686         return 0;
7687 }
7688
7689 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7690 {
7691         uint64_t clock, clock_lo, clock_hi, hi_check;
7692
7693         switch (adev->ip_versions[GC_HWIP][0]) {
7694         case IP_VERSION(10, 3, 1):
7695         case IP_VERSION(10, 3, 3):
7696         case IP_VERSION(10, 3, 7):
7697                 preempt_disable();
7698                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7699                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7700                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7701                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7702                  * roughly every 42 seconds.
7703                  */
7704                 if (hi_check != clock_hi) {
7705                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7706                         clock_hi = hi_check;
7707                 }
7708                 preempt_enable();
7709                 clock = clock_lo | (clock_hi << 32ULL);
7710                 break;
7711         case IP_VERSION(10, 3, 6):
7712                 preempt_disable();
7713                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7714                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7715                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7716                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7717                  * roughly every 42 seconds.
7718                  */
7719                 if (hi_check != clock_hi) {
7720                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7721                         clock_hi = hi_check;
7722                 }
7723                 preempt_enable();
7724                 clock = clock_lo | (clock_hi << 32ULL);
7725                 break;
7726         default:
7727                 preempt_disable();
7728                 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7729                 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7730                 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7731                 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7732                  * roughly every 42 seconds.
7733                  */
7734                 if (hi_check != clock_hi) {
7735                         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7736                         clock_hi = hi_check;
7737                 }
7738                 preempt_enable();
7739                 clock = clock_lo | (clock_hi << 32ULL);
7740                 break;
7741         }
7742         return clock;
7743 }
7744
7745 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7746                                            uint32_t vmid,
7747                                            uint32_t gds_base, uint32_t gds_size,
7748                                            uint32_t gws_base, uint32_t gws_size,
7749                                            uint32_t oa_base, uint32_t oa_size)
7750 {
7751         struct amdgpu_device *adev = ring->adev;
7752
7753         /* GDS Base */
7754         gfx_v10_0_write_data_to_reg(ring, 0, false,
7755                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7756                                     gds_base);
7757
7758         /* GDS Size */
7759         gfx_v10_0_write_data_to_reg(ring, 0, false,
7760                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7761                                     gds_size);
7762
7763         /* GWS */
7764         gfx_v10_0_write_data_to_reg(ring, 0, false,
7765                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7766                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7767
7768         /* OA */
7769         gfx_v10_0_write_data_to_reg(ring, 0, false,
7770                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7771                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7772 }
7773
7774 static int gfx_v10_0_early_init(void *handle)
7775 {
7776         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7777
7778         switch (adev->ip_versions[GC_HWIP][0]) {
7779         case IP_VERSION(10, 1, 10):
7780         case IP_VERSION(10, 1, 1):
7781         case IP_VERSION(10, 1, 2):
7782         case IP_VERSION(10, 1, 3):
7783         case IP_VERSION(10, 1, 4):
7784                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7785                 break;
7786         case IP_VERSION(10, 3, 0):
7787         case IP_VERSION(10, 3, 2):
7788         case IP_VERSION(10, 3, 1):
7789         case IP_VERSION(10, 3, 4):
7790         case IP_VERSION(10, 3, 5):
7791         case IP_VERSION(10, 3, 6):
7792         case IP_VERSION(10, 3, 3):
7793         case IP_VERSION(10, 3, 7):
7794                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7795                 break;
7796         default:
7797                 break;
7798         }
7799
7800         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7801                                           AMDGPU_MAX_COMPUTE_RINGS);
7802
7803         gfx_v10_0_set_kiq_pm4_funcs(adev);
7804         gfx_v10_0_set_ring_funcs(adev);
7805         gfx_v10_0_set_irq_funcs(adev);
7806         gfx_v10_0_set_gds_init(adev);
7807         gfx_v10_0_set_rlc_funcs(adev);
7808         gfx_v10_0_set_mqd_funcs(adev);
7809
7810         /* init rlcg reg access ctrl */
7811         gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7812
7813         return 0;
7814 }
7815
7816 static int gfx_v10_0_late_init(void *handle)
7817 {
7818         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7819         int r;
7820
7821         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7822         if (r)
7823                 return r;
7824
7825         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7826         if (r)
7827                 return r;
7828
7829         return 0;
7830 }
7831
7832 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7833 {
7834         uint32_t rlc_cntl;
7835
7836         /* if RLC is not enabled, do nothing */
7837         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7838         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7839 }
7840
7841 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7842 {
7843         uint32_t data;
7844         unsigned i;
7845
7846         data = RLC_SAFE_MODE__CMD_MASK;
7847         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7848
7849         switch (adev->ip_versions[GC_HWIP][0]) {
7850         case IP_VERSION(10, 3, 0):
7851         case IP_VERSION(10, 3, 2):
7852         case IP_VERSION(10, 3, 1):
7853         case IP_VERSION(10, 3, 4):
7854         case IP_VERSION(10, 3, 5):
7855         case IP_VERSION(10, 3, 6):
7856         case IP_VERSION(10, 3, 3):
7857         case IP_VERSION(10, 3, 7):
7858                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7859
7860                 /* wait for RLC_SAFE_MODE */
7861                 for (i = 0; i < adev->usec_timeout; i++) {
7862                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7863                                            RLC_SAFE_MODE, CMD))
7864                                 break;
7865                         udelay(1);
7866                 }
7867                 break;
7868         default:
7869                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7870
7871                 /* wait for RLC_SAFE_MODE */
7872                 for (i = 0; i < adev->usec_timeout; i++) {
7873                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7874                                            RLC_SAFE_MODE, CMD))
7875                                 break;
7876                         udelay(1);
7877                 }
7878                 break;
7879         }
7880 }
7881
7882 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7883 {
7884         uint32_t data;
7885
7886         data = RLC_SAFE_MODE__CMD_MASK;
7887         switch (adev->ip_versions[GC_HWIP][0]) {
7888         case IP_VERSION(10, 3, 0):
7889         case IP_VERSION(10, 3, 2):
7890         case IP_VERSION(10, 3, 1):
7891         case IP_VERSION(10, 3, 4):
7892         case IP_VERSION(10, 3, 5):
7893         case IP_VERSION(10, 3, 6):
7894         case IP_VERSION(10, 3, 3):
7895         case IP_VERSION(10, 3, 7):
7896                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7897                 break;
7898         default:
7899                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7900                 break;
7901         }
7902 }
7903
7904 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7905                                                       bool enable)
7906 {
7907         uint32_t data, def;
7908
7909         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7910                 return;
7911
7912         /* It is disabled by HW by default */
7913         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7914                 /* 0 - Disable some blocks' MGCG */
7915                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7916                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7917                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7918                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7919
7920                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7921                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7922                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7923                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7924                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7925                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7926                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7927                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7928
7929                 if (def != data)
7930                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7931
7932                 /* MGLS is a global flag to control all MGLS in GFX */
7933                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7934                         /* 2 - RLC memory Light sleep */
7935                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7936                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7937                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7938                                 if (def != data)
7939                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7940                         }
7941                         /* 3 - CP memory Light sleep */
7942                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7943                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7944                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7945                                 if (def != data)
7946                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7947                         }
7948                 }
7949         } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7950                 /* 1 - MGCG_OVERRIDE */
7951                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7952                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7953                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7954                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7955                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7956                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7957                          RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7958                 if (def != data)
7959                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7960
7961                 /* 2 - disable MGLS in CP */
7962                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7963                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7964                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7965                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7966                 }
7967
7968                 /* 3 - disable MGLS in RLC */
7969                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7970                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7971                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7972                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7973                 }
7974
7975         }
7976 }
7977
7978 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7979                                            bool enable)
7980 {
7981         uint32_t data, def;
7982
7983         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7984                 return;
7985
7986         /* Enable 3D CGCG/CGLS */
7987         if (enable) {
7988                 /* write cmd to clear cgcg/cgls ov */
7989                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7990
7991                 /* unset CGCG override */
7992                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7993                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7994
7995                 /* update CGCG and CGLS override bits */
7996                 if (def != data)
7997                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7998
7999                 /* enable 3Dcgcg FSM(0x0000363f) */
8000                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8001                 data = 0;
8002
8003                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8004                         data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8005                                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8006
8007                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8008                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8009                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8010
8011                 if (def != data)
8012                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8013
8014                 /* set IDLE_POLL_COUNT(0x00900100) */
8015                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8016                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8017                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8018                 if (def != data)
8019                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8020         } else {
8021                 /* Disable CGCG/CGLS */
8022                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8023
8024                 /* disable cgcg, cgls should be disabled */
8025                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8026                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8027
8028                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8029                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8030
8031                 /* disable cgcg and cgls in FSM */
8032                 if (def != data)
8033                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8034         }
8035 }
8036
8037 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8038                                                       bool enable)
8039 {
8040         uint32_t def, data;
8041
8042         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8043                 return;
8044
8045         if (enable) {
8046                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8047
8048                 /* unset CGCG override */
8049                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8050                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8051
8052                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8053                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8054
8055                 /* update CGCG and CGLS override bits */
8056                 if (def != data)
8057                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8058
8059                 /* enable cgcg FSM(0x0000363F) */
8060                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8061                 data = 0;
8062
8063                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8064                         data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8065                                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8066
8067                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8068                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8069                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8070
8071                 if (def != data)
8072                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8073
8074                 /* set IDLE_POLL_COUNT(0x00900100) */
8075                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8076                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8077                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8078                 if (def != data)
8079                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8080         } else {
8081                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8082
8083                 /* reset CGCG/CGLS bits */
8084                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8085                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8086
8087                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8088                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8089
8090                 /* disable cgcg and cgls in FSM */
8091                 if (def != data)
8092                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8093         }
8094 }
8095
8096 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8097                                                       bool enable)
8098 {
8099         uint32_t def, data;
8100
8101         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8102                 return;
8103
8104         if (enable) {
8105                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8106                 /* unset FGCG override */
8107                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8108                 /* update FGCG override bits */
8109                 if (def != data)
8110                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8111
8112                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8113                 /* unset RLC SRAM CLK GATER override */
8114                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8115                 /* update RLC SRAM CLK GATER override bits */
8116                 if (def != data)
8117                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8118         } else {
8119                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8120                 /* reset FGCG bits */
8121                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8122                 /* disable FGCG*/
8123                 if (def != data)
8124                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8125
8126                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8127                 /* reset RLC SRAM CLK GATER bits */
8128                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8129                 /* disable RLC SRAM CLK*/
8130                 if (def != data)
8131                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8132         }
8133 }
8134
8135 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8136 {
8137         uint32_t reg_data = 0;
8138         uint32_t reg_idx = 0;
8139         uint32_t i;
8140
8141         const uint32_t tcp_ctrl_regs[] = {
8142                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8143                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8144                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8145                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8146                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8147                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8148                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8149                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8150                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8151                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8152                 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8153                 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8154                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8155                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8156                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8157                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8158                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8159                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8160                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8161                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8162                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8163                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8164                 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8165                 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8166         };
8167
8168         const uint32_t tcp_ctrl_regs_nv12[] = {
8169                 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8170                 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8171                 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8172                 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8173                 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8174                 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8175                 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8176                 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8177                 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8178                 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8179                 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8180                 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8181                 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8182                 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8183                 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8184                 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8185                 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8186                 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8187                 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8188                 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8189         };
8190
8191         const uint32_t sm_ctlr_regs[] = {
8192                 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8193                 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8194                 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8195                 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8196         };
8197
8198         if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8199                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8200                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8201                                   tcp_ctrl_regs_nv12[i];
8202                         reg_data = RREG32(reg_idx);
8203                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8204                         WREG32(reg_idx, reg_data);
8205                 }
8206         } else {
8207                 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8208                         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8209                                   tcp_ctrl_regs[i];
8210                         reg_data = RREG32(reg_idx);
8211                         reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8212                         WREG32(reg_idx, reg_data);
8213                 }
8214         }
8215
8216         for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8217                 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8218                           sm_ctlr_regs[i];
8219                 reg_data = RREG32(reg_idx);
8220                 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8221                 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8222                 WREG32(reg_idx, reg_data);
8223         }
8224 }
8225
8226 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8227                                             bool enable)
8228 {
8229         amdgpu_gfx_rlc_enter_safe_mode(adev);
8230
8231         if (enable) {
8232                 /* enable FGCG firstly*/
8233                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8234                 /* CGCG/CGLS should be enabled after MGCG/MGLS
8235                  * ===  MGCG + MGLS ===
8236                  */
8237                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8238                 /* ===  CGCG /CGLS for GFX 3D Only === */
8239                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8240                 /* ===  CGCG + CGLS === */
8241                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8242
8243                 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8244                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8245                     (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8246                         gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8247         } else {
8248                 /* CGCG/CGLS should be disabled before MGCG/MGLS
8249                  * ===  CGCG + CGLS ===
8250                  */
8251                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8252                 /* ===  CGCG /CGLS for GFX 3D Only === */
8253                 gfx_v10_0_update_3d_clock_gating(adev, enable);
8254                 /* ===  MGCG + MGLS === */
8255                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8256                 /* disable fgcg at last*/
8257                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8258         }
8259
8260         if (adev->cg_flags &
8261             (AMD_CG_SUPPORT_GFX_MGCG |
8262              AMD_CG_SUPPORT_GFX_CGLS |
8263              AMD_CG_SUPPORT_GFX_CGCG |
8264              AMD_CG_SUPPORT_GFX_3D_CGCG |
8265              AMD_CG_SUPPORT_GFX_3D_CGLS))
8266                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8267
8268         amdgpu_gfx_rlc_exit_safe_mode(adev);
8269
8270         return 0;
8271 }
8272
8273 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8274 {
8275         u32 reg, data;
8276
8277         amdgpu_gfx_off_ctrl(adev, false);
8278
8279         /* not for *_SOC15 */
8280         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8281         if (amdgpu_sriov_is_pp_one_vf(adev))
8282                 data = RREG32_NO_KIQ(reg);
8283         else
8284                 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8285
8286         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8287         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8288
8289         if (amdgpu_sriov_is_pp_one_vf(adev))
8290                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8291         else
8292                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8293
8294         amdgpu_gfx_off_ctrl(adev, true);
8295 }
8296
8297 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8298                                         uint32_t offset,
8299                                         struct soc15_reg_rlcg *entries, int arr_size)
8300 {
8301         int i;
8302         uint32_t reg;
8303
8304         if (!entries)
8305                 return false;
8306
8307         for (i = 0; i < arr_size; i++) {
8308                 const struct soc15_reg_rlcg *entry;
8309
8310                 entry = &entries[i];
8311                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8312                 if (offset == reg)
8313                         return true;
8314         }
8315
8316         return false;
8317 }
8318
8319 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8320 {
8321         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8322 }
8323
8324 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8325 {
8326         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8327
8328         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8329                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8330         else
8331                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8332
8333         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8334
8335         /*
8336          * CGPG enablement required and the register to program the hysteresis value
8337          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8338          * in refclk count. Note that RLC FW is modified to take 16 bits from
8339          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8340          *
8341          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8342          * of CGPG enablement starting point.
8343          * Power/performance team will optimize it and might give a new value later.
8344          */
8345         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8346                 switch (adev->ip_versions[GC_HWIP][0]) {
8347                 case IP_VERSION(10, 3, 1):
8348                 case IP_VERSION(10, 3, 3):
8349                 case IP_VERSION(10, 3, 6):
8350                 case IP_VERSION(10, 3, 7):
8351                         data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8352                         WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8353                         break;
8354                 default:
8355                         break;
8356                 }
8357         }
8358 }
8359
8360 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8361 {
8362         amdgpu_gfx_rlc_enter_safe_mode(adev);
8363
8364         gfx_v10_cntl_power_gating(adev, enable);
8365
8366         amdgpu_gfx_rlc_exit_safe_mode(adev);
8367 }
8368
8369 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8370         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8371         .set_safe_mode = gfx_v10_0_set_safe_mode,
8372         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8373         .init = gfx_v10_0_rlc_init,
8374         .get_csb_size = gfx_v10_0_get_csb_size,
8375         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8376         .resume = gfx_v10_0_rlc_resume,
8377         .stop = gfx_v10_0_rlc_stop,
8378         .reset = gfx_v10_0_rlc_reset,
8379         .start = gfx_v10_0_rlc_start,
8380         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8381 };
8382
8383 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8384         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8385         .set_safe_mode = gfx_v10_0_set_safe_mode,
8386         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8387         .init = gfx_v10_0_rlc_init,
8388         .get_csb_size = gfx_v10_0_get_csb_size,
8389         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8390         .resume = gfx_v10_0_rlc_resume,
8391         .stop = gfx_v10_0_rlc_stop,
8392         .reset = gfx_v10_0_rlc_reset,
8393         .start = gfx_v10_0_rlc_start,
8394         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8395         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8396 };
8397
8398 static int gfx_v10_0_set_powergating_state(void *handle,
8399                                           enum amd_powergating_state state)
8400 {
8401         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8402         bool enable = (state == AMD_PG_STATE_GATE);
8403
8404         if (amdgpu_sriov_vf(adev))
8405                 return 0;
8406
8407         switch (adev->ip_versions[GC_HWIP][0]) {
8408         case IP_VERSION(10, 1, 10):
8409         case IP_VERSION(10, 1, 1):
8410         case IP_VERSION(10, 1, 2):
8411         case IP_VERSION(10, 3, 0):
8412         case IP_VERSION(10, 3, 2):
8413         case IP_VERSION(10, 3, 4):
8414         case IP_VERSION(10, 3, 5):
8415                 amdgpu_gfx_off_ctrl(adev, enable);
8416                 break;
8417         case IP_VERSION(10, 3, 1):
8418         case IP_VERSION(10, 3, 3):
8419         case IP_VERSION(10, 3, 6):
8420         case IP_VERSION(10, 3, 7):
8421                 gfx_v10_cntl_pg(adev, enable);
8422                 amdgpu_gfx_off_ctrl(adev, enable);
8423                 break;
8424         default:
8425                 break;
8426         }
8427         return 0;
8428 }
8429
8430 static int gfx_v10_0_set_clockgating_state(void *handle,
8431                                           enum amd_clockgating_state state)
8432 {
8433         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8434
8435         if (amdgpu_sriov_vf(adev))
8436                 return 0;
8437
8438         switch (adev->ip_versions[GC_HWIP][0]) {
8439         case IP_VERSION(10, 1, 10):
8440         case IP_VERSION(10, 1, 1):
8441         case IP_VERSION(10, 1, 2):
8442         case IP_VERSION(10, 3, 0):
8443         case IP_VERSION(10, 3, 2):
8444         case IP_VERSION(10, 3, 1):
8445         case IP_VERSION(10, 3, 4):
8446         case IP_VERSION(10, 3, 5):
8447         case IP_VERSION(10, 3, 6):
8448         case IP_VERSION(10, 3, 3):
8449         case IP_VERSION(10, 3, 7):
8450                 gfx_v10_0_update_gfx_clock_gating(adev,
8451                                                  state == AMD_CG_STATE_GATE);
8452                 break;
8453         default:
8454                 break;
8455         }
8456         return 0;
8457 }
8458
8459 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8460 {
8461         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8462         int data;
8463
8464         /* AMD_CG_SUPPORT_GFX_FGCG */
8465         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8466         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8467                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8468
8469         /* AMD_CG_SUPPORT_GFX_MGCG */
8470         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8471         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8472                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8473
8474         /* AMD_CG_SUPPORT_GFX_CGCG */
8475         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8476         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8477                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8478
8479         /* AMD_CG_SUPPORT_GFX_CGLS */
8480         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8481                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8482
8483         /* AMD_CG_SUPPORT_GFX_RLC_LS */
8484         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8485         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8486                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8487
8488         /* AMD_CG_SUPPORT_GFX_CP_LS */
8489         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8490         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8491                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8492
8493         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8494         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8495         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8496                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8497
8498         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8499         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8500                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8501 }
8502
8503 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8504 {
8505         /* gfx10 is 32bit rptr*/
8506         return *(uint32_t *)ring->rptr_cpu_addr;
8507 }
8508
8509 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8510 {
8511         struct amdgpu_device *adev = ring->adev;
8512         u64 wptr;
8513
8514         /* XXX check if swapping is necessary on BE */
8515         if (ring->use_doorbell) {
8516                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8517         } else {
8518                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8519                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8520         }
8521
8522         return wptr;
8523 }
8524
8525 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8526 {
8527         struct amdgpu_device *adev = ring->adev;
8528
8529         if (ring->use_doorbell) {
8530                 /* XXX check if swapping is necessary on BE */
8531                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
8532                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8533         } else {
8534                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8535                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8536         }
8537 }
8538
8539 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8540 {
8541         /* gfx10 hardware is 32bit rptr */
8542         return *(uint32_t *)ring->rptr_cpu_addr;
8543 }
8544
8545 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8546 {
8547         u64 wptr;
8548
8549         /* XXX check if swapping is necessary on BE */
8550         if (ring->use_doorbell)
8551                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8552         else
8553                 BUG();
8554         return wptr;
8555 }
8556
8557 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8558 {
8559         struct amdgpu_device *adev = ring->adev;
8560
8561         /* XXX check if swapping is necessary on BE */
8562         if (ring->use_doorbell) {
8563                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
8564                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8565         } else {
8566                 BUG(); /* only DOORBELL method supported on gfx10 now */
8567         }
8568 }
8569
8570 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8571 {
8572         struct amdgpu_device *adev = ring->adev;
8573         u32 ref_and_mask, reg_mem_engine;
8574         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8575
8576         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8577                 switch (ring->me) {
8578                 case 1:
8579                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8580                         break;
8581                 case 2:
8582                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8583                         break;
8584                 default:
8585                         return;
8586                 }
8587                 reg_mem_engine = 0;
8588         } else {
8589                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8590                 reg_mem_engine = 1; /* pfp */
8591         }
8592
8593         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8594                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8595                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8596                                ref_and_mask, ref_and_mask, 0x20);
8597 }
8598
8599 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8600                                        struct amdgpu_job *job,
8601                                        struct amdgpu_ib *ib,
8602                                        uint32_t flags)
8603 {
8604         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8605         u32 header, control = 0;
8606
8607         if (ib->flags & AMDGPU_IB_FLAG_CE)
8608                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8609         else
8610                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8611
8612         control |= ib->length_dw | (vmid << 24);
8613
8614         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8615                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8616
8617                 if (flags & AMDGPU_IB_PREEMPTED)
8618                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8619
8620                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8621                         gfx_v10_0_ring_emit_de_meta(ring,
8622                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8623         }
8624
8625         if (ring->is_mes_queue)
8626                 /* inherit vmid from mqd */
8627                 control |= 0x400000;
8628
8629         amdgpu_ring_write(ring, header);
8630         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8631         amdgpu_ring_write(ring,
8632 #ifdef __BIG_ENDIAN
8633                 (2 << 0) |
8634 #endif
8635                 lower_32_bits(ib->gpu_addr));
8636         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8637         amdgpu_ring_write(ring, control);
8638 }
8639
8640 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8641                                            struct amdgpu_job *job,
8642                                            struct amdgpu_ib *ib,
8643                                            uint32_t flags)
8644 {
8645         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8646         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8647
8648         if (ring->is_mes_queue)
8649                 /* inherit vmid from mqd */
8650                 control |= 0x40000000;
8651
8652         /* Currently, there is a high possibility to get wave ID mismatch
8653          * between ME and GDS, leading to a hw deadlock, because ME generates
8654          * different wave IDs than the GDS expects. This situation happens
8655          * randomly when at least 5 compute pipes use GDS ordered append.
8656          * The wave IDs generated by ME are also wrong after suspend/resume.
8657          * Those are probably bugs somewhere else in the kernel driver.
8658          *
8659          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8660          * GDS to 0 for this ring (me/pipe).
8661          */
8662         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8663                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8664                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8665                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8666         }
8667
8668         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8669         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8670         amdgpu_ring_write(ring,
8671 #ifdef __BIG_ENDIAN
8672                                 (2 << 0) |
8673 #endif
8674                                 lower_32_bits(ib->gpu_addr));
8675         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8676         amdgpu_ring_write(ring, control);
8677 }
8678
8679 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8680                                      u64 seq, unsigned flags)
8681 {
8682         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8683         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8684
8685         /* RELEASE_MEM - flush caches, send int */
8686         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8687         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8688                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8689                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8690                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8691                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8692                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8693                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8694         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8695                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8696
8697         /*
8698          * the address should be Qword aligned if 64bit write, Dword
8699          * aligned if only send 32bit data low (discard data high)
8700          */
8701         if (write64bit)
8702                 BUG_ON(addr & 0x7);
8703         else
8704                 BUG_ON(addr & 0x3);
8705         amdgpu_ring_write(ring, lower_32_bits(addr));
8706         amdgpu_ring_write(ring, upper_32_bits(addr));
8707         amdgpu_ring_write(ring, lower_32_bits(seq));
8708         amdgpu_ring_write(ring, upper_32_bits(seq));
8709         amdgpu_ring_write(ring, ring->is_mes_queue ?
8710                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8711 }
8712
8713 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8714 {
8715         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8716         uint32_t seq = ring->fence_drv.sync_seq;
8717         uint64_t addr = ring->fence_drv.gpu_addr;
8718
8719         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8720                                upper_32_bits(addr), seq, 0xffffffff, 4);
8721 }
8722
8723 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8724                                    uint16_t pasid, uint32_t flush_type,
8725                                    bool all_hub, uint8_t dst_sel)
8726 {
8727         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8728         amdgpu_ring_write(ring,
8729                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8730                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8731                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8732                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8733 }
8734
8735 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8736                                          unsigned vmid, uint64_t pd_addr)
8737 {
8738         if (ring->is_mes_queue)
8739                 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8740         else
8741                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8742
8743         /* compute doesn't have PFP */
8744         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8745                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8746                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8747                 amdgpu_ring_write(ring, 0x0);
8748         }
8749 }
8750
8751 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8752                                           u64 seq, unsigned int flags)
8753 {
8754         struct amdgpu_device *adev = ring->adev;
8755
8756         /* we only allocate 32bit for each seq wb address */
8757         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8758
8759         /* write fence seq to the "addr" */
8760         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8761         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8762                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8763         amdgpu_ring_write(ring, lower_32_bits(addr));
8764         amdgpu_ring_write(ring, upper_32_bits(addr));
8765         amdgpu_ring_write(ring, lower_32_bits(seq));
8766
8767         if (flags & AMDGPU_FENCE_FLAG_INT) {
8768                 /* set register to trigger INT */
8769                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8770                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8771                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8772                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8773                 amdgpu_ring_write(ring, 0);
8774                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8775         }
8776 }
8777
8778 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8779 {
8780         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8781         amdgpu_ring_write(ring, 0);
8782 }
8783
8784 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8785                                          uint32_t flags)
8786 {
8787         uint32_t dw2 = 0;
8788
8789         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8790                 gfx_v10_0_ring_emit_ce_meta(ring,
8791                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8792
8793         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8794         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8795                 /* set load_global_config & load_global_uconfig */
8796                 dw2 |= 0x8001;
8797                 /* set load_cs_sh_regs */
8798                 dw2 |= 0x01000000;
8799                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8800                 dw2 |= 0x10002;
8801
8802                 /* set load_ce_ram if preamble presented */
8803                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8804                         dw2 |= 0x10000000;
8805         } else {
8806                 /* still load_ce_ram if this is the first time preamble presented
8807                  * although there is no context switch happens.
8808                  */
8809                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8810                         dw2 |= 0x10000000;
8811         }
8812
8813         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8814         amdgpu_ring_write(ring, dw2);
8815         amdgpu_ring_write(ring, 0);
8816 }
8817
8818 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8819 {
8820         unsigned ret;
8821
8822         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8823         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8824         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8825         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8826         ret = ring->wptr & ring->buf_mask;
8827         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8828
8829         return ret;
8830 }
8831
8832 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8833 {
8834         unsigned cur;
8835         BUG_ON(offset > ring->buf_mask);
8836         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8837
8838         cur = (ring->wptr - 1) & ring->buf_mask;
8839         if (likely(cur > offset))
8840                 ring->ring[offset] = cur - offset;
8841         else
8842                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8843 }
8844
8845 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8846 {
8847         int i, r = 0;
8848         struct amdgpu_device *adev = ring->adev;
8849         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8850         struct amdgpu_ring *kiq_ring = &kiq->ring;
8851         unsigned long flags;
8852
8853         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8854                 return -EINVAL;
8855
8856         spin_lock_irqsave(&kiq->ring_lock, flags);
8857
8858         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8859                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8860                 return -ENOMEM;
8861         }
8862
8863         /* assert preemption condition */
8864         amdgpu_ring_set_preempt_cond_exec(ring, false);
8865
8866         /* assert IB preemption, emit the trailing fence */
8867         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8868                                    ring->trail_fence_gpu_addr,
8869                                    ++ring->trail_seq);
8870         amdgpu_ring_commit(kiq_ring);
8871
8872         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8873
8874         /* poll the trailing fence */
8875         for (i = 0; i < adev->usec_timeout; i++) {
8876                 if (ring->trail_seq ==
8877                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8878                         break;
8879                 udelay(1);
8880         }
8881
8882         if (i >= adev->usec_timeout) {
8883                 r = -EINVAL;
8884                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8885         }
8886
8887         /* deassert preemption condition */
8888         amdgpu_ring_set_preempt_cond_exec(ring, true);
8889         return r;
8890 }
8891
8892 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8893 {
8894         struct amdgpu_device *adev = ring->adev;
8895         struct v10_ce_ib_state ce_payload = {0};
8896         uint64_t offset, ce_payload_gpu_addr;
8897         void *ce_payload_cpu_addr;
8898         int cnt;
8899
8900         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8901
8902         if (ring->is_mes_queue) {
8903                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8904                                   gfx[0].gfx_meta_data) +
8905                         offsetof(struct v10_gfx_meta_data, ce_payload);
8906                 ce_payload_gpu_addr =
8907                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8908                 ce_payload_cpu_addr =
8909                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8910         } else {
8911                 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8912                 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8913                 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8914         }
8915
8916         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8917         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8918                                  WRITE_DATA_DST_SEL(8) |
8919                                  WR_CONFIRM) |
8920                                  WRITE_DATA_CACHE_POLICY(0));
8921         amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8922         amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8923
8924         if (resume)
8925                 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8926                                            sizeof(ce_payload) >> 2);
8927         else
8928                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8929                                            sizeof(ce_payload) >> 2);
8930 }
8931
8932 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8933 {
8934         struct amdgpu_device *adev = ring->adev;
8935         struct v10_de_ib_state de_payload = {0};
8936         uint64_t offset, gds_addr, de_payload_gpu_addr;
8937         void *de_payload_cpu_addr;
8938         int cnt;
8939
8940         if (ring->is_mes_queue) {
8941                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8942                                   gfx[0].gfx_meta_data) +
8943                         offsetof(struct v10_gfx_meta_data, de_payload);
8944                 de_payload_gpu_addr =
8945                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8946                 de_payload_cpu_addr =
8947                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8948
8949                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8950                                   gfx[0].gds_backup) +
8951                         offsetof(struct v10_gfx_meta_data, de_payload);
8952                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8953         } else {
8954                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8955                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8956                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8957
8958                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8959                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
8960                                  PAGE_SIZE);
8961         }
8962
8963         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8964         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8965
8966         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8967         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8968         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8969                                  WRITE_DATA_DST_SEL(8) |
8970                                  WR_CONFIRM) |
8971                                  WRITE_DATA_CACHE_POLICY(0));
8972         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8973         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8974
8975         if (resume)
8976                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8977                                            sizeof(de_payload) >> 2);
8978         else
8979                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8980                                            sizeof(de_payload) >> 2);
8981 }
8982
8983 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8984                                     bool secure)
8985 {
8986         uint32_t v = secure ? FRAME_TMZ : 0;
8987
8988         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8989         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8990 }
8991
8992 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8993                                      uint32_t reg_val_offs)
8994 {
8995         struct amdgpu_device *adev = ring->adev;
8996
8997         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8998         amdgpu_ring_write(ring, 0 |     /* src: register*/
8999                                 (5 << 8) |      /* dst: memory */
9000                                 (1 << 20));     /* write confirm */
9001         amdgpu_ring_write(ring, reg);
9002         amdgpu_ring_write(ring, 0);
9003         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
9004                                 reg_val_offs * 4));
9005         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
9006                                 reg_val_offs * 4));
9007 }
9008
9009 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9010                                    uint32_t val)
9011 {
9012         uint32_t cmd = 0;
9013
9014         switch (ring->funcs->type) {
9015         case AMDGPU_RING_TYPE_GFX:
9016                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9017                 break;
9018         case AMDGPU_RING_TYPE_KIQ:
9019                 cmd = (1 << 16); /* no inc addr */
9020                 break;
9021         default:
9022                 cmd = WR_CONFIRM;
9023                 break;
9024         }
9025         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9026         amdgpu_ring_write(ring, cmd);
9027         amdgpu_ring_write(ring, reg);
9028         amdgpu_ring_write(ring, 0);
9029         amdgpu_ring_write(ring, val);
9030 }
9031
9032 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9033                                         uint32_t val, uint32_t mask)
9034 {
9035         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9036 }
9037
9038 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9039                                                    uint32_t reg0, uint32_t reg1,
9040                                                    uint32_t ref, uint32_t mask)
9041 {
9042         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9043         struct amdgpu_device *adev = ring->adev;
9044         bool fw_version_ok = false;
9045
9046         fw_version_ok = adev->gfx.cp_fw_write_wait;
9047
9048         if (fw_version_ok)
9049                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9050                                        ref, mask, 0x20);
9051         else
9052                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9053                                                            ref, mask);
9054 }
9055
9056 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9057                                          unsigned vmid)
9058 {
9059         struct amdgpu_device *adev = ring->adev;
9060         uint32_t value = 0;
9061
9062         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9063         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9064         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9065         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9066         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9067 }
9068
9069 static void
9070 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9071                                       uint32_t me, uint32_t pipe,
9072                                       enum amdgpu_interrupt_state state)
9073 {
9074         uint32_t cp_int_cntl, cp_int_cntl_reg;
9075
9076         if (!me) {
9077                 switch (pipe) {
9078                 case 0:
9079                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9080                         break;
9081                 case 1:
9082                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9083                         break;
9084                 default:
9085                         DRM_DEBUG("invalid pipe %d\n", pipe);
9086                         return;
9087                 }
9088         } else {
9089                 DRM_DEBUG("invalid me %d\n", me);
9090                 return;
9091         }
9092
9093         switch (state) {
9094         case AMDGPU_IRQ_STATE_DISABLE:
9095                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9096                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9097                                             TIME_STAMP_INT_ENABLE, 0);
9098                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9099                 break;
9100         case AMDGPU_IRQ_STATE_ENABLE:
9101                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9102                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9103                                             TIME_STAMP_INT_ENABLE, 1);
9104                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9105                 break;
9106         default:
9107                 break;
9108         }
9109 }
9110
9111 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9112                                                      int me, int pipe,
9113                                                      enum amdgpu_interrupt_state state)
9114 {
9115         u32 mec_int_cntl, mec_int_cntl_reg;
9116
9117         /*
9118          * amdgpu controls only the first MEC. That's why this function only
9119          * handles the setting of interrupts for this specific MEC. All other
9120          * pipes' interrupts are set by amdkfd.
9121          */
9122
9123         if (me == 1) {
9124                 switch (pipe) {
9125                 case 0:
9126                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9127                         break;
9128                 case 1:
9129                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9130                         break;
9131                 case 2:
9132                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9133                         break;
9134                 case 3:
9135                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9136                         break;
9137                 default:
9138                         DRM_DEBUG("invalid pipe %d\n", pipe);
9139                         return;
9140                 }
9141         } else {
9142                 DRM_DEBUG("invalid me %d\n", me);
9143                 return;
9144         }
9145
9146         switch (state) {
9147         case AMDGPU_IRQ_STATE_DISABLE:
9148                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9149                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9150                                              TIME_STAMP_INT_ENABLE, 0);
9151                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9152                 break;
9153         case AMDGPU_IRQ_STATE_ENABLE:
9154                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9155                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9156                                              TIME_STAMP_INT_ENABLE, 1);
9157                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9158                 break;
9159         default:
9160                 break;
9161         }
9162 }
9163
9164 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9165                                             struct amdgpu_irq_src *src,
9166                                             unsigned type,
9167                                             enum amdgpu_interrupt_state state)
9168 {
9169         switch (type) {
9170         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9171                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9172                 break;
9173         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9174                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9175                 break;
9176         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9177                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9178                 break;
9179         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9180                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9181                 break;
9182         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9183                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9184                 break;
9185         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9186                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9187                 break;
9188         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9189                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9190                 break;
9191         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9192                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9193                 break;
9194         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9195                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9196                 break;
9197         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9198                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9199                 break;
9200         default:
9201                 break;
9202         }
9203         return 0;
9204 }
9205
9206 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9207                              struct amdgpu_irq_src *source,
9208                              struct amdgpu_iv_entry *entry)
9209 {
9210         int i;
9211         u8 me_id, pipe_id, queue_id;
9212         struct amdgpu_ring *ring;
9213         uint32_t mes_queue_id = entry->src_data[0];
9214
9215         DRM_DEBUG("IH: CP EOP\n");
9216
9217         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9218                 struct amdgpu_mes_queue *queue;
9219
9220                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9221
9222                 spin_lock(&adev->mes.queue_id_lock);
9223                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9224                 if (queue) {
9225                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9226                         amdgpu_fence_process(queue->ring);
9227                 }
9228                 spin_unlock(&adev->mes.queue_id_lock);
9229         } else {
9230                 me_id = (entry->ring_id & 0x0c) >> 2;
9231                 pipe_id = (entry->ring_id & 0x03) >> 0;
9232                 queue_id = (entry->ring_id & 0x70) >> 4;
9233
9234                 switch (me_id) {
9235                 case 0:
9236                         if (pipe_id == 0)
9237                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9238                         else
9239                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9240                         break;
9241                 case 1:
9242                 case 2:
9243                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9244                                 ring = &adev->gfx.compute_ring[i];
9245                                 /* Per-queue interrupt is supported for MEC starting from VI.
9246                                  * The interrupt can only be enabled/disabled per pipe instead
9247                                  * of per queue.
9248                                  */
9249                                 if ((ring->me == me_id) &&
9250                                     (ring->pipe == pipe_id) &&
9251                                     (ring->queue == queue_id))
9252                                         amdgpu_fence_process(ring);
9253                         }
9254                         break;
9255                 }
9256         }
9257
9258         return 0;
9259 }
9260
9261 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9262                                               struct amdgpu_irq_src *source,
9263                                               unsigned type,
9264                                               enum amdgpu_interrupt_state state)
9265 {
9266         switch (state) {
9267         case AMDGPU_IRQ_STATE_DISABLE:
9268         case AMDGPU_IRQ_STATE_ENABLE:
9269                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9270                                PRIV_REG_INT_ENABLE,
9271                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9272                 break;
9273         default:
9274                 break;
9275         }
9276
9277         return 0;
9278 }
9279
9280 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9281                                                struct amdgpu_irq_src *source,
9282                                                unsigned type,
9283                                                enum amdgpu_interrupt_state state)
9284 {
9285         switch (state) {
9286         case AMDGPU_IRQ_STATE_DISABLE:
9287         case AMDGPU_IRQ_STATE_ENABLE:
9288                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9289                                PRIV_INSTR_INT_ENABLE,
9290                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9291                 break;
9292         default:
9293                 break;
9294         }
9295
9296         return 0;
9297 }
9298
9299 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9300                                         struct amdgpu_iv_entry *entry)
9301 {
9302         u8 me_id, pipe_id, queue_id;
9303         struct amdgpu_ring *ring;
9304         int i;
9305
9306         me_id = (entry->ring_id & 0x0c) >> 2;
9307         pipe_id = (entry->ring_id & 0x03) >> 0;
9308         queue_id = (entry->ring_id & 0x70) >> 4;
9309
9310         switch (me_id) {
9311         case 0:
9312                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9313                         ring = &adev->gfx.gfx_ring[i];
9314                         /* we only enabled 1 gfx queue per pipe for now */
9315                         if (ring->me == me_id && ring->pipe == pipe_id)
9316                                 drm_sched_fault(&ring->sched);
9317                 }
9318                 break;
9319         case 1:
9320         case 2:
9321                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9322                         ring = &adev->gfx.compute_ring[i];
9323                         if (ring->me == me_id && ring->pipe == pipe_id &&
9324                             ring->queue == queue_id)
9325                                 drm_sched_fault(&ring->sched);
9326                 }
9327                 break;
9328         default:
9329                 BUG();
9330         }
9331 }
9332
9333 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9334                                   struct amdgpu_irq_src *source,
9335                                   struct amdgpu_iv_entry *entry)
9336 {
9337         DRM_ERROR("Illegal register access in command stream\n");
9338         gfx_v10_0_handle_priv_fault(adev, entry);
9339         return 0;
9340 }
9341
9342 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9343                                    struct amdgpu_irq_src *source,
9344                                    struct amdgpu_iv_entry *entry)
9345 {
9346         DRM_ERROR("Illegal instruction in command stream\n");
9347         gfx_v10_0_handle_priv_fault(adev, entry);
9348         return 0;
9349 }
9350
9351 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9352                                              struct amdgpu_irq_src *src,
9353                                              unsigned int type,
9354                                              enum amdgpu_interrupt_state state)
9355 {
9356         uint32_t tmp, target;
9357         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9358
9359         if (ring->me == 1)
9360                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9361         else
9362                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9363         target += ring->pipe;
9364
9365         switch (type) {
9366         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9367                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9368                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9369                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9370                                             GENERIC2_INT_ENABLE, 0);
9371                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9372
9373                         tmp = RREG32_SOC15_IP(GC, target);
9374                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9375                                             GENERIC2_INT_ENABLE, 0);
9376                         WREG32_SOC15_IP(GC, target, tmp);
9377                 } else {
9378                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9379                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9380                                             GENERIC2_INT_ENABLE, 1);
9381                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9382
9383                         tmp = RREG32_SOC15_IP(GC, target);
9384                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9385                                             GENERIC2_INT_ENABLE, 1);
9386                         WREG32_SOC15_IP(GC, target, tmp);
9387                 }
9388                 break;
9389         default:
9390                 BUG(); /* kiq only support GENERIC2_INT now */
9391                 break;
9392         }
9393         return 0;
9394 }
9395
9396 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9397                              struct amdgpu_irq_src *source,
9398                              struct amdgpu_iv_entry *entry)
9399 {
9400         u8 me_id, pipe_id, queue_id;
9401         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9402
9403         me_id = (entry->ring_id & 0x0c) >> 2;
9404         pipe_id = (entry->ring_id & 0x03) >> 0;
9405         queue_id = (entry->ring_id & 0x70) >> 4;
9406         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9407                    me_id, pipe_id, queue_id);
9408
9409         amdgpu_fence_process(ring);
9410         return 0;
9411 }
9412
9413 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9414 {
9415         const unsigned int gcr_cntl =
9416                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9417                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9418                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9419                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9420                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9421                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9422                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9423                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9424
9425         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9426         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9427         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9428         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9429         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9430         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9431         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9432         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9433         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9434 }
9435
9436 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9437         .name = "gfx_v10_0",
9438         .early_init = gfx_v10_0_early_init,
9439         .late_init = gfx_v10_0_late_init,
9440         .sw_init = gfx_v10_0_sw_init,
9441         .sw_fini = gfx_v10_0_sw_fini,
9442         .hw_init = gfx_v10_0_hw_init,
9443         .hw_fini = gfx_v10_0_hw_fini,
9444         .suspend = gfx_v10_0_suspend,
9445         .resume = gfx_v10_0_resume,
9446         .is_idle = gfx_v10_0_is_idle,
9447         .wait_for_idle = gfx_v10_0_wait_for_idle,
9448         .soft_reset = gfx_v10_0_soft_reset,
9449         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9450         .set_powergating_state = gfx_v10_0_set_powergating_state,
9451         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9452 };
9453
9454 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9455         .type = AMDGPU_RING_TYPE_GFX,
9456         .align_mask = 0xff,
9457         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9458         .support_64bit_ptrs = true,
9459         .secure_submission_supported = true,
9460         .vmhub = AMDGPU_GFXHUB_0,
9461         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9462         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9463         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9464         .emit_frame_size = /* totally 242 maximum if 16 IBs */
9465                 5 + /* COND_EXEC */
9466                 7 + /* PIPELINE_SYNC */
9467                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9468                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9469                 2 + /* VM_FLUSH */
9470                 8 + /* FENCE for VM_FLUSH */
9471                 20 + /* GDS switch */
9472                 4 + /* double SWITCH_BUFFER,
9473                      * the first COND_EXEC jump to the place
9474                      * just prior to this double SWITCH_BUFFER
9475                      */
9476                 5 + /* COND_EXEC */
9477                 7 + /* HDP_flush */
9478                 4 + /* VGT_flush */
9479                 14 + /* CE_META */
9480                 31 + /* DE_META */
9481                 3 + /* CNTX_CTRL */
9482                 5 + /* HDP_INVL */
9483                 8 + 8 + /* FENCE x2 */
9484                 2 + /* SWITCH_BUFFER */
9485                 8, /* gfx_v10_0_emit_mem_sync */
9486         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9487         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9488         .emit_fence = gfx_v10_0_ring_emit_fence,
9489         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9490         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9491         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9492         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9493         .test_ring = gfx_v10_0_ring_test_ring,
9494         .test_ib = gfx_v10_0_ring_test_ib,
9495         .insert_nop = amdgpu_ring_insert_nop,
9496         .pad_ib = amdgpu_ring_generic_pad_ib,
9497         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9498         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9499         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9500         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9501         .preempt_ib = gfx_v10_0_ring_preempt_ib,
9502         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9503         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9504         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9505         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9506         .soft_recovery = gfx_v10_0_ring_soft_recovery,
9507         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9508 };
9509
9510 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9511         .type = AMDGPU_RING_TYPE_COMPUTE,
9512         .align_mask = 0xff,
9513         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9514         .support_64bit_ptrs = true,
9515         .vmhub = AMDGPU_GFXHUB_0,
9516         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9517         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9518         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9519         .emit_frame_size =
9520                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9521                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9522                 5 + /* hdp invalidate */
9523                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9524                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9525                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9526                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9527                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9528                 8, /* gfx_v10_0_emit_mem_sync */
9529         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9530         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9531         .emit_fence = gfx_v10_0_ring_emit_fence,
9532         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9533         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9534         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9535         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9536         .test_ring = gfx_v10_0_ring_test_ring,
9537         .test_ib = gfx_v10_0_ring_test_ib,
9538         .insert_nop = amdgpu_ring_insert_nop,
9539         .pad_ib = amdgpu_ring_generic_pad_ib,
9540         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9541         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9542         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9543         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9544 };
9545
9546 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9547         .type = AMDGPU_RING_TYPE_KIQ,
9548         .align_mask = 0xff,
9549         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9550         .support_64bit_ptrs = true,
9551         .vmhub = AMDGPU_GFXHUB_0,
9552         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9553         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9554         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9555         .emit_frame_size =
9556                 20 + /* gfx_v10_0_ring_emit_gds_switch */
9557                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9558                 5 + /*hdp invalidate */
9559                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9560                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9561                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9562                 2 + /* gfx_v10_0_ring_emit_vm_flush */
9563                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9564         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9565         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9566         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9567         .test_ring = gfx_v10_0_ring_test_ring,
9568         .test_ib = gfx_v10_0_ring_test_ib,
9569         .insert_nop = amdgpu_ring_insert_nop,
9570         .pad_ib = amdgpu_ring_generic_pad_ib,
9571         .emit_rreg = gfx_v10_0_ring_emit_rreg,
9572         .emit_wreg = gfx_v10_0_ring_emit_wreg,
9573         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9574         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9575 };
9576
9577 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9578 {
9579         int i;
9580
9581         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9582
9583         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9584                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9585
9586         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9587                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9588 }
9589
9590 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9591         .set = gfx_v10_0_set_eop_interrupt_state,
9592         .process = gfx_v10_0_eop_irq,
9593 };
9594
9595 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9596         .set = gfx_v10_0_set_priv_reg_fault_state,
9597         .process = gfx_v10_0_priv_reg_irq,
9598 };
9599
9600 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9601         .set = gfx_v10_0_set_priv_inst_fault_state,
9602         .process = gfx_v10_0_priv_inst_irq,
9603 };
9604
9605 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9606         .set = gfx_v10_0_kiq_set_interrupt_state,
9607         .process = gfx_v10_0_kiq_irq,
9608 };
9609
9610 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9611 {
9612         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9613         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9614
9615         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9616         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9617
9618         adev->gfx.priv_reg_irq.num_types = 1;
9619         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9620
9621         adev->gfx.priv_inst_irq.num_types = 1;
9622         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9623 }
9624
9625 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9626 {
9627         switch (adev->ip_versions[GC_HWIP][0]) {
9628         case IP_VERSION(10, 1, 10):
9629         case IP_VERSION(10, 1, 1):
9630         case IP_VERSION(10, 1, 3):
9631         case IP_VERSION(10, 1, 4):
9632         case IP_VERSION(10, 3, 2):
9633         case IP_VERSION(10, 3, 1):
9634         case IP_VERSION(10, 3, 4):
9635         case IP_VERSION(10, 3, 5):
9636         case IP_VERSION(10, 3, 6):
9637         case IP_VERSION(10, 3, 3):
9638         case IP_VERSION(10, 3, 7):
9639                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9640                 break;
9641         case IP_VERSION(10, 1, 2):
9642         case IP_VERSION(10, 3, 0):
9643                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9644                 break;
9645         default:
9646                 break;
9647         }
9648 }
9649
9650 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9651 {
9652         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9653                             adev->gfx.config.max_sh_per_se *
9654                             adev->gfx.config.max_shader_engines;
9655
9656         adev->gds.gds_size = 0x10000;
9657         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9658         adev->gds.gws_size = 64;
9659         adev->gds.oa_size = 16;
9660 }
9661
9662 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9663 {
9664         /* set gfx eng mqd */
9665         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9666                 sizeof(struct v10_gfx_mqd);
9667         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9668                 gfx_v10_0_gfx_mqd_init;
9669         /* set compute eng mqd */
9670         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9671                 sizeof(struct v10_compute_mqd);
9672         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9673                 gfx_v10_0_compute_mqd_init;
9674 }
9675
9676 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9677                                                           u32 bitmap)
9678 {
9679         u32 data;
9680
9681         if (!bitmap)
9682                 return;
9683
9684         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9685         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9686
9687         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9688 }
9689
9690 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9691 {
9692         u32 disabled_mask =
9693                 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9694         u32 efuse_setting = 0;
9695         u32 vbios_setting = 0;
9696
9697         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9698         efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9699         efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9700
9701         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9702         vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9703         vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9704
9705         disabled_mask |= efuse_setting | vbios_setting;
9706
9707         return (~disabled_mask);
9708 }
9709
9710 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9711 {
9712         u32 wgp_idx, wgp_active_bitmap;
9713         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9714
9715         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9716         cu_active_bitmap = 0;
9717
9718         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9719                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9720                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9721                 if (wgp_active_bitmap & (1 << wgp_idx))
9722                         cu_active_bitmap |= cu_bitmap_per_wgp;
9723         }
9724
9725         return cu_active_bitmap;
9726 }
9727
9728 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9729                                  struct amdgpu_cu_info *cu_info)
9730 {
9731         int i, j, k, counter, active_cu_number = 0;
9732         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9733         unsigned disable_masks[4 * 2];
9734
9735         if (!adev || !cu_info)
9736                 return -EINVAL;
9737
9738         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9739
9740         mutex_lock(&adev->grbm_idx_mutex);
9741         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9742                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9743                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9744                         if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9745                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9746                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9747                              (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9748                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9749                                 continue;
9750                         mask = 1;
9751                         ao_bitmap = 0;
9752                         counter = 0;
9753                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9754                         if (i < 4 && j < 2)
9755                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9756                                         adev, disable_masks[i * 2 + j]);
9757                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9758                         cu_info->bitmap[i][j] = bitmap;
9759
9760                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9761                                 if (bitmap & mask) {
9762                                         if (counter < adev->gfx.config.max_cu_per_sh)
9763                                                 ao_bitmap |= mask;
9764                                         counter++;
9765                                 }
9766                                 mask <<= 1;
9767                         }
9768                         active_cu_number += counter;
9769                         if (i < 2 && j < 2)
9770                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9771                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9772                 }
9773         }
9774         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9775         mutex_unlock(&adev->grbm_idx_mutex);
9776
9777         cu_info->number = active_cu_number;
9778         cu_info->ao_cu_mask = ao_cu_mask;
9779         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9780
9781         return 0;
9782 }
9783
9784 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9785 {
9786         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9787
9788         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9789         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9790         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9791
9792         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9793         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9794         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9795
9796         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9797                                                 adev->gfx.config.max_shader_engines);
9798         disabled_sa = efuse_setting | vbios_setting;
9799         disabled_sa &= max_sa_mask;
9800
9801         return disabled_sa;
9802 }
9803
9804 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9805 {
9806         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9807         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9808
9809         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9810
9811         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9812         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9813         max_shader_engines = adev->gfx.config.max_shader_engines;
9814
9815         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9816                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9817                 disabled_sa_per_se &= max_sa_per_se_mask;
9818                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9819                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9820                         break;
9821                 }
9822         }
9823 }
9824
9825 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9826 {
9827         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9828                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9829                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9830                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9831
9832         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9833         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9834                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9835                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9836                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9837                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9838
9839         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9840                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9841                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9842                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9843
9844         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9845
9846         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9847                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9848 }
9849
9850 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9851 {
9852         .type = AMD_IP_BLOCK_TYPE_GFX,
9853         .major = 10,
9854         .minor = 0,
9855         .rev = 0,
9856         .funcs = &gfx_v10_0_ip_funcs,
9857 };