drivers/gpu/drm/i915/display/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/time.h>
  25
  26 #include "hsw_ips.h"
  27 #include "i915_reg.h"
  28 #include "intel_atomic.h"
  29 #include "intel_atomic_plane.h"
  30 #include "intel_audio.h"
  31 #include "intel_bw.h"
  32 #include "intel_cdclk.h"
  33 #include "intel_crtc.h"
  34 #include "intel_de.h"
  35 #include "intel_dp.h"
  36 #include "intel_display_types.h"
  37 #include "intel_mchbar_regs.h"
  38 #include "intel_pci_config.h"
  39 #include "intel_pcode.h"
  40 #include "intel_psr.h"
  41 #include "intel_vdsc.h"
  42 #include "vlv_sideband.h"
  43
  44 /**
  45  * DOC: CDCLK / RAWCLK
  46  *
  47  * The display engine uses several different clocks to do its work. There
  48  * are two main clocks involved that aren't directly related to the actual
  49  * pixel clock or any symbol/bit clock of the actual output port. These
  50  * are the core display clock (CDCLK) and RAWCLK.
  51  *
  52  * CDCLK clocks most of the display pipe logic, and thus its frequency
  53  * must be high enough to support the rate at which pixels are flowing
  54  * through the pipes. Downscaling must also be accounted as that increases
  55  * the effective pixel rate.
  56  *
  57  * On several platforms the CDCLK frequency can be changed dynamically
  58  * to minimize power consumption for a given display configuration.
  59  * Typically changes to the CDCLK frequency require all the display pipes
  60  * to be shut down while the frequency is being changed.
  61  *
  62  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  63  * DMC will not change the active CDCLK frequency however, so that part
  64  * will still be performed by the driver directly.
  65  *
  66  * There are multiple components involved in the generation of the CDCLK
  67  * frequency:
  68  *
  69  * - We have the CDCLK PLL, which generates an output clock based on a
  70  *   reference clock and a ratio parameter.
  71  * - The CD2X Divider, which divides the output of the PLL based on a
  72  *   divisor selected from a set of pre-defined choices.
  73  * - The CD2X Squasher, which further divides the output based on a
  74  *   waveform represented as a sequence of bits where each zero
  75  *   "squashes out" a clock cycle.
  76  * - And, finally, a fixed divider that divides the output frequency by 2.
  77  *
  78  * As such, the resulting CDCLK frequency can be calculated with the
  79  * following formula:
  80  *
  81  *     cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
  82  *
  83  * , where vco is the frequency generated by the PLL; cd2x_div
  84  * represents the CD2X Divider; sq_len and sq_div are the bit length
  85  * and the number of high bits for the CD2X Squasher waveform, respectively;
  86  * and 2 represents the fixed divider.
  87  *
  88  * Note that some older platforms do not contain the CD2X Divider
  89  * and/or CD2X Squasher, in which case we can ignore their respective
  90  * factors in the formula above.
  91  *
  92  * Several methods exist to change the CDCLK frequency, which ones are
  93  * supported depends on the platform:
  94  *
  95  * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
  96  * - CD2X divider update. Single pipe can be active as the divider update
  97  *   can be synchronized with the pipe's start of vblank.
  98  * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
  99  * - Squash waveform update. Pipes can be active.
 100  * - Crawl and squash can also be done back to back. Pipes can be active.
 101  *
 102  * RAWCLK is a fixed frequency clock, often used by various auxiliary
 103  * blocks such as AUX CH or backlight PWM. Hence the only thing we
 104  * really need to know about RAWCLK is its frequency so that various
 105  * dividers can be programmed correctly.
 106  */
 107
 108 struct intel_cdclk_funcs {
 109         void (*get_cdclk)(struct drm_i915_private *i915,
 110                           struct intel_cdclk_config *cdclk_config);
 111         void (*set_cdclk)(struct drm_i915_private *i915,
 112                           const struct intel_cdclk_config *cdclk_config,
 113                           enum pipe pipe);
 114         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 115         u8 (*calc_voltage_level)(int cdclk);
 116 };
 117
 118 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
 119                            struct intel_cdclk_config *cdclk_config)
 120 {
 121         dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
 122 }
 123
 124 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
 125                                   const struct intel_cdclk_config *cdclk_config,
 126                                   enum pipe pipe)
 127 {
 128         dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
 129 }
 130
 131 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
 132                                           struct intel_cdclk_state *cdclk_config)
 133 {
 134         return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
 135 }
 136
 137 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 138                                          int cdclk)
 139 {
 140         return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
 141 }
 142
 143 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
 144                                    struct intel_cdclk_config *cdclk_config)
 145 {
 146         cdclk_config->cdclk = 133333;
 147 }
 148
 149 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
 150                                    struct intel_cdclk_config *cdclk_config)
 151 {
 152         cdclk_config->cdclk = 200000;
 153 }
 154
 155 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
 156                                    struct intel_cdclk_config *cdclk_config)
 157 {
 158         cdclk_config->cdclk = 266667;
 159 }
 160
 161 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
 162                                    struct intel_cdclk_config *cdclk_config)
 163 {
 164         cdclk_config->cdclk = 333333;
 165 }
 166
 167 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
 168                                    struct intel_cdclk_config *cdclk_config)
 169 {
 170         cdclk_config->cdclk = 400000;
 171 }
 172
 173 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
 174                                    struct intel_cdclk_config *cdclk_config)
 175 {
 176         cdclk_config->cdclk = 450000;
 177 }
 178
 179 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
 180                            struct intel_cdclk_config *cdclk_config)
 181 {
 182         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 183         u16 hpllcc = 0;
 184
 185         /*
 186          * 852GM/852GMV only supports 133 MHz and the HPLLCC
 187          * encoding is different :(
 188          * FIXME is this the right way to detect 852GM/852GMV?
 189          */
 190         if (pdev->revision == 0x1) {
 191                 cdclk_config->cdclk = 133333;
 192                 return;
 193         }
 194
 195         pci_bus_read_config_word(pdev->bus,
 196                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 197
 198         /* Assume that the hardware is in the high speed state.  This
 199          * should be the default.
 200          */
 201         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 202         case GC_CLOCK_133_200:
 203         case GC_CLOCK_133_200_2:
 204         case GC_CLOCK_100_200:
 205                 cdclk_config->cdclk = 200000;
 206                 break;
 207         case GC_CLOCK_166_250:
 208                 cdclk_config->cdclk = 250000;
 209                 break;
 210         case GC_CLOCK_100_133:
 211                 cdclk_config->cdclk = 133333;
 212                 break;
 213         case GC_CLOCK_133_266:
 214         case GC_CLOCK_133_266_2:
 215         case GC_CLOCK_166_266:
 216                 cdclk_config->cdclk = 266667;
 217                 break;
 218         }
 219 }
 220
 221 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 222                              struct intel_cdclk_config *cdclk_config)
 223 {
 224         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 225         u16 gcfgc = 0;
 226
 227         pci_read_config_word(pdev, GCFGC, &gcfgc);
 228
 229         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 230                 cdclk_config->cdclk = 133333;
 231                 return;
 232         }
 233
 234         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 235         case GC_DISPLAY_CLOCK_333_320_MHZ:
 236                 cdclk_config->cdclk = 333333;
 237                 break;
 238         default:
 239         case GC_DISPLAY_CLOCK_190_200_MHZ:
 240                 cdclk_config->cdclk = 190000;
 241                 break;
 242         }
 243 }
 244
 245 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 246                              struct intel_cdclk_config *cdclk_config)
 247 {
 248         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 249         u16 gcfgc = 0;
 250
 251         pci_read_config_word(pdev, GCFGC, &gcfgc);
 252
 253         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 254                 cdclk_config->cdclk = 133333;
 255                 return;
 256         }
 257
 258         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 259         case GC_DISPLAY_CLOCK_333_320_MHZ:
 260                 cdclk_config->cdclk = 320000;
 261                 break;
 262         default:
 263         case GC_DISPLAY_CLOCK_190_200_MHZ:
 264                 cdclk_config->cdclk = 200000;
 265                 break;
 266         }
 267 }
 268
 269 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 270 {
 271         static const unsigned int blb_vco[8] = {
 272                 [0] = 3200000,
 273                 [1] = 4000000,
 274                 [2] = 5333333,
 275                 [3] = 4800000,
 276                 [4] = 6400000,
 277         };
 278         static const unsigned int pnv_vco[8] = {
 279                 [0] = 3200000,
 280                 [1] = 4000000,
 281                 [2] = 5333333,
 282                 [3] = 4800000,
 283                 [4] = 2666667,
 284         };
 285         static const unsigned int cl_vco[8] = {
 286                 [0] = 3200000,
 287                 [1] = 4000000,
 288                 [2] = 5333333,
 289                 [3] = 6400000,
 290                 [4] = 3333333,
 291                 [5] = 3566667,
 292                 [6] = 4266667,
 293         };
 294         static const unsigned int elk_vco[8] = {
 295                 [0] = 3200000,
 296                 [1] = 4000000,
 297                 [2] = 5333333,
 298                 [3] = 4800000,
 299         };
 300         static const unsigned int ctg_vco[8] = {
 301                 [0] = 3200000,
 302                 [1] = 4000000,
 303                 [2] = 5333333,
 304                 [3] = 6400000,
 305                 [4] = 2666667,
 306                 [5] = 4266667,
 307         };
 308         const unsigned int *vco_table;
 309         unsigned int vco;
 310         u8 tmp = 0;
 311
 312         /* FIXME other chipsets? */
 313         if (IS_GM45(dev_priv))
 314                 vco_table = ctg_vco;
 315         else if (IS_G45(dev_priv))
 316                 vco_table = elk_vco;
 317         else if (IS_I965GM(dev_priv))
 318                 vco_table = cl_vco;
 319         else if (IS_PINEVIEW(dev_priv))
 320                 vco_table = pnv_vco;
 321         else if (IS_G33(dev_priv))
 322                 vco_table = blb_vco;
 323         else
 324                 return 0;
 325
 326         tmp = intel_de_read(dev_priv,
 327                             IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 328
 329         vco = vco_table[tmp & 0x7];
 330         if (vco == 0)
 331                 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
 332                         tmp);
 333         else
 334                 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
 335
 336         return vco;
 337 }
 338
 339 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 340                           struct intel_cdclk_config *cdclk_config)
 341 {
 342         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 343         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 344         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 345         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 346         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 347         const u8 *div_table;
 348         unsigned int cdclk_sel;
 349         u16 tmp = 0;
 350
 351         cdclk_config->vco = intel_hpll_vco(dev_priv);
 352
 353         pci_read_config_word(pdev, GCFGC, &tmp);
 354
 355         cdclk_sel = (tmp >> 4) & 0x7;
 356
 357         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 358                 goto fail;
 359
 360         switch (cdclk_config->vco) {
 361         case 3200000:
 362                 div_table = div_3200;
 363                 break;
 364         case 4000000:
 365                 div_table = div_4000;
 366                 break;
 367         case 4800000:
 368                 div_table = div_4800;
 369                 break;
 370         case 5333333:
 371                 div_table = div_5333;
 372                 break;
 373         default:
 374                 goto fail;
 375         }
 376
 377         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 378                                                 div_table[cdclk_sel]);
 379         return;
 380
 381 fail:
 382         drm_err(&dev_priv->drm,
 383                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 384                 cdclk_config->vco, tmp);
 385         cdclk_config->cdclk = 190476;
 386 }
 387
 388 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 389                           struct intel_cdclk_config *cdclk_config)
 390 {
 391         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 392         u16 gcfgc = 0;
 393
 394         pci_read_config_word(pdev, GCFGC, &gcfgc);
 395
 396         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 397         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 398                 cdclk_config->cdclk = 266667;
 399                 break;
 400         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 401                 cdclk_config->cdclk = 333333;
 402                 break;
 403         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 404                 cdclk_config->cdclk = 444444;
 405                 break;
 406         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 407                 cdclk_config->cdclk = 200000;
 408                 break;
 409         default:
 410                 drm_err(&dev_priv->drm,
 411                         "Unknown pnv display core clock 0x%04x\n", gcfgc);
 412                 fallthrough;
 413         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 414                 cdclk_config->cdclk = 133333;
 415                 break;
 416         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 417                 cdclk_config->cdclk = 166667;
 418                 break;
 419         }
 420 }
 421
 422 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 423                              struct intel_cdclk_config *cdclk_config)
 424 {
 425         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 426         static const u8 div_3200[] = { 16, 10,  8 };
 427         static const u8 div_4000[] = { 20, 12, 10 };
 428         static const u8 div_5333[] = { 24, 16, 14 };
 429         const u8 *div_table;
 430         unsigned int cdclk_sel;
 431         u16 tmp = 0;
 432
 433         cdclk_config->vco = intel_hpll_vco(dev_priv);
 434
 435         pci_read_config_word(pdev, GCFGC, &tmp);
 436
 437         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 438
 439         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 440                 goto fail;
 441
 442         switch (cdclk_config->vco) {
 443         case 3200000:
 444                 div_table = div_3200;
 445                 break;
 446         case 4000000:
 447                 div_table = div_4000;
 448                 break;
 449         case 5333333:
 450                 div_table = div_5333;
 451                 break;
 452         default:
 453                 goto fail;
 454         }
 455
 456         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 457                                                 div_table[cdclk_sel]);
 458         return;
 459
 460 fail:
 461         drm_err(&dev_priv->drm,
 462                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 463                 cdclk_config->vco, tmp);
 464         cdclk_config->cdclk = 200000;
 465 }
 466
 467 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 468                            struct intel_cdclk_config *cdclk_config)
 469 {
 470         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 471         unsigned int cdclk_sel;
 472         u16 tmp = 0;
 473
 474         cdclk_config->vco = intel_hpll_vco(dev_priv);
 475
 476         pci_read_config_word(pdev, GCFGC, &tmp);
 477
 478         cdclk_sel = (tmp >> 12) & 0x1;
 479
 480         switch (cdclk_config->vco) {
 481         case 2666667:
 482         case 4000000:
 483         case 5333333:
 484                 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
 485                 break;
 486         case 3200000:
 487                 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
 488                 break;
 489         default:
 490                 drm_err(&dev_priv->drm,
 491                         "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 492                         cdclk_config->vco, tmp);
 493                 cdclk_config->cdclk = 222222;
 494                 break;
 495         }
 496 }
 497
 498 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 499                           struct intel_cdclk_config *cdclk_config)
 500 {
 501         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 502         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 503
 504         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 505                 cdclk_config->cdclk = 800000;
 506         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 507                 cdclk_config->cdclk = 450000;
 508         else if (freq == LCPLL_CLK_FREQ_450)
 509                 cdclk_config->cdclk = 450000;
 510         else if (IS_HASWELL_ULT(dev_priv))
 511                 cdclk_config->cdclk = 337500;
 512         else
 513                 cdclk_config->cdclk = 540000;
 514 }
 515
 516 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 517 {
 518         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 519                 333333 : 320000;
 520
 521         /*
 522          * We seem to get an unstable or solid color picture at 200MHz.
 523          * Not sure what's wrong. For now use 200MHz only when all pipes
 524          * are off.
 525          */
 526         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 527                 return 400000;
 528         else if (min_cdclk > 266667)
 529                 return freq_320;
 530         else if (min_cdclk > 0)
 531                 return 266667;
 532         else
 533                 return 200000;
 534 }
 535
 536 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 537 {
 538         if (IS_VALLEYVIEW(dev_priv)) {
 539                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 540                         return 2;
 541                 else if (cdclk >= 266667)
 542                         return 1;
 543                 else
 544                         return 0;
 545         } else {
 546                 /*
 547                  * Specs are full of misinformation, but testing on actual
 548                  * hardware has shown that we just need to write the desired
 549                  * CCK divider into the Punit register.
 550                  */
 551                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 552         }
 553 }
 554
 555 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 556                           struct intel_cdclk_config *cdclk_config)
 557 {
 558         u32 val;
 559
 560         vlv_iosf_sb_get(dev_priv,
 561                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 562
 563         cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
 564         cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 565                                                 CCK_DISPLAY_CLOCK_CONTROL,
 566                                                 cdclk_config->vco);
 567
 568         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 569
 570         vlv_iosf_sb_put(dev_priv,
 571                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 572
 573         if (IS_VALLEYVIEW(dev_priv))
 574                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
 575                         DSPFREQGUAR_SHIFT;
 576         else
 577                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 578                         DSPFREQGUAR_SHIFT_CHV;
 579 }
 580
 581 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 582 {
 583         unsigned int credits, default_credits;
 584
 585         if (IS_CHERRYVIEW(dev_priv))
 586                 default_credits = PFI_CREDIT(12);
 587         else
 588                 default_credits = PFI_CREDIT(8);
 589
 590         if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 591                 /* CHV suggested value is 31 or 63 */
 592                 if (IS_CHERRYVIEW(dev_priv))
 593                         credits = PFI_CREDIT_63;
 594                 else
 595                         credits = PFI_CREDIT(15);
 596         } else {
 597                 credits = default_credits;
 598         }
 599
 600         /*
 601          * WA - write default credits before re-programming
 602          * FIXME: should we also set the resend bit here?
 603          */
 604         intel_de_write(dev_priv, GCI_CONTROL,
 605                        VGA_FAST_MODE_DISABLE | default_credits);
 606
 607         intel_de_write(dev_priv, GCI_CONTROL,
 608                        VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
 609
 610         /*
 611          * FIXME is this guaranteed to clear
 612          * immediately or should we poll for it?
 613          */
 614         drm_WARN_ON(&dev_priv->drm,
 615                     intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
 616 }
 617
 618 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 619                           const struct intel_cdclk_config *cdclk_config,
 620                           enum pipe pipe)
 621 {
 622         int cdclk = cdclk_config->cdclk;
 623         u32 val, cmd = cdclk_config->voltage_level;
 624         intel_wakeref_t wakeref;
 625
 626         switch (cdclk) {
 627         case 400000:
 628         case 333333:
 629         case 320000:
 630         case 266667:
 631         case 200000:
 632                 break;
 633         default:
 634                 MISSING_CASE(cdclk);
 635                 return;
 636         }
 637
 638         /* There are cases where we can end up here with power domains
 639          * off and a CDCLK frequency other than the minimum, like when
 640          * issuing a modeset without actually changing any display after
 641          * a system suspend.  So grab the display core domain, which covers
 642          * the HW blocks needed for the following programming.
 643          */
 644         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 645
 646         vlv_iosf_sb_get(dev_priv,
 647                         BIT(VLV_IOSF_SB_CCK) |
 648                         BIT(VLV_IOSF_SB_BUNIT) |
 649                         BIT(VLV_IOSF_SB_PUNIT));
 650
 651         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 652         val &= ~DSPFREQGUAR_MASK;
 653         val |= (cmd << DSPFREQGUAR_SHIFT);
 654         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 655         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 656                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 657                      50)) {
 658                 drm_err(&dev_priv->drm,
 659                         "timed out waiting for CDclk change\n");
 660         }
 661
 662         if (cdclk == 400000) {
 663                 u32 divider;
 664
 665                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 666                                             cdclk) - 1;
 667
 668                 /* adjust cdclk divider */
 669                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 670                 val &= ~CCK_FREQUENCY_VALUES;
 671                 val |= divider;
 672                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 673
 674                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 675                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 676                              50))
 677                         drm_err(&dev_priv->drm,
 678                                 "timed out waiting for CDclk change\n");
 679         }
 680
 681         /* adjust self-refresh exit latency value */
 682         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 683         val &= ~0x7f;
 684
 685         /*
 686          * For high bandwidth configs, we set a higher latency in the bunit
 687          * so that the core display fetch happens in time to avoid underruns.
 688          */
 689         if (cdclk == 400000)
 690                 val |= 4500 / 250; /* 4.5 usec */
 691         else
 692                 val |= 3000 / 250; /* 3.0 usec */
 693         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 694
 695         vlv_iosf_sb_put(dev_priv,
 696                         BIT(VLV_IOSF_SB_CCK) |
 697                         BIT(VLV_IOSF_SB_BUNIT) |
 698                         BIT(VLV_IOSF_SB_PUNIT));
 699
 700         intel_update_cdclk(dev_priv);
 701
 702         vlv_program_pfi_credits(dev_priv);
 703
 704         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 705 }
 706
 707 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 708                           const struct intel_cdclk_config *cdclk_config,
 709                           enum pipe pipe)
 710 {
 711         int cdclk = cdclk_config->cdclk;
 712         u32 val, cmd = cdclk_config->voltage_level;
 713         intel_wakeref_t wakeref;
 714
 715         switch (cdclk) {
 716         case 333333:
 717         case 320000:
 718         case 266667:
 719         case 200000:
 720                 break;
 721         default:
 722                 MISSING_CASE(cdclk);
 723                 return;
 724         }
 725
 726         /* There are cases where we can end up here with power domains
 727          * off and a CDCLK frequency other than the minimum, like when
 728          * issuing a modeset without actually changing any display after
 729          * a system suspend.  So grab the display core domain, which covers
 730          * the HW blocks needed for the following programming.
 731          */
 732         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 733
 734         vlv_punit_get(dev_priv);
 735         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 736         val &= ~DSPFREQGUAR_MASK_CHV;
 737         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 738         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 739         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 740                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 741                      50)) {
 742                 drm_err(&dev_priv->drm,
 743                         "timed out waiting for CDclk change\n");
 744         }
 745
 746         vlv_punit_put(dev_priv);
 747
 748         intel_update_cdclk(dev_priv);
 749
 750         vlv_program_pfi_credits(dev_priv);
 751
 752         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 753 }
 754
 755 static int bdw_calc_cdclk(int min_cdclk)
 756 {
 757         if (min_cdclk > 540000)
 758                 return 675000;
 759         else if (min_cdclk > 450000)
 760                 return 540000;
 761         else if (min_cdclk > 337500)
 762                 return 450000;
 763         else
 764                 return 337500;
 765 }
 766
 767 static u8 bdw_calc_voltage_level(int cdclk)
 768 {
 769         switch (cdclk) {
 770         default:
 771         case 337500:
 772                 return 2;
 773         case 450000:
 774                 return 0;
 775         case 540000:
 776                 return 1;
 777         case 675000:
 778                 return 3;
 779         }
 780 }
 781
 782 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 783                           struct intel_cdclk_config *cdclk_config)
 784 {
 785         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 786         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 787
 788         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 789                 cdclk_config->cdclk = 800000;
 790         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 791                 cdclk_config->cdclk = 450000;
 792         else if (freq == LCPLL_CLK_FREQ_450)
 793                 cdclk_config->cdclk = 450000;
 794         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 795                 cdclk_config->cdclk = 540000;
 796         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 797                 cdclk_config->cdclk = 337500;
 798         else
 799                 cdclk_config->cdclk = 675000;
 800
 801         /*
 802          * Can't read this out :( Let's assume it's
 803          * at least what the CDCLK frequency requires.
 804          */
 805         cdclk_config->voltage_level =
 806                 bdw_calc_voltage_level(cdclk_config->cdclk);
 807 }
 808
 809 static u32 bdw_cdclk_freq_sel(int cdclk)
 810 {
 811         switch (cdclk) {
 812         default:
 813                 MISSING_CASE(cdclk);
 814                 fallthrough;
 815         case 337500:
 816                 return LCPLL_CLK_FREQ_337_5_BDW;
 817         case 450000:
 818                 return LCPLL_CLK_FREQ_450;
 819         case 540000:
 820                 return LCPLL_CLK_FREQ_54O_BDW;
 821         case 675000:
 822                 return LCPLL_CLK_FREQ_675_BDW;
 823         }
 824 }
 825
 826 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 827                           const struct intel_cdclk_config *cdclk_config,
 828                           enum pipe pipe)
 829 {
 830         int cdclk = cdclk_config->cdclk;
 831         int ret;
 832
 833         if (drm_WARN(&dev_priv->drm,
 834                      (intel_de_read(dev_priv, LCPLL_CTL) &
 835                       (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 836                        LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 837                        LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 838                        LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 839                      "trying to change cdclk frequency with cdclk not enabled\n"))
 840                 return;
 841
 842         ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 843         if (ret) {
 844                 drm_err(&dev_priv->drm,
 845                         "failed to inform pcode about cdclk change\n");
 846                 return;
 847         }
 848
 849         intel_de_rmw(dev_priv, LCPLL_CTL,
 850                      0, LCPLL_CD_SOURCE_FCLK);
 851
 852         /*
 853          * According to the spec, it should be enough to poll for this 1 us.
 854          * However, extensive testing shows that this can take longer.
 855          */
 856         if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
 857                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 858                 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
 859
 860         intel_de_rmw(dev_priv, LCPLL_CTL,
 861                      LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
 862
 863         intel_de_rmw(dev_priv, LCPLL_CTL,
 864                      LCPLL_CD_SOURCE_FCLK, 0);
 865
 866         if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
 867                          LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 868                 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
 869
 870         snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
 871                         cdclk_config->voltage_level);
 872
 873         intel_de_write(dev_priv, CDCLK_FREQ,
 874                        DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 875
 876         intel_update_cdclk(dev_priv);
 877 }
 878
 879 static int skl_calc_cdclk(int min_cdclk, int vco)
 880 {
 881         if (vco == 8640000) {
 882                 if (min_cdclk > 540000)
 883                         return 617143;
 884                 else if (min_cdclk > 432000)
 885                         return 540000;
 886                 else if (min_cdclk > 308571)
 887                         return 432000;
 888                 else
 889                         return 308571;
 890         } else {
 891                 if (min_cdclk > 540000)
 892                         return 675000;
 893                 else if (min_cdclk > 450000)
 894                         return 540000;
 895                 else if (min_cdclk > 337500)
 896                         return 450000;
 897                 else
 898                         return 337500;
 899         }
 900 }
 901
 902 static u8 skl_calc_voltage_level(int cdclk)
 903 {
 904         if (cdclk > 540000)
 905                 return 3;
 906         else if (cdclk > 450000)
 907                 return 2;
 908         else if (cdclk > 337500)
 909                 return 1;
 910         else
 911                 return 0;
 912 }
 913
 914 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 915                              struct intel_cdclk_config *cdclk_config)
 916 {
 917         u32 val;
 918
 919         cdclk_config->ref = 24000;
 920         cdclk_config->vco = 0;
 921
 922         val = intel_de_read(dev_priv, LCPLL1_CTL);
 923         if ((val & LCPLL_PLL_ENABLE) == 0)
 924                 return;
 925
 926         if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
 927                 return;
 928
 929         val = intel_de_read(dev_priv, DPLL_CTRL1);
 930
 931         if (drm_WARN_ON(&dev_priv->drm,
 932                         (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 933                                 DPLL_CTRL1_SSC(SKL_DPLL0) |
 934                                 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 935                         DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 936                 return;
 937
 938         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 939         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 940         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 941         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 942         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 943                 cdclk_config->vco = 8100000;
 944                 break;
 945         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 946         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 947                 cdclk_config->vco = 8640000;
 948                 break;
 949         default:
 950                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 951                 break;
 952         }
 953 }
 954
 955 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 956                           struct intel_cdclk_config *cdclk_config)
 957 {
 958         u32 cdctl;
 959
 960         skl_dpll0_update(dev_priv, cdclk_config);
 961
 962         cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
 963
 964         if (cdclk_config->vco == 0)
 965                 goto out;
 966
 967         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
 968
 969         if (cdclk_config->vco == 8640000) {
 970                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 971                 case CDCLK_FREQ_450_432:
 972                         cdclk_config->cdclk = 432000;
 973                         break;
 974                 case CDCLK_FREQ_337_308:
 975                         cdclk_config->cdclk = 308571;
 976                         break;
 977                 case CDCLK_FREQ_540:
 978                         cdclk_config->cdclk = 540000;
 979                         break;
 980                 case CDCLK_FREQ_675_617:
 981                         cdclk_config->cdclk = 617143;
 982                         break;
 983                 default:
 984                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 985                         break;
 986                 }
 987         } else {
 988                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 989                 case CDCLK_FREQ_450_432:
 990                         cdclk_config->cdclk = 450000;
 991                         break;
 992                 case CDCLK_FREQ_337_308:
 993                         cdclk_config->cdclk = 337500;
 994                         break;
 995                 case CDCLK_FREQ_540:
 996                         cdclk_config->cdclk = 540000;
 997                         break;
 998                 case CDCLK_FREQ_675_617:
 999                         cdclk_config->cdclk = 675000;
1000                         break;
1001                 default:
1002                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1003                         break;
1004                 }
1005         }
1006
1007  out:
1008         /*
1009          * Can't read this out :( Let's assume it's
1010          * at least what the CDCLK frequency requires.
1011          */
1012         cdclk_config->voltage_level =
1013                 skl_calc_voltage_level(cdclk_config->cdclk);
1014 }
1015
1016 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1017 static int skl_cdclk_decimal(int cdclk)
1018 {
1019         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1020 }
1021
1022 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
1023                                         int vco)
1024 {
1025         bool changed = dev_priv->skl_preferred_vco_freq != vco;
1026
1027         dev_priv->skl_preferred_vco_freq = vco;
1028
1029         if (changed)
1030                 intel_update_max_cdclk(dev_priv);
1031 }
1032
1033 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
1034 {
1035         drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
1036
1037         /*
1038          * We always enable DPLL0 with the lowest link rate possible, but still
1039          * taking into account the VCO required to operate the eDP panel at the
1040          * desired frequency. The usual DP link rates operate with a VCO of
1041          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1042          * The modeset code is responsible for the selection of the exact link
1043          * rate later on, with the constraint of choosing a frequency that
1044          * works with vco.
1045          */
1046         if (vco == 8640000)
1047                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1048         else
1049                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1050 }
1051
1052 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
1053 {
1054         intel_de_rmw(dev_priv, DPLL_CTRL1,
1055                      DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1056                      DPLL_CTRL1_SSC(SKL_DPLL0) |
1057                      DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1058                      DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1059                      skl_dpll0_link_rate(dev_priv, vco));
1060         intel_de_posting_read(dev_priv, DPLL_CTRL1);
1061
1062         intel_de_rmw(dev_priv, LCPLL1_CTL,
1063                      0, LCPLL_PLL_ENABLE);
1064
1065         if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1066                 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
1067
1068         dev_priv->display.cdclk.hw.vco = vco;
1069
1070         /* We'll want to keep using the current vco from now on. */
1071         skl_set_preferred_cdclk_vco(dev_priv, vco);
1072 }
1073
1074 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1075 {
1076         intel_de_rmw(dev_priv, LCPLL1_CTL,
1077                      LCPLL_PLL_ENABLE, 0);
1078
1079         if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1080                 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1081
1082         dev_priv->display.cdclk.hw.vco = 0;
1083 }
1084
1085 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
1086                               int cdclk, int vco)
1087 {
1088         switch (cdclk) {
1089         default:
1090                 drm_WARN_ON(&dev_priv->drm,
1091                             cdclk != dev_priv->display.cdclk.hw.bypass);
1092                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1093                 fallthrough;
1094         case 308571:
1095         case 337500:
1096                 return CDCLK_FREQ_337_308;
1097         case 450000:
1098         case 432000:
1099                 return CDCLK_FREQ_450_432;
1100         case 540000:
1101                 return CDCLK_FREQ_540;
1102         case 617143:
1103         case 675000:
1104                 return CDCLK_FREQ_675_617;
1105         }
1106 }
1107
1108 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1109                           const struct intel_cdclk_config *cdclk_config,
1110                           enum pipe pipe)
1111 {
1112         int cdclk = cdclk_config->cdclk;
1113         int vco = cdclk_config->vco;
1114         u32 freq_select, cdclk_ctl;
1115         int ret;
1116
1117         /*
1118          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1119          * unsupported on SKL. In theory this should never happen since only
1120          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1121          * supported on SKL either, see the above WA. WARN whenever trying to
1122          * use the corresponding VCO freq as that always leads to using the
1123          * minimum 308MHz CDCLK.
1124          */
1125         drm_WARN_ON_ONCE(&dev_priv->drm,
1126                          IS_SKYLAKE(dev_priv) && vco == 8640000);
1127
1128         ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1129                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1130                                 SKL_CDCLK_READY_FOR_CHANGE,
1131                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1132         if (ret) {
1133                 drm_err(&dev_priv->drm,
1134                         "Failed to inform PCU about cdclk change (%d)\n", ret);
1135                 return;
1136         }
1137
1138         freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1139
1140         if (dev_priv->display.cdclk.hw.vco != 0 &&
1141             dev_priv->display.cdclk.hw.vco != vco)
1142                 skl_dpll0_disable(dev_priv);
1143
1144         cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1145
1146         if (dev_priv->display.cdclk.hw.vco != vco) {
1147                 /* Wa Display #1183: skl,kbl,cfl */
1148                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1149                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1150                 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1151         }
1152
1153         /* Wa Display #1183: skl,kbl,cfl */
1154         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1155         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1156         intel_de_posting_read(dev_priv, CDCLK_CTL);
1157
1158         if (dev_priv->display.cdclk.hw.vco != vco)
1159                 skl_dpll0_enable(dev_priv, vco);
1160
1161         /* Wa Display #1183: skl,kbl,cfl */
1162         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1163         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1164
1165         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1166         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1167
1168         /* Wa Display #1183: skl,kbl,cfl */
1169         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1170         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1171         intel_de_posting_read(dev_priv, CDCLK_CTL);
1172
1173         /* inform PCU of the change */
1174         snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1175                         cdclk_config->voltage_level);
1176
1177         intel_update_cdclk(dev_priv);
1178 }
1179
1180 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1181 {
1182         u32 cdctl, expected;
1183
1184         /*
1185          * check if the pre-os initialized the display
1186          * There is SWF18 scratchpad register defined which is set by the
1187          * pre-os which can be used by the OS drivers to check the status
1188          */
1189         if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1190                 goto sanitize;
1191
1192         intel_update_cdclk(dev_priv);
1193         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1194
1195         /* Is PLL enabled and locked ? */
1196         if (dev_priv->display.cdclk.hw.vco == 0 ||
1197             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1198                 goto sanitize;
1199
1200         /* DPLL okay; verify the cdclock
1201          *
1202          * Noticed in some instances that the freq selection is correct but
1203          * decimal part is programmed wrong from BIOS where pre-os does not
1204          * enable display. Verify the same as well.
1205          */
1206         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1207         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1208                 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
1209         if (cdctl == expected)
1210                 /* All well; nothing to sanitize */
1211                 return;
1212
1213 sanitize:
1214         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1215
1216         /* force cdclk programming */
1217         dev_priv->display.cdclk.hw.cdclk = 0;
1218         /* force full PLL disable + enable */
1219         dev_priv->display.cdclk.hw.vco = ~0;
1220 }
1221
1222 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1223 {
1224         struct intel_cdclk_config cdclk_config;
1225
1226         skl_sanitize_cdclk(dev_priv);
1227
1228         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
1229             dev_priv->display.cdclk.hw.vco != 0) {
1230                 /*
1231                  * Use the current vco as our initial
1232                  * guess as to what the preferred vco is.
1233                  */
1234                 if (dev_priv->skl_preferred_vco_freq == 0)
1235                         skl_set_preferred_cdclk_vco(dev_priv,
1236                                                     dev_priv->display.cdclk.hw.vco);
1237                 return;
1238         }
1239
1240         cdclk_config = dev_priv->display.cdclk.hw;
1241
1242         cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1243         if (cdclk_config.vco == 0)
1244                 cdclk_config.vco = 8100000;
1245         cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1246         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1247
1248         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1249 }
1250
1251 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1252 {
1253         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
1254
1255         cdclk_config.cdclk = cdclk_config.bypass;
1256         cdclk_config.vco = 0;
1257         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1258
1259         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1260 }
1261
1262 struct intel_cdclk_vals {
1263         u32 cdclk;
1264         u16 refclk;
1265         u16 waveform;
1266         u8 ratio;
1267 };
1268
1269 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1270         { .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1271         { .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1272         { .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1273         { .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1274         { .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1275         {}
1276 };
1277
1278 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1279         { .refclk = 19200, .cdclk =  79200, .ratio = 33 },
1280         { .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1281         { .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1282         {}
1283 };
1284
1285 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1286         { .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1287         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1288         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1289         { .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1290         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1291         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1292
1293         { .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1294         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1295         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1296         { .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1297         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1298         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1299
1300         { .refclk = 38400, .cdclk = 172800, .ratio =  9 },
1301         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1302         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1303         { .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1304         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1305         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1306         {}
1307 };
1308
1309 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1310         { .refclk = 19200, .cdclk = 172800, .ratio =  36 },
1311         { .refclk = 19200, .cdclk = 192000, .ratio =  40 },
1312         { .refclk = 19200, .cdclk = 307200, .ratio =  64 },
1313         { .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1314         { .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1315         { .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1316
1317         { .refclk = 24000, .cdclk = 180000, .ratio =  30 },
1318         { .refclk = 24000, .cdclk = 192000, .ratio =  32 },
1319         { .refclk = 24000, .cdclk = 312000, .ratio =  52 },
1320         { .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1321         { .refclk = 24000, .cdclk = 552000, .ratio =  92 },
1322         { .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1323
1324         { .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1325         { .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1326         { .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1327         { .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1328         { .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1329         { .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1330         {}
1331 };
1332
1333 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1334         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1335         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1336         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1337
1338         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1339         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1340         { .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1341
1342         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1343         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1344         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1345         {}
1346 };
1347
1348 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1349         { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1350         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1351         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1352         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1353         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1354
1355         { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1356         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1357         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1358         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1359         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1360
1361         { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1362         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1363         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1364         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1365         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1366         {}
1367 };
1368
1369 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1370         { .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1371         { .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1372         { .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1373         { .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1374         { .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1375         { .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1376
1377         { .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1378         { .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1379         { .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1380         { .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1381         { .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1382         { .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1383
1384         { .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1385         { .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1386         { .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1387         { .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1388         { .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1389         { .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1390         {}
1391 };
1392
1393 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1394         { .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1395         { .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1396         { .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1397         { .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1398         { .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1399         { .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1400         { .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1401         { .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1402         { .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1403         { .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1404         { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1405         { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1406         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1407         {}
1408 };
1409
1410 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1411         { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1412         { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1413         { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1414         { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1415         { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1416         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1417         {}
1418 };
1419
1420 static const struct intel_cdclk_vals lnl_cdclk_table[] = {
1421         { .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1422         { .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1423         { .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1424         { .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1425         { .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1426         { .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1427         { .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1428         { .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1429         { .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1430         { .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1431         { .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1432         { .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1433         { .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1434         { .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1435         { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1436         { .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1437         { .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1438         { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1439         { .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1440         { .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1441         { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1442         {}
1443 };
1444
1445 static const int cdclk_squash_len = 16;
1446
1447 static int cdclk_squash_divider(u16 waveform)
1448 {
1449         return hweight16(waveform ?: 0xffff);
1450 }
1451
1452 static int cdclk_divider(int cdclk, int vco, u16 waveform)
1453 {
1454         /* 2 * cd2x divider */
1455         return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1456                                  cdclk * cdclk_squash_len);
1457 }
1458
1459 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1460 {
1461         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1462         int i;
1463
1464         for (i = 0; table[i].refclk; i++)
1465                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1466                     table[i].cdclk >= min_cdclk)
1467                         return table[i].cdclk;
1468
1469         drm_WARN(&dev_priv->drm, 1,
1470                  "Cannot satisfy minimum cdclk %d with refclk %u\n",
1471                  min_cdclk, dev_priv->display.cdclk.hw.ref);
1472         return 0;
1473 }
1474
1475 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1476 {
1477         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1478         int i;
1479
1480         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1481                 return 0;
1482
1483         for (i = 0; table[i].refclk; i++)
1484                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1485                     table[i].cdclk == cdclk)
1486                         return dev_priv->display.cdclk.hw.ref * table[i].ratio;
1487
1488         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1489                  cdclk, dev_priv->display.cdclk.hw.ref);
1490         return 0;
1491 }
1492
1493 static u8 bxt_calc_voltage_level(int cdclk)
1494 {
1495         return DIV_ROUND_UP(cdclk, 25000);
1496 }
1497
1498 static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1499                              const int voltage_level_max_cdclk[])
1500 {
1501         int voltage_level;
1502
1503         for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1504                 if (cdclk <= voltage_level_max_cdclk[voltage_level])
1505                         return voltage_level;
1506         }
1507
1508         MISSING_CASE(cdclk);
1509         return num_voltage_levels - 1;
1510 }
1511
1512 static u8 icl_calc_voltage_level(int cdclk)
1513 {
1514         static const int icl_voltage_level_max_cdclk[] = {
1515                 [0] = 312000,
1516                 [1] = 556800,
1517                 [2] = 652800,
1518         };
1519
1520         return calc_voltage_level(cdclk,
1521                                   ARRAY_SIZE(icl_voltage_level_max_cdclk),
1522                                   icl_voltage_level_max_cdclk);
1523 }
1524
1525 static u8 ehl_calc_voltage_level(int cdclk)
1526 {
1527         static const int ehl_voltage_level_max_cdclk[] = {
1528                 [0] = 180000,
1529                 [1] = 312000,
1530                 [2] = 326400,
1531                 /*
1532                  * Bspec lists the limit as 556.8 MHz, but some JSL
1533                  * development boards (at least) boot with 652.8 MHz
1534                  */
1535                 [3] = 652800,
1536         };
1537
1538         return calc_voltage_level(cdclk,
1539                                   ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1540                                   ehl_voltage_level_max_cdclk);
1541 }
1542
1543 static u8 tgl_calc_voltage_level(int cdclk)
1544 {
1545         static const int tgl_voltage_level_max_cdclk[] = {
1546                 [0] = 312000,
1547                 [1] = 326400,
1548                 [2] = 556800,
1549                 [3] = 652800,
1550         };
1551
1552         return calc_voltage_level(cdclk,
1553                                   ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1554                                   tgl_voltage_level_max_cdclk);
1555 }
1556
1557 static u8 rplu_calc_voltage_level(int cdclk)
1558 {
1559         static const int rplu_voltage_level_max_cdclk[] = {
1560                 [0] = 312000,
1561                 [1] = 480000,
1562                 [2] = 556800,
1563                 [3] = 652800,
1564         };
1565
1566         return calc_voltage_level(cdclk,
1567                                   ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1568                                   rplu_voltage_level_max_cdclk);
1569 }
1570
1571 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1572                                struct intel_cdclk_config *cdclk_config)
1573 {
1574         u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1575
1576         switch (dssm) {
1577         default:
1578                 MISSING_CASE(dssm);
1579                 fallthrough;
1580         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1581                 cdclk_config->ref = 24000;
1582                 break;
1583         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1584                 cdclk_config->ref = 19200;
1585                 break;
1586         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1587                 cdclk_config->ref = 38400;
1588                 break;
1589         }
1590 }
1591
1592 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1593                                struct intel_cdclk_config *cdclk_config)
1594 {
1595         u32 val, ratio;
1596
1597         if (IS_DG2(dev_priv))
1598                 cdclk_config->ref = 38400;
1599         else if (DISPLAY_VER(dev_priv) >= 11)
1600                 icl_readout_refclk(dev_priv, cdclk_config);
1601         else
1602                 cdclk_config->ref = 19200;
1603
1604         val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1605         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1606             (val & BXT_DE_PLL_LOCK) == 0) {
1607                 /*
1608                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1609                  * setting it to zero is a way to signal that.
1610                  */
1611                 cdclk_config->vco = 0;
1612                 return;
1613         }
1614
1615         /*
1616          * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1617          * gen9lp had it in a separate PLL control register.
1618          */
1619         if (DISPLAY_VER(dev_priv) >= 11)
1620                 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1621         else
1622                 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1623
1624         cdclk_config->vco = ratio * cdclk_config->ref;
1625 }
1626
1627 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1628                           struct intel_cdclk_config *cdclk_config)
1629 {
1630         u32 squash_ctl = 0;
1631         u32 divider;
1632         int div;
1633
1634         bxt_de_pll_readout(dev_priv, cdclk_config);
1635
1636         if (DISPLAY_VER(dev_priv) >= 12)
1637                 cdclk_config->bypass = cdclk_config->ref / 2;
1638         else if (DISPLAY_VER(dev_priv) >= 11)
1639                 cdclk_config->bypass = 50000;
1640         else
1641                 cdclk_config->bypass = cdclk_config->ref;
1642
1643         if (cdclk_config->vco == 0) {
1644                 cdclk_config->cdclk = cdclk_config->bypass;
1645                 goto out;
1646         }
1647
1648         divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1649
1650         switch (divider) {
1651         case BXT_CDCLK_CD2X_DIV_SEL_1:
1652                 div = 2;
1653                 break;
1654         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1655                 div = 3;
1656                 break;
1657         case BXT_CDCLK_CD2X_DIV_SEL_2:
1658                 div = 4;
1659                 break;
1660         case BXT_CDCLK_CD2X_DIV_SEL_4:
1661                 div = 8;
1662                 break;
1663         default:
1664                 MISSING_CASE(divider);
1665                 return;
1666         }
1667
1668         if (HAS_CDCLK_SQUASH(dev_priv))
1669                 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
1670
1671         if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1672                 u16 waveform;
1673                 int size;
1674
1675                 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1676                 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1677
1678                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1679                                                         cdclk_config->vco, size * div);
1680         } else {
1681                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1682         }
1683
1684  out:
1685         /*
1686          * Can't read this out :( Let's assume it's
1687          * at least what the CDCLK frequency requires.
1688          */
1689         cdclk_config->voltage_level =
1690                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
1691 }
1692
1693 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1694 {
1695         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1696
1697         /* Timeout 200us */
1698         if (intel_de_wait_for_clear(dev_priv,
1699                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1700                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1701
1702         dev_priv->display.cdclk.hw.vco = 0;
1703 }
1704
1705 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1706 {
1707         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1708
1709         intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
1710                      BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1711
1712         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1713
1714         /* Timeout 200us */
1715         if (intel_de_wait_for_set(dev_priv,
1716                                   BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1717                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1718
1719         dev_priv->display.cdclk.hw.vco = vco;
1720 }
1721
1722 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1723 {
1724         intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
1725                      BXT_DE_PLL_PLL_ENABLE, 0);
1726
1727         /* Timeout 200us */
1728         if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1729                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1730
1731         dev_priv->display.cdclk.hw.vco = 0;
1732 }
1733
1734 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1735 {
1736         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1737         u32 val;
1738
1739         val = ICL_CDCLK_PLL_RATIO(ratio);
1740         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1741
1742         val |= BXT_DE_PLL_PLL_ENABLE;
1743         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1744
1745         /* Timeout 200us */
1746         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1747                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1748
1749         dev_priv->display.cdclk.hw.vco = vco;
1750 }
1751
1752 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
1753 {
1754         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1755         u32 val;
1756
1757         /* Write PLL ratio without disabling */
1758         val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1759         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1760
1761         /* Submit freq change request */
1762         val |= BXT_DE_PLL_FREQ_REQ;
1763         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1764
1765         /* Timeout 200us */
1766         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
1767                                   BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1768                 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
1769
1770         val &= ~BXT_DE_PLL_FREQ_REQ;
1771         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1772
1773         dev_priv->display.cdclk.hw.vco = vco;
1774 }
1775
1776 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1777 {
1778         if (DISPLAY_VER(dev_priv) >= 12) {
1779                 if (pipe == INVALID_PIPE)
1780                         return TGL_CDCLK_CD2X_PIPE_NONE;
1781                 else
1782                         return TGL_CDCLK_CD2X_PIPE(pipe);
1783         } else if (DISPLAY_VER(dev_priv) >= 11) {
1784                 if (pipe == INVALID_PIPE)
1785                         return ICL_CDCLK_CD2X_PIPE_NONE;
1786                 else
1787                         return ICL_CDCLK_CD2X_PIPE(pipe);
1788         } else {
1789                 if (pipe == INVALID_PIPE)
1790                         return BXT_CDCLK_CD2X_PIPE_NONE;
1791                 else
1792                         return BXT_CDCLK_CD2X_PIPE(pipe);
1793         }
1794 }
1795
1796 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
1797                                   int cdclk, int vco, u16 waveform)
1798 {
1799         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1800         switch (cdclk_divider(cdclk, vco, waveform)) {
1801         default:
1802                 drm_WARN_ON(&dev_priv->drm,
1803                             cdclk != dev_priv->display.cdclk.hw.bypass);
1804                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1805                 fallthrough;
1806         case 2:
1807                 return BXT_CDCLK_CD2X_DIV_SEL_1;
1808         case 3:
1809                 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1810         case 4:
1811                 return BXT_CDCLK_CD2X_DIV_SEL_2;
1812         case 8:
1813                 return BXT_CDCLK_CD2X_DIV_SEL_4;
1814         }
1815 }
1816
1817 static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
1818                                  int cdclk)
1819 {
1820         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1821         int i;
1822
1823         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1824                 return 0;
1825
1826         for (i = 0; table[i].refclk; i++)
1827                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1828                     table[i].cdclk == cdclk)
1829                         return table[i].waveform;
1830
1831         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1832                  cdclk, dev_priv->display.cdclk.hw.ref);
1833
1834         return 0xffff;
1835 }
1836
1837 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1838 {
1839         if (i915->display.cdclk.hw.vco != 0 &&
1840             i915->display.cdclk.hw.vco != vco)
1841                 icl_cdclk_pll_disable(i915);
1842
1843         if (i915->display.cdclk.hw.vco != vco)
1844                 icl_cdclk_pll_enable(i915, vco);
1845 }
1846
1847 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1848 {
1849         if (i915->display.cdclk.hw.vco != 0 &&
1850             i915->display.cdclk.hw.vco != vco)
1851                 bxt_de_pll_disable(i915);
1852
1853         if (i915->display.cdclk.hw.vco != vco)
1854                 bxt_de_pll_enable(i915, vco);
1855 }
1856
1857 static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
1858                                      u16 waveform)
1859 {
1860         u32 squash_ctl = 0;
1861
1862         if (waveform)
1863                 squash_ctl = CDCLK_SQUASH_ENABLE |
1864                              CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1865
1866         intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
1867 }
1868
1869 static bool cdclk_pll_is_unknown(unsigned int vco)
1870 {
1871         /*
1872          * Ensure driver does not take the crawl path for the
1873          * case when the vco is set to ~0 in the
1874          * sanitize path.
1875          */
1876         return vco == ~0;
1877 }
1878
1879 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
1880                                                     const struct intel_cdclk_config *old_cdclk_config,
1881                                                     const struct intel_cdclk_config *new_cdclk_config,
1882                                                     struct intel_cdclk_config *mid_cdclk_config)
1883 {
1884         u16 old_waveform, new_waveform, mid_waveform;
1885         int old_div, new_div, mid_div;
1886
1887         /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1888         if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1889                 return false;
1890
1891         /* Return if both Squash and Crawl are not present */
1892         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
1893                 return false;
1894
1895         old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
1896         new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
1897
1898         /* Return if Squash only or Crawl only is the desired action */
1899         if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
1900             old_cdclk_config->vco == new_cdclk_config->vco ||
1901             old_waveform == new_waveform)
1902                 return false;
1903
1904         old_div = cdclk_divider(old_cdclk_config->cdclk,
1905                                 old_cdclk_config->vco, old_waveform);
1906         new_div = cdclk_divider(new_cdclk_config->cdclk,
1907                                 new_cdclk_config->vco, new_waveform);
1908
1909         /*
1910          * Should not happen currently. We might need more midpoint
1911          * transitions if we need to also change the cd2x divider.
1912          */
1913         if (drm_WARN_ON(&i915->drm, old_div != new_div))
1914                 return false;
1915
1916         *mid_cdclk_config = *new_cdclk_config;
1917
1918         /*
1919          * Populate the mid_cdclk_config accordingly.
1920          * - If moving to a higher cdclk, the desired action is squashing.
1921          * The mid cdclk config should have the new (squash) waveform.
1922          * - If moving to a lower cdclk, the desired action is crawling.
1923          * The mid cdclk config should have the new vco.
1924          */
1925
1926         if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
1927                 mid_cdclk_config->vco = old_cdclk_config->vco;
1928                 mid_div = old_div;
1929                 mid_waveform = new_waveform;
1930         } else {
1931                 mid_cdclk_config->vco = new_cdclk_config->vco;
1932                 mid_div = new_div;
1933                 mid_waveform = old_waveform;
1934         }
1935
1936         mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
1937                                                     mid_cdclk_config->vco,
1938                                                     cdclk_squash_len * mid_div);
1939
1940         /* make sure the mid clock came out sane */
1941
1942         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
1943                     min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
1944         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
1945                     i915->display.cdclk.max_cdclk_freq);
1946         drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
1947                     mid_waveform);
1948
1949         return true;
1950 }
1951
1952 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
1953 {
1954         return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
1955                 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
1956                 IS_DG2(dev_priv)) &&
1957                 dev_priv->display.cdclk.hw.vco > 0;
1958 }
1959
1960 static u32 bxt_cdclk_ctl(struct drm_i915_private *i915,
1961                          const struct intel_cdclk_config *cdclk_config,
1962                          enum pipe pipe)
1963 {
1964         int cdclk = cdclk_config->cdclk;
1965         int vco = cdclk_config->vco;
1966         u16 waveform;
1967         u32 val;
1968
1969         waveform = cdclk_squash_waveform(i915, cdclk);
1970
1971         val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) |
1972                 bxt_cdclk_cd2x_pipe(i915, pipe);
1973
1974         /*
1975          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1976          * enable otherwise.
1977          */
1978         if ((IS_GEMINILAKE(i915) || IS_BROXTON(i915)) &&
1979             cdclk >= 500000)
1980                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1981
1982         if (DISPLAY_VER(i915) >= 20)
1983                 val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
1984         else
1985                 val |= skl_cdclk_decimal(cdclk);
1986
1987         return val;
1988 }
1989
1990 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
1991                            const struct intel_cdclk_config *cdclk_config,
1992                            enum pipe pipe)
1993 {
1994         int cdclk = cdclk_config->cdclk;
1995         int vco = cdclk_config->vco;
1996         u16 waveform;
1997
1998         if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
1999             !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
2000                 if (dev_priv->display.cdclk.hw.vco != vco)
2001                         adlp_cdclk_pll_crawl(dev_priv, vco);
2002         } else if (DISPLAY_VER(dev_priv) >= 11) {
2003                 /* wa_15010685871: dg2, mtl */
2004                 if (pll_enable_wa_needed(dev_priv))
2005                         dg2_cdclk_squash_program(dev_priv, 0);
2006
2007                 icl_cdclk_pll_update(dev_priv, vco);
2008         } else
2009                 bxt_cdclk_pll_update(dev_priv, vco);
2010
2011         waveform = cdclk_squash_waveform(dev_priv, cdclk);
2012
2013         if (HAS_CDCLK_SQUASH(dev_priv))
2014                 dg2_cdclk_squash_program(dev_priv, waveform);
2015
2016         intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe));
2017
2018         if (pipe != INVALID_PIPE)
2019                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
2020 }
2021
2022 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
2023                           const struct intel_cdclk_config *cdclk_config,
2024                           enum pipe pipe)
2025 {
2026         struct intel_cdclk_config mid_cdclk_config;
2027         int cdclk = cdclk_config->cdclk;
2028         int ret = 0;
2029
2030         /*
2031          * Inform power controller of upcoming frequency change.
2032          * Display versions 14 and beyond do not follow the PUnit
2033          * mailbox communication, skip
2034          * this step.
2035          */
2036         if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
2037                 /* NOOP */;
2038         else if (DISPLAY_VER(dev_priv) >= 11)
2039                 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2040                                         SKL_CDCLK_PREPARE_FOR_CHANGE,
2041                                         SKL_CDCLK_READY_FOR_CHANGE,
2042                                         SKL_CDCLK_READY_FOR_CHANGE, 3);
2043         else
2044                 /*
2045                  * BSpec requires us to wait up to 150usec, but that leads to
2046                  * timeouts; the 2ms used here is based on experiment.
2047                  */
2048                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2049                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
2050                                               0x80000000, 150, 2);
2051
2052         if (ret) {
2053                 drm_err(&dev_priv->drm,
2054                         "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2055                         ret, cdclk);
2056                 return;
2057         }
2058
2059         if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
2060                                                     cdclk_config, &mid_cdclk_config)) {
2061                 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
2062                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2063         } else {
2064                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
2065         }
2066
2067         if (DISPLAY_VER(dev_priv) >= 14)
2068                 /*
2069                  * NOOP - No Pcode communication needed for
2070                  * Display versions 14 and beyond
2071                  */;
2072         else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
2073                 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
2074                                       cdclk_config->voltage_level);
2075         if (DISPLAY_VER(dev_priv) < 11) {
2076                 /*
2077                  * The timeout isn't specified, the 2ms used here is based on
2078                  * experiment.
2079                  * FIXME: Waiting for the request completion could be delayed
2080                  * until the next PCODE request based on BSpec.
2081                  */
2082                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
2083                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
2084                                               cdclk_config->voltage_level,
2085                                               150, 2);
2086         }
2087         if (ret) {
2088                 drm_err(&dev_priv->drm,
2089                         "PCode CDCLK freq set failed, (err %d, freq %d)\n",
2090                         ret, cdclk);
2091                 return;
2092         }
2093
2094         intel_update_cdclk(dev_priv);
2095
2096         if (DISPLAY_VER(dev_priv) >= 11)
2097                 /*
2098                  * Can't read out the voltage level :(
2099                  * Let's just assume everything is as expected.
2100                  */
2101                 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
2102 }
2103
2104 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
2105 {
2106         u32 cdctl, expected;
2107         int cdclk, vco;
2108
2109         intel_update_cdclk(dev_priv);
2110         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
2111
2112         if (dev_priv->display.cdclk.hw.vco == 0 ||
2113             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
2114                 goto sanitize;
2115
2116         /* Make sure this is a legal cdclk value for the platform */
2117         cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
2118         if (cdclk != dev_priv->display.cdclk.hw.cdclk)
2119                 goto sanitize;
2120
2121         /* Make sure the VCO is correct for the cdclk */
2122         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2123         if (vco != dev_priv->display.cdclk.hw.vco)
2124                 goto sanitize;
2125
2126         /*
2127          * Some BIOS versions leave an incorrect decimal frequency value and
2128          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2129          * so sanitize this register.
2130          */
2131         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
2132         expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);
2133
2134         /*
2135          * Let's ignore the pipe field, since BIOS could have configured the
2136          * dividers both synching to an active pipe, or asynchronously
2137          * (PIPE_NONE).
2138          */
2139         cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2140         expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2141
2142         if (cdctl == expected)
2143                 /* All well; nothing to sanitize */
2144                 return;
2145
2146 sanitize:
2147         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
2148
2149         /* force cdclk programming */
2150         dev_priv->display.cdclk.hw.cdclk = 0;
2151
2152         /* force full PLL disable + enable */
2153         dev_priv->display.cdclk.hw.vco = ~0;
2154 }
2155
2156 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
2157 {
2158         struct intel_cdclk_config cdclk_config;
2159
2160         bxt_sanitize_cdclk(dev_priv);
2161
2162         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
2163             dev_priv->display.cdclk.hw.vco != 0)
2164                 return;
2165
2166         cdclk_config = dev_priv->display.cdclk.hw;
2167
2168         /*
2169          * FIXME:
2170          * - The initial CDCLK needs to be read from VBT.
2171          *   Need to make this change after VBT has changes for BXT.
2172          */
2173         cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
2174         cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
2175         cdclk_config.voltage_level =
2176                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2177
2178         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2179 }
2180
2181 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
2182 {
2183         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
2184
2185         cdclk_config.cdclk = cdclk_config.bypass;
2186         cdclk_config.vco = 0;
2187         cdclk_config.voltage_level =
2188                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2189
2190         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2191 }
2192
2193 /**
2194  * intel_cdclk_init_hw - Initialize CDCLK hardware
2195  * @i915: i915 device
2196  *
2197  * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2198  * sanitizing the state of the hardware if needed. This is generally done only
2199  * during the display core initialization sequence, after which the DMC will
2200  * take care of turning CDCLK off/on as needed.
2201  */
2202 void intel_cdclk_init_hw(struct drm_i915_private *i915)
2203 {
2204         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2205                 bxt_cdclk_init_hw(i915);
2206         else if (DISPLAY_VER(i915) == 9)
2207                 skl_cdclk_init_hw(i915);
2208 }
2209
2210 /**
2211  * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2212  * @i915: i915 device
2213  *
2214  * Uninitialize CDCLK. This is done only during the display core
2215  * uninitialization sequence.
2216  */
2217 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
2218 {
2219         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2220                 bxt_cdclk_uninit_hw(i915);
2221         else if (DISPLAY_VER(i915) == 9)
2222                 skl_cdclk_uninit_hw(i915);
2223 }
2224
2225 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
2226                                              const struct intel_cdclk_config *a,
2227                                              const struct intel_cdclk_config *b)
2228 {
2229         u16 old_waveform;
2230         u16 new_waveform;
2231
2232         drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
2233
2234         if (a->vco == 0 || b->vco == 0)
2235                 return false;
2236
2237         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
2238                 return false;
2239
2240         old_waveform = cdclk_squash_waveform(i915, a->cdclk);
2241         new_waveform = cdclk_squash_waveform(i915, b->cdclk);
2242
2243         return a->vco != b->vco &&
2244                old_waveform != new_waveform;
2245 }
2246
2247 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
2248                                   const struct intel_cdclk_config *a,
2249                                   const struct intel_cdclk_config *b)
2250 {
2251         int a_div, b_div;
2252
2253         if (!HAS_CDCLK_CRAWL(dev_priv))
2254                 return false;
2255
2256         /*
2257          * The vco and cd2x divider will change independently
2258          * from each, so we disallow cd2x change when crawling.
2259          */
2260         a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2261         b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2262
2263         return a->vco != 0 && b->vco != 0 &&
2264                 a->vco != b->vco &&
2265                 a_div == b_div &&
2266                 a->ref == b->ref;
2267 }
2268
2269 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
2270                                    const struct intel_cdclk_config *a,
2271                                    const struct intel_cdclk_config *b)
2272 {
2273         /*
2274          * FIXME should store a bit more state in intel_cdclk_config
2275          * to differentiate squasher vs. cd2x divider properly. For
2276          * the moment all platforms with squasher use a fixed cd2x
2277          * divider.
2278          */
2279         if (!HAS_CDCLK_SQUASH(dev_priv))
2280                 return false;
2281
2282         return a->cdclk != b->cdclk &&
2283                 a->vco != 0 &&
2284                 a->vco == b->vco &&
2285                 a->ref == b->ref;
2286 }
2287
2288 /**
2289  * intel_cdclk_clock_changed - Check whether the clock changed
2290  * @a: first CDCLK configuration
2291  * @b: second CDCLK configuration
2292  *
2293  * Returns:
2294  * True if CDCLK changed in a way that requires re-programming and
2295  * False otherwise.
2296  */
2297 bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2298                                const struct intel_cdclk_config *b)
2299 {
2300         return a->cdclk != b->cdclk ||
2301                 a->vco != b->vco ||
2302                 a->ref != b->ref;
2303 }
2304
2305 /**
2306  * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2307  *                               configurations requires only a cd2x divider update
2308  * @dev_priv: i915 device
2309  * @a: first CDCLK configuration
2310  * @b: second CDCLK configuration
2311  *
2312  * Returns:
2313  * True if changing between the two CDCLK configurations
2314  * can be done with just a cd2x divider update, false if not.
2315  */
2316 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
2317                                         const struct intel_cdclk_config *a,
2318                                         const struct intel_cdclk_config *b)
2319 {
2320         /* Older hw doesn't have the capability */
2321         if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
2322                 return false;
2323
2324         /*
2325          * FIXME should store a bit more state in intel_cdclk_config
2326          * to differentiate squasher vs. cd2x divider properly. For
2327          * the moment all platforms with squasher use a fixed cd2x
2328          * divider.
2329          */
2330         if (HAS_CDCLK_SQUASH(dev_priv))
2331                 return false;
2332
2333         return a->cdclk != b->cdclk &&
2334                 a->vco != 0 &&
2335                 a->vco == b->vco &&
2336                 a->ref == b->ref;
2337 }
2338
2339 /**
2340  * intel_cdclk_changed - Determine if two CDCLK configurations are different
2341  * @a: first CDCLK configuration
2342  * @b: second CDCLK configuration
2343  *
2344  * Returns:
2345  * True if the CDCLK configurations don't match, false if they do.
2346  */
2347 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2348                                 const struct intel_cdclk_config *b)
2349 {
2350         return intel_cdclk_clock_changed(a, b) ||
2351                 a->voltage_level != b->voltage_level;
2352 }
2353
2354 void intel_cdclk_dump_config(struct drm_i915_private *i915,
2355                              const struct intel_cdclk_config *cdclk_config,
2356                              const char *context)
2357 {
2358         drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2359                     context, cdclk_config->cdclk, cdclk_config->vco,
2360                     cdclk_config->ref, cdclk_config->bypass,
2361                     cdclk_config->voltage_level);
2362 }
2363
2364 static void intel_pcode_notify(struct drm_i915_private *i915,
2365                                u8 voltage_level,
2366                                u8 active_pipe_count,
2367                                u16 cdclk,
2368                                bool cdclk_update_valid,
2369                                bool pipe_count_update_valid)
2370 {
2371         int ret;
2372         u32 update_mask = 0;
2373
2374         if (!IS_DG2(i915))
2375                 return;
2376
2377         update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2378
2379         if (cdclk_update_valid)
2380                 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2381
2382         if (pipe_count_update_valid)
2383                 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2384
2385         ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2386                                 SKL_CDCLK_PREPARE_FOR_CHANGE |
2387                                 update_mask,
2388                                 SKL_CDCLK_READY_FOR_CHANGE,
2389                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
2390         if (ret)
2391                 drm_err(&i915->drm,
2392                         "Failed to inform PCU about display config (err %d)\n",
2393                         ret);
2394 }
2395
2396 /**
2397  * intel_set_cdclk - Push the CDCLK configuration to the hardware
2398  * @dev_priv: i915 device
2399  * @cdclk_config: new CDCLK configuration
2400  * @pipe: pipe with which to synchronize the update
2401  *
2402  * Program the hardware based on the passed in CDCLK state,
2403  * if necessary.
2404  */
2405 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2406                             const struct intel_cdclk_config *cdclk_config,
2407                             enum pipe pipe)
2408 {
2409         struct intel_encoder *encoder;
2410
2411         if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
2412                 return;
2413
2414         if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
2415                 return;
2416
2417         intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
2418
2419         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2420                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2421
2422                 intel_psr_pause(intel_dp);
2423         }
2424
2425         intel_audio_cdclk_change_pre(dev_priv);
2426
2427         /*
2428          * Lock aux/gmbus while we change cdclk in case those
2429          * functions use cdclk. Not all platforms/ports do,
2430          * but we'll lock them all for simplicity.
2431          */
2432         mutex_lock(&dev_priv->display.gmbus.mutex);
2433         for_each_intel_dp(&dev_priv->drm, encoder) {
2434                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2435
2436                 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2437                                      &dev_priv->display.gmbus.mutex);
2438         }
2439
2440         intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
2441
2442         for_each_intel_dp(&dev_priv->drm, encoder) {
2443                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2444
2445                 mutex_unlock(&intel_dp->aux.hw_mutex);
2446         }
2447         mutex_unlock(&dev_priv->display.gmbus.mutex);
2448
2449         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2450                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2451
2452                 intel_psr_resume(intel_dp);
2453         }
2454
2455         intel_audio_cdclk_change_post(dev_priv);
2456
2457         if (drm_WARN(&dev_priv->drm,
2458                      intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
2459                      "cdclk state doesn't match!\n")) {
2460                 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
2461                 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
2462         }
2463 }
2464
2465 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2466 {
2467         struct drm_i915_private *i915 = to_i915(state->base.dev);
2468         const struct intel_cdclk_state *old_cdclk_state =
2469                 intel_atomic_get_old_cdclk_state(state);
2470         const struct intel_cdclk_state *new_cdclk_state =
2471                 intel_atomic_get_new_cdclk_state(state);
2472         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2473         bool change_cdclk, update_pipe_count;
2474
2475         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2476                                  &new_cdclk_state->actual) &&
2477                                  new_cdclk_state->active_pipes ==
2478                                  old_cdclk_state->active_pipes)
2479                 return;
2480
2481         /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2482         voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2483
2484         change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2485         update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2486                             hweight8(old_cdclk_state->active_pipes);
2487
2488         /*
2489          * According to "Sequence Before Frequency Change",
2490          * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2491          * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2492          * which basically means we choose the maximum of old and new CDCLK, if we know both
2493          */
2494         if (change_cdclk)
2495                 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2496
2497         /*
2498          * According to "Sequence For Pipe Count Change",
2499          * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2500          * (power well is enabled)
2501          * no action if it is decreasing, before the change
2502          */
2503         if (update_pipe_count)
2504                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2505
2506         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2507                            change_cdclk, update_pipe_count);
2508 }
2509
2510 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2511 {
2512         struct drm_i915_private *i915 = to_i915(state->base.dev);
2513         const struct intel_cdclk_state *new_cdclk_state =
2514                 intel_atomic_get_new_cdclk_state(state);
2515         const struct intel_cdclk_state *old_cdclk_state =
2516                 intel_atomic_get_old_cdclk_state(state);
2517         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2518         bool update_cdclk, update_pipe_count;
2519
2520         /* According to "Sequence After Frequency Change", set voltage to used level */
2521         voltage_level = new_cdclk_state->actual.voltage_level;
2522
2523         update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2524         update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2525                             hweight8(old_cdclk_state->active_pipes);
2526
2527         /*
2528          * According to "Sequence After Frequency Change",
2529          * set bits 25:16 to current CDCLK
2530          */
2531         if (update_cdclk)
2532                 cdclk = new_cdclk_state->actual.cdclk;
2533
2534         /*
2535          * According to "Sequence For Pipe Count Change",
2536          * if pipe count is decreasing, set bits 25:16 to current pipe count,
2537          * after the change(power well is disabled)
2538          * no action if it is increasing, after the change
2539          */
2540         if (update_pipe_count)
2541                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2542
2543         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2544                            update_cdclk, update_pipe_count);
2545 }
2546
2547 /**
2548  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2549  * @state: intel atomic state
2550  *
2551  * Program the hardware before updating the HW plane state based on the
2552  * new CDCLK state, if necessary.
2553  */
2554 void
2555 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2556 {
2557         struct drm_i915_private *i915 = to_i915(state->base.dev);
2558         const struct intel_cdclk_state *old_cdclk_state =
2559                 intel_atomic_get_old_cdclk_state(state);
2560         const struct intel_cdclk_state *new_cdclk_state =
2561                 intel_atomic_get_new_cdclk_state(state);
2562         enum pipe pipe = new_cdclk_state->pipe;
2563
2564         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2565                                  &new_cdclk_state->actual))
2566                 return;
2567
2568         if (IS_DG2(i915))
2569                 intel_cdclk_pcode_pre_notify(state);
2570
2571         if (pipe == INVALID_PIPE ||
2572             old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
2573                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2574
2575                 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2576         }
2577 }
2578
2579 /**
2580  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2581  * @state: intel atomic state
2582  *
2583  * Program the hardware after updating the HW plane state based on the
2584  * new CDCLK state, if necessary.
2585  */
2586 void
2587 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2588 {
2589         struct drm_i915_private *i915 = to_i915(state->base.dev);
2590         const struct intel_cdclk_state *old_cdclk_state =
2591                 intel_atomic_get_old_cdclk_state(state);
2592         const struct intel_cdclk_state *new_cdclk_state =
2593                 intel_atomic_get_new_cdclk_state(state);
2594         enum pipe pipe = new_cdclk_state->pipe;
2595
2596         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2597                                  &new_cdclk_state->actual))
2598                 return;
2599
2600         if (IS_DG2(i915))
2601                 intel_cdclk_pcode_post_notify(state);
2602
2603         if (pipe != INVALID_PIPE &&
2604             old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
2605                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2606
2607                 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2608         }
2609 }
2610
2611 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2612 {
2613         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2614         int pixel_rate = crtc_state->pixel_rate;
2615
2616         if (DISPLAY_VER(dev_priv) >= 10)
2617                 return DIV_ROUND_UP(pixel_rate, 2);
2618         else if (DISPLAY_VER(dev_priv) == 9 ||
2619                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2620                 return pixel_rate;
2621         else if (IS_CHERRYVIEW(dev_priv))
2622                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2623         else if (crtc_state->double_wide)
2624                 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2625         else
2626                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2627 }
2628
2629 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2630 {
2631         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2632         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2633         struct intel_plane *plane;
2634         int min_cdclk = 0;
2635
2636         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
2637                 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2638
2639         return min_cdclk;
2640 }
2641
2642 static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
2643 {
2644         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2645         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2646         int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
2647         int min_cdclk = 0;
2648
2649         /*
2650          * When we decide to use only one VDSC engine, since
2651          * each VDSC operates with 1 ppc throughput, pixel clock
2652          * cannot be higher than the VDSC clock (cdclk)
2653          * If there 2 VDSC engines, then pixel clock can't be higher than
2654          * VDSC clock(cdclk) * 2 and so on.
2655          */
2656         min_cdclk = max_t(int, min_cdclk,
2657                           DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances));
2658
2659         if (crtc_state->bigjoiner_pipes) {
2660                 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
2661
2662                 /*
2663                  * According to Bigjoiner bw check:
2664                  * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
2665                  *
2666                  * We have already computed compressed_bpp, so now compute the min CDCLK that
2667                  * is required to support this compressed_bpp.
2668                  *
2669                  * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
2670                  *
2671                  * Since PPC = 2 with bigjoiner
2672                  * => CDCLK >= compressed_bpp * Pixel clock  / 2 * Bigjoiner Interface bits
2673                  */
2674                 int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
2675                 int min_cdclk_bj =
2676                         (to_bpp_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
2677                          pixel_clock) / (2 * bigjoiner_interface_bits);
2678
2679                 min_cdclk = max(min_cdclk, min_cdclk_bj);
2680         }
2681
2682         return min_cdclk;
2683 }
2684
2685 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2686 {
2687         struct drm_i915_private *dev_priv =
2688                 to_i915(crtc_state->uapi.crtc->dev);
2689         int min_cdclk;
2690
2691         if (!crtc_state->hw.enable)
2692                 return 0;
2693
2694         min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2695
2696         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2697         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2698                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2699
2700         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2701          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2702          * there may be audio corruption or screen corruption." This cdclk
2703          * restriction for GLK is 316.8 MHz.
2704          */
2705         if (intel_crtc_has_dp_encoder(crtc_state) &&
2706             crtc_state->has_audio &&
2707             crtc_state->port_clock >= 540000 &&
2708             crtc_state->lane_count == 4) {
2709                 if (DISPLAY_VER(dev_priv) == 10) {
2710                         /* Display WA #1145: glk */
2711                         min_cdclk = max(316800, min_cdclk);
2712                 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2713                         /* Display WA #1144: skl,bxt */
2714                         min_cdclk = max(432000, min_cdclk);
2715                 }
2716         }
2717
2718         /*
2719          * According to BSpec, "The CD clock frequency must be at least twice
2720          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2721          */
2722         if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2723                 min_cdclk = max(2 * 96000, min_cdclk);
2724
2725         /*
2726          * "For DP audio configuration, cdclk frequency shall be set to
2727          *  meet the following requirements:
2728          *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
2729          *  270                    | 320 or higher
2730          *  162                    | 200 or higher"
2731          */
2732         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2733             intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2734                 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2735
2736         /*
2737          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2738          * than 320000KHz.
2739          */
2740         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2741             IS_VALLEYVIEW(dev_priv))
2742                 min_cdclk = max(320000, min_cdclk);
2743
2744         /*
2745          * On Geminilake once the CDCLK gets as low as 79200
2746          * picture gets unstable, despite that values are
2747          * correct for DSI PLL and DE PLL.
2748          */
2749         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2750             IS_GEMINILAKE(dev_priv))
2751                 min_cdclk = max(158400, min_cdclk);
2752
2753         /* Account for additional needs from the planes */
2754         min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2755
2756         if (crtc_state->dsc.compression_enable)
2757                 min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2758
2759         /*
2760          * HACK. Currently for TGL/DG2 platforms we calculate
2761          * min_cdclk initially based on pixel_rate divided
2762          * by 2, accounting for also plane requirements,
2763          * however in some cases the lowest possible CDCLK
2764          * doesn't work and causing the underruns.
2765          * Explicitly stating here that this seems to be currently
2766          * rather a Hack, than final solution.
2767          */
2768         if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
2769                 /*
2770                  * Clamp to max_cdclk_freq in case pixel rate is higher,
2771                  * in order not to break an 8K, but still leave W/A at place.
2772                  */
2773                 min_cdclk = max_t(int, min_cdclk,
2774                                   min_t(int, crtc_state->pixel_rate,
2775                                         dev_priv->display.cdclk.max_cdclk_freq));
2776         }
2777
2778         return min_cdclk;
2779 }
2780
2781 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2782 {
2783         struct intel_atomic_state *state = cdclk_state->base.state;
2784         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2785         const struct intel_bw_state *bw_state;
2786         struct intel_crtc *crtc;
2787         struct intel_crtc_state *crtc_state;
2788         int min_cdclk, i;
2789         enum pipe pipe;
2790
2791         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2792                 int ret;
2793
2794                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2795                 if (min_cdclk < 0)
2796                         return min_cdclk;
2797
2798                 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2799                         continue;
2800
2801                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2802
2803                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2804                 if (ret)
2805                         return ret;
2806         }
2807
2808         bw_state = intel_atomic_get_new_bw_state(state);
2809         if (bw_state) {
2810                 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2811
2812                 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2813                         int ret;
2814
2815                         cdclk_state->bw_min_cdclk = min_cdclk;
2816
2817                         ret = intel_atomic_lock_global_state(&cdclk_state->base);
2818                         if (ret)
2819                                 return ret;
2820                 }
2821         }
2822
2823         min_cdclk = max(cdclk_state->force_min_cdclk,
2824                         cdclk_state->bw_min_cdclk);
2825         for_each_pipe(dev_priv, pipe)
2826                 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2827
2828         /*
2829          * Avoid glk_force_audio_cdclk() causing excessive screen
2830          * blinking when multiple pipes are active by making sure
2831          * CDCLK frequency is always high enough for audio. With a
2832          * single active pipe we can always change CDCLK frequency
2833          * by changing the cd2x divider (see glk_cdclk_table[]) and
2834          * thus a full modeset won't be needed then.
2835          */
2836         if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes &&
2837             !is_power_of_2(cdclk_state->active_pipes))
2838                 min_cdclk = max(2 * 96000, min_cdclk);
2839
2840         if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
2841                 drm_dbg_kms(&dev_priv->drm,
2842                             "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2843                             min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
2844                 return -EINVAL;
2845         }
2846
2847         return min_cdclk;
2848 }
2849
2850 /*
2851  * Account for port clock min voltage level requirements.
2852  * This only really does something on DISPLA_VER >= 11 but can be
2853  * called on earlier platforms as well.
2854  *
2855  * Note that this functions assumes that 0 is
2856  * the lowest voltage value, and higher values
2857  * correspond to increasingly higher voltages.
2858  *
2859  * Should that relationship no longer hold on
2860  * future platforms this code will need to be
2861  * adjusted.
2862  */
2863 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2864 {
2865         struct intel_atomic_state *state = cdclk_state->base.state;
2866         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2867         struct intel_crtc *crtc;
2868         struct intel_crtc_state *crtc_state;
2869         u8 min_voltage_level;
2870         int i;
2871         enum pipe pipe;
2872
2873         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2874                 int ret;
2875
2876                 if (crtc_state->hw.enable)
2877                         min_voltage_level = crtc_state->min_voltage_level;
2878                 else
2879                         min_voltage_level = 0;
2880
2881                 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2882                         continue;
2883
2884                 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2885
2886                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2887                 if (ret)
2888                         return ret;
2889         }
2890
2891         min_voltage_level = 0;
2892         for_each_pipe(dev_priv, pipe)
2893                 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2894                                         min_voltage_level);
2895
2896         return min_voltage_level;
2897 }
2898
2899 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2900 {
2901         struct intel_atomic_state *state = cdclk_state->base.state;
2902         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2903         int min_cdclk, cdclk;
2904
2905         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2906         if (min_cdclk < 0)
2907                 return min_cdclk;
2908
2909         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2910
2911         cdclk_state->logical.cdclk = cdclk;
2912         cdclk_state->logical.voltage_level =
2913                 vlv_calc_voltage_level(dev_priv, cdclk);
2914
2915         if (!cdclk_state->active_pipes) {
2916                 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2917
2918                 cdclk_state->actual.cdclk = cdclk;
2919                 cdclk_state->actual.voltage_level =
2920                         vlv_calc_voltage_level(dev_priv, cdclk);
2921         } else {
2922                 cdclk_state->actual = cdclk_state->logical;
2923         }
2924
2925         return 0;
2926 }
2927
2928 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2929 {
2930         int min_cdclk, cdclk;
2931
2932         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2933         if (min_cdclk < 0)
2934                 return min_cdclk;
2935
2936         cdclk = bdw_calc_cdclk(min_cdclk);
2937
2938         cdclk_state->logical.cdclk = cdclk;
2939         cdclk_state->logical.voltage_level =
2940                 bdw_calc_voltage_level(cdclk);
2941
2942         if (!cdclk_state->active_pipes) {
2943                 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2944
2945                 cdclk_state->actual.cdclk = cdclk;
2946                 cdclk_state->actual.voltage_level =
2947                         bdw_calc_voltage_level(cdclk);
2948         } else {
2949                 cdclk_state->actual = cdclk_state->logical;
2950         }
2951
2952         return 0;
2953 }
2954
2955 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2956 {
2957         struct intel_atomic_state *state = cdclk_state->base.state;
2958         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2959         struct intel_crtc *crtc;
2960         struct intel_crtc_state *crtc_state;
2961         int vco, i;
2962
2963         vco = cdclk_state->logical.vco;
2964         if (!vco)
2965                 vco = dev_priv->skl_preferred_vco_freq;
2966
2967         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2968                 if (!crtc_state->hw.enable)
2969                         continue;
2970
2971                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2972                         continue;
2973
2974                 /*
2975                  * DPLL0 VCO may need to be adjusted to get the correct
2976                  * clock for eDP. This will affect cdclk as well.
2977                  */
2978                 switch (crtc_state->port_clock / 2) {
2979                 case 108000:
2980                 case 216000:
2981                         vco = 8640000;
2982                         break;
2983                 default:
2984                         vco = 8100000;
2985                         break;
2986                 }
2987         }
2988
2989         return vco;
2990 }
2991
2992 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2993 {
2994         int min_cdclk, cdclk, vco;
2995
2996         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2997         if (min_cdclk < 0)
2998                 return min_cdclk;
2999
3000         vco = skl_dpll0_vco(cdclk_state);
3001
3002         cdclk = skl_calc_cdclk(min_cdclk, vco);
3003
3004         cdclk_state->logical.vco = vco;
3005         cdclk_state->logical.cdclk = cdclk;
3006         cdclk_state->logical.voltage_level =
3007                 skl_calc_voltage_level(cdclk);
3008
3009         if (!cdclk_state->active_pipes) {
3010                 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
3011
3012                 cdclk_state->actual.vco = vco;
3013                 cdclk_state->actual.cdclk = cdclk;
3014                 cdclk_state->actual.voltage_level =
3015                         skl_calc_voltage_level(cdclk);
3016         } else {
3017                 cdclk_state->actual = cdclk_state->logical;
3018         }
3019
3020         return 0;
3021 }
3022
3023 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3024 {
3025         struct intel_atomic_state *state = cdclk_state->base.state;
3026         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3027         int min_cdclk, min_voltage_level, cdclk, vco;
3028
3029         min_cdclk = intel_compute_min_cdclk(cdclk_state);
3030         if (min_cdclk < 0)
3031                 return min_cdclk;
3032
3033         min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
3034         if (min_voltage_level < 0)
3035                 return min_voltage_level;
3036
3037         cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
3038         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3039
3040         cdclk_state->logical.vco = vco;
3041         cdclk_state->logical.cdclk = cdclk;
3042         cdclk_state->logical.voltage_level =
3043                 max_t(int, min_voltage_level,
3044                       intel_cdclk_calc_voltage_level(dev_priv, cdclk));
3045
3046         if (!cdclk_state->active_pipes) {
3047                 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
3048                 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
3049
3050                 cdclk_state->actual.vco = vco;
3051                 cdclk_state->actual.cdclk = cdclk;
3052                 cdclk_state->actual.voltage_level =
3053                         intel_cdclk_calc_voltage_level(dev_priv, cdclk);
3054         } else {
3055                 cdclk_state->actual = cdclk_state->logical;
3056         }
3057
3058         return 0;
3059 }
3060
3061 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
3062 {
3063         int min_cdclk;
3064
3065         /*
3066          * We can't change the cdclk frequency, but we still want to
3067          * check that the required minimum frequency doesn't exceed
3068          * the actual cdclk frequency.
3069          */
3070         min_cdclk = intel_compute_min_cdclk(cdclk_state);
3071         if (min_cdclk < 0)
3072                 return min_cdclk;
3073
3074         return 0;
3075 }
3076
3077 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3078 {
3079         struct intel_cdclk_state *cdclk_state;
3080
3081         cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3082         if (!cdclk_state)
3083                 return NULL;
3084
3085         cdclk_state->pipe = INVALID_PIPE;
3086
3087         return &cdclk_state->base;
3088 }
3089
3090 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3091                                       struct intel_global_state *state)
3092 {
3093         kfree(state);
3094 }
3095
3096 static const struct intel_global_state_funcs intel_cdclk_funcs = {
3097         .atomic_duplicate_state = intel_cdclk_duplicate_state,
3098         .atomic_destroy_state = intel_cdclk_destroy_state,
3099 };
3100
3101 struct intel_cdclk_state *
3102 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3103 {
3104         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3105         struct intel_global_state *cdclk_state;
3106
3107         cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
3108         if (IS_ERR(cdclk_state))
3109                 return ERR_CAST(cdclk_state);
3110
3111         return to_intel_cdclk_state(cdclk_state);
3112 }
3113
3114 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
3115                              bool *need_cdclk_calc)
3116 {
3117         const struct intel_cdclk_state *old_cdclk_state;
3118         const struct intel_cdclk_state *new_cdclk_state;
3119         struct intel_plane_state __maybe_unused *plane_state;
3120         struct intel_plane *plane;
3121         int ret;
3122         int i;
3123
3124         /*
3125          * active_planes bitmask has been updated, and potentially affected
3126          * planes are part of the state. We can now compute the minimum cdclk
3127          * for each plane.
3128          */
3129         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
3130                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
3131                 if (ret)
3132                         return ret;
3133         }
3134
3135         ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
3136         if (ret)
3137                 return ret;
3138
3139         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3140         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3141
3142         if (new_cdclk_state &&
3143             old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
3144                 *need_cdclk_calc = true;
3145
3146         return 0;
3147 }
3148
3149 int intel_cdclk_init(struct drm_i915_private *dev_priv)
3150 {
3151         struct intel_cdclk_state *cdclk_state;
3152
3153         cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3154         if (!cdclk_state)
3155                 return -ENOMEM;
3156
3157         intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
3158                                      &cdclk_state->base, &intel_cdclk_funcs);
3159
3160         return 0;
3161 }
3162
3163 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
3164                                        const struct intel_cdclk_state *old_cdclk_state,
3165                                        const struct intel_cdclk_state *new_cdclk_state)
3166 {
3167         bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3168                                       hweight8(new_cdclk_state->active_pipes);
3169         bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3170                                                  &new_cdclk_state->actual);
3171         /*
3172          * We need to poke hw for gen >= 12, because we notify PCode if
3173          * pipe power well count changes.
3174          */
3175         return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed);
3176 }
3177
3178 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3179 {
3180         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3181         const struct intel_cdclk_state *old_cdclk_state;
3182         struct intel_cdclk_state *new_cdclk_state;
3183         enum pipe pipe = INVALID_PIPE;
3184         int ret;
3185
3186         new_cdclk_state = intel_atomic_get_cdclk_state(state);
3187         if (IS_ERR(new_cdclk_state))
3188                 return PTR_ERR(new_cdclk_state);
3189
3190         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3191
3192         new_cdclk_state->active_pipes =
3193                 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3194
3195         ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
3196         if (ret)
3197                 return ret;
3198
3199         if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
3200                 /*
3201                  * Also serialize commits across all crtcs
3202                  * if the actual hw needs to be poked.
3203                  */
3204                 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3205                 if (ret)
3206                         return ret;
3207         } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3208                    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3209                    intel_cdclk_changed(&old_cdclk_state->logical,
3210                                        &new_cdclk_state->logical)) {
3211                 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3212                 if (ret)
3213                         return ret;
3214         } else {
3215                 return 0;
3216         }
3217
3218         if (is_power_of_2(new_cdclk_state->active_pipes) &&
3219             intel_cdclk_can_cd2x_update(dev_priv,
3220                                         &old_cdclk_state->actual,
3221                                         &new_cdclk_state->actual)) {
3222                 struct intel_crtc *crtc;
3223                 struct intel_crtc_state *crtc_state;
3224
3225                 pipe = ilog2(new_cdclk_state->active_pipes);
3226                 crtc = intel_crtc_for_pipe(dev_priv, pipe);
3227
3228                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3229                 if (IS_ERR(crtc_state))
3230                         return PTR_ERR(crtc_state);
3231
3232                 if (intel_crtc_needs_modeset(crtc_state))
3233                         pipe = INVALID_PIPE;
3234         }
3235
3236         if (intel_cdclk_can_crawl_and_squash(dev_priv,
3237                                              &old_cdclk_state->actual,
3238                                              &new_cdclk_state->actual)) {
3239                 drm_dbg_kms(&dev_priv->drm,
3240                             "Can change cdclk via crawling and squashing\n");
3241         } else if (intel_cdclk_can_squash(dev_priv,
3242                                         &old_cdclk_state->actual,
3243                                         &new_cdclk_state->actual)) {
3244                 drm_dbg_kms(&dev_priv->drm,
3245                             "Can change cdclk via squashing\n");
3246         } else if (intel_cdclk_can_crawl(dev_priv,
3247                                          &old_cdclk_state->actual,
3248                                          &new_cdclk_state->actual)) {
3249                 drm_dbg_kms(&dev_priv->drm,
3250                             "Can change cdclk via crawling\n");
3251         } else if (pipe != INVALID_PIPE) {
3252                 new_cdclk_state->pipe = pipe;
3253
3254                 drm_dbg_kms(&dev_priv->drm,
3255                             "Can change cdclk cd2x divider with pipe %c active\n",
3256                             pipe_name(pipe));
3257         } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual,
3258                                              &new_cdclk_state->actual)) {
3259                 /* All pipes must be switched off while we change the cdclk. */
3260                 ret = intel_modeset_all_pipes_late(state, "CDCLK change");
3261                 if (ret)
3262                         return ret;
3263
3264                 drm_dbg_kms(&dev_priv->drm,
3265                             "Modeset required for cdclk change\n");
3266         }
3267
3268         drm_dbg_kms(&dev_priv->drm,
3269                     "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3270                     new_cdclk_state->logical.cdclk,
3271                     new_cdclk_state->actual.cdclk);
3272         drm_dbg_kms(&dev_priv->drm,
3273                     "New voltage level calculated to be logical %u, actual %u\n",
3274                     new_cdclk_state->logical.voltage_level,
3275                     new_cdclk_state->actual.voltage_level);
3276
3277         return 0;
3278 }
3279
3280 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
3281 {
3282         int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
3283
3284         if (DISPLAY_VER(dev_priv) >= 10)
3285                 return 2 * max_cdclk_freq;
3286         else if (DISPLAY_VER(dev_priv) == 9 ||
3287                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3288                 return max_cdclk_freq;
3289         else if (IS_CHERRYVIEW(dev_priv))
3290                 return max_cdclk_freq*95/100;
3291         else if (DISPLAY_VER(dev_priv) < 4)
3292                 return 2*max_cdclk_freq*90/100;
3293         else
3294                 return max_cdclk_freq*90/100;
3295 }
3296
3297 /**
3298  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3299  * @dev_priv: i915 device
3300  *
3301  * Determine the maximum CDCLK frequency the platform supports, and also
3302  * derive the maximum dot clock frequency the maximum CDCLK frequency
3303  * allows.
3304  */
3305 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
3306 {
3307         if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3308                 if (dev_priv->display.cdclk.hw.ref == 24000)
3309                         dev_priv->display.cdclk.max_cdclk_freq = 552000;
3310                 else
3311                         dev_priv->display.cdclk.max_cdclk_freq = 556800;
3312         } else if (DISPLAY_VER(dev_priv) >= 11) {
3313                 if (dev_priv->display.cdclk.hw.ref == 24000)
3314                         dev_priv->display.cdclk.max_cdclk_freq = 648000;
3315                 else
3316                         dev_priv->display.cdclk.max_cdclk_freq = 652800;
3317         } else if (IS_GEMINILAKE(dev_priv)) {
3318                 dev_priv->display.cdclk.max_cdclk_freq = 316800;
3319         } else if (IS_BROXTON(dev_priv)) {
3320                 dev_priv->display.cdclk.max_cdclk_freq = 624000;
3321         } else if (DISPLAY_VER(dev_priv) == 9) {
3322                 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3323                 int max_cdclk, vco;
3324
3325                 vco = dev_priv->skl_preferred_vco_freq;
3326                 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
3327
3328                 /*
3329                  * Use the lower (vco 8640) cdclk values as a
3330                  * first guess. skl_calc_cdclk() will correct it
3331                  * if the preferred vco is 8100 instead.
3332                  */
3333                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3334                         max_cdclk = 617143;
3335                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3336                         max_cdclk = 540000;
3337                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3338                         max_cdclk = 432000;
3339                 else
3340                         max_cdclk = 308571;
3341
3342                 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3343         } else if (IS_BROADWELL(dev_priv))  {
3344                 /*
3345                  * FIXME with extra cooling we can allow
3346                  * 540 MHz for ULX and 675 Mhz for ULT.
3347                  * How can we know if extra cooling is
3348                  * available? PCI ID, VTB, something else?
3349                  */
3350                 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3351                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3352                 else if (IS_BROADWELL_ULX(dev_priv))
3353                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3354                 else if (IS_BROADWELL_ULT(dev_priv))
3355                         dev_priv->display.cdclk.max_cdclk_freq = 540000;
3356                 else
3357                         dev_priv->display.cdclk.max_cdclk_freq = 675000;
3358         } else if (IS_CHERRYVIEW(dev_priv)) {
3359                 dev_priv->display.cdclk.max_cdclk_freq = 320000;
3360         } else if (IS_VALLEYVIEW(dev_priv)) {
3361                 dev_priv->display.cdclk.max_cdclk_freq = 400000;
3362         } else {
3363                 /* otherwise assume cdclk is fixed */
3364                 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
3365         }
3366
3367         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
3368
3369         drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
3370                 dev_priv->display.cdclk.max_cdclk_freq);
3371
3372         drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
3373                 dev_priv->max_dotclk_freq);
3374 }
3375
3376 /**
3377  * intel_update_cdclk - Determine the current CDCLK frequency
3378  * @dev_priv: i915 device
3379  *
3380  * Determine the current CDCLK frequency.
3381  */
3382 void intel_update_cdclk(struct drm_i915_private *dev_priv)
3383 {
3384         intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
3385
3386         /*
3387          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3388          * Programmng [sic] note: bit[9:2] should be programmed to the number
3389          * of cdclk that generates 4MHz reference clock freq which is used to
3390          * generate GMBus clock. This will vary with the cdclk freq.
3391          */
3392         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3393                 intel_de_write(dev_priv, GMBUSFREQ_VLV,
3394                                DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
3395 }
3396
3397 static int dg1_rawclk(struct drm_i915_private *dev_priv)
3398 {
3399         /*
3400          * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
3401          * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3402          */
3403         intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
3404                        CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3405
3406         return 38400;
3407 }
3408
3409 static int cnp_rawclk(struct drm_i915_private *dev_priv)
3410 {
3411         u32 rawclk;
3412         int divider, fraction;
3413
3414         if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3415                 /* 24 MHz */
3416                 divider = 24000;
3417                 fraction = 0;
3418         } else {
3419                 /* 19.2 MHz */
3420                 divider = 19000;
3421                 fraction = 200;
3422         }
3423
3424         rawclk = CNP_RAWCLK_DIV(divider / 1000);
3425         if (fraction) {
3426                 int numerator = 1;
3427
3428                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3429                                                            fraction) - 1);
3430                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3431                         rawclk |= ICP_RAWCLK_NUM(numerator);
3432         }
3433
3434         intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
3435         return divider + fraction;
3436 }
3437
3438 static int pch_rawclk(struct drm_i915_private *dev_priv)
3439 {
3440         return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3441 }
3442
3443 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
3444 {
3445         /* RAWCLK_FREQ_VLV register updated from power well code */
3446         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3447                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
3448 }
3449
3450 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
3451 {
3452         u32 clkcfg;
3453
3454         /*
3455          * hrawclock is 1/4 the FSB frequency
3456          *
3457          * Note that this only reads the state of the FSB
3458          * straps, not the actual FSB frequency. Some BIOSen
3459          * let you configure each independently. Ideally we'd
3460          * read out the actual FSB frequency but sadly we
3461          * don't know which registers have that information,
3462          * and all the relevant docs have gone to bit heaven :(
3463          */
3464         clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
3465
3466         if (IS_MOBILE(dev_priv)) {
3467                 switch (clkcfg) {
3468                 case CLKCFG_FSB_400:
3469                         return 100000;
3470                 case CLKCFG_FSB_533:
3471                         return 133333;
3472                 case CLKCFG_FSB_667:
3473                         return 166667;
3474                 case CLKCFG_FSB_800:
3475                         return 200000;
3476                 case CLKCFG_FSB_1067:
3477                         return 266667;
3478                 case CLKCFG_FSB_1333:
3479                         return 333333;
3480                 default:
3481                         MISSING_CASE(clkcfg);
3482                         return 133333;
3483                 }
3484         } else {
3485                 switch (clkcfg) {
3486                 case CLKCFG_FSB_400_ALT:
3487                         return 100000;
3488                 case CLKCFG_FSB_533:
3489                         return 133333;
3490                 case CLKCFG_FSB_667:
3491                         return 166667;
3492                 case CLKCFG_FSB_800:
3493                         return 200000;
3494                 case CLKCFG_FSB_1067_ALT:
3495                         return 266667;
3496                 case CLKCFG_FSB_1333_ALT:
3497                         return 333333;
3498                 case CLKCFG_FSB_1600_ALT:
3499                         return 400000;
3500                 default:
3501                         return 133333;
3502                 }
3503         }
3504 }
3505
3506 /**
3507  * intel_read_rawclk - Determine the current RAWCLK frequency
3508  * @dev_priv: i915 device
3509  *
3510  * Determine the current RAWCLK frequency. RAWCLK is a fixed
3511  * frequency clock so this needs to done only once.
3512  */
3513 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
3514 {
3515         u32 freq;
3516
3517         if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
3518                 /*
3519                  * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
3520                  * "RAWCLK_FREQ defaults to the values for 38.4 and does
3521                  * not need to be programmed."
3522                  */
3523                 freq = 38400;
3524         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3525                 freq = dg1_rawclk(dev_priv);
3526         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3527                 freq = cnp_rawclk(dev_priv);
3528         else if (HAS_PCH_SPLIT(dev_priv))
3529                 freq = pch_rawclk(dev_priv);
3530         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3531                 freq = vlv_hrawclk(dev_priv);
3532         else if (DISPLAY_VER(dev_priv) >= 3)
3533                 freq = i9xx_hrawclk(dev_priv);
3534         else
3535                 /* no rawclk on other platforms, or no need to know it */
3536                 return 0;
3537
3538         return freq;
3539 }
3540
3541 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3542 {
3543         struct drm_i915_private *i915 = m->private;
3544
3545         seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
3546         seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
3547         seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
3548
3549         return 0;
3550 }
3551
3552 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3553
3554 void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
3555 {
3556         struct drm_minor *minor = i915->drm.primary;
3557
3558         debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3559                             i915, &i915_cdclk_info_fops);
3560 }
3561
3562 static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
3563         .get_cdclk = bxt_get_cdclk,
3564         .set_cdclk = bxt_set_cdclk,
3565         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3566         .calc_voltage_level = rplu_calc_voltage_level,
3567 };
3568
3569 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3570         .get_cdclk = bxt_get_cdclk,
3571         .set_cdclk = bxt_set_cdclk,
3572         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3573         .calc_voltage_level = rplu_calc_voltage_level,
3574 };
3575
3576 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3577         .get_cdclk = bxt_get_cdclk,
3578         .set_cdclk = bxt_set_cdclk,
3579         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3580         .calc_voltage_level = tgl_calc_voltage_level,
3581 };
3582
3583 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3584         .get_cdclk = bxt_get_cdclk,
3585         .set_cdclk = bxt_set_cdclk,
3586         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3587         .calc_voltage_level = ehl_calc_voltage_level,
3588 };
3589
3590 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3591         .get_cdclk = bxt_get_cdclk,
3592         .set_cdclk = bxt_set_cdclk,
3593         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3594         .calc_voltage_level = icl_calc_voltage_level,
3595 };
3596
3597 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3598         .get_cdclk = bxt_get_cdclk,
3599         .set_cdclk = bxt_set_cdclk,
3600         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3601         .calc_voltage_level = bxt_calc_voltage_level,
3602 };
3603
3604 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3605         .get_cdclk = skl_get_cdclk,
3606         .set_cdclk = skl_set_cdclk,
3607         .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3608 };
3609
3610 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3611         .get_cdclk = bdw_get_cdclk,
3612         .set_cdclk = bdw_set_cdclk,
3613         .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3614 };
3615
3616 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3617         .get_cdclk = vlv_get_cdclk,
3618         .set_cdclk = chv_set_cdclk,
3619         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3620 };
3621
3622 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3623         .get_cdclk = vlv_get_cdclk,
3624         .set_cdclk = vlv_set_cdclk,
3625         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3626 };
3627
3628 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3629         .get_cdclk = hsw_get_cdclk,
3630         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3631 };
3632
3633 /* SNB, IVB, 965G, 945G */
3634 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3635         .get_cdclk = fixed_400mhz_get_cdclk,
3636         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3637 };
3638
3639 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3640         .get_cdclk = fixed_450mhz_get_cdclk,
3641         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3642 };
3643
3644 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3645         .get_cdclk = gm45_get_cdclk,
3646         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3647 };
3648
3649 /* G45 uses G33 */
3650
3651 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3652         .get_cdclk = i965gm_get_cdclk,
3653         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3654 };
3655
3656 /* i965G uses fixed 400 */
3657
3658 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3659         .get_cdclk = pnv_get_cdclk,
3660         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3661 };
3662
3663 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3664         .get_cdclk = g33_get_cdclk,
3665         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3666 };
3667
3668 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3669         .get_cdclk = i945gm_get_cdclk,
3670         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3671 };
3672
3673 /* i945G uses fixed 400 */
3674
3675 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3676         .get_cdclk = i915gm_get_cdclk,
3677         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3678 };
3679
3680 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3681         .get_cdclk = fixed_333mhz_get_cdclk,
3682         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3683 };
3684
3685 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3686         .get_cdclk = fixed_266mhz_get_cdclk,
3687         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3688 };
3689
3690 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3691         .get_cdclk = i85x_get_cdclk,
3692         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3693 };
3694
3695 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3696         .get_cdclk = fixed_200mhz_get_cdclk,
3697         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3698 };
3699
3700 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3701         .get_cdclk = fixed_133mhz_get_cdclk,
3702         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3703 };
3704
3705 /**
3706  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3707  * @dev_priv: i915 device
3708  */
3709 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
3710 {
3711         if (DISPLAY_VER(dev_priv) >= 20) {
3712                 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3713                 dev_priv->display.cdclk.table = lnl_cdclk_table;
3714         } else if (DISPLAY_VER(dev_priv) >= 14) {
3715                 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3716                 dev_priv->display.cdclk.table = mtl_cdclk_table;
3717         } else if (IS_DG2(dev_priv)) {
3718                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3719                 dev_priv->display.cdclk.table = dg2_cdclk_table;
3720         } else if (IS_ALDERLAKE_P(dev_priv)) {
3721                 /* Wa_22011320316:adl-p[a0] */
3722                 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3723                         dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
3724                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3725                 } else if (IS_RAPTORLAKE_U(dev_priv)) {
3726                         dev_priv->display.cdclk.table = rplu_cdclk_table;
3727                         dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
3728                 } else {
3729                         dev_priv->display.cdclk.table = adlp_cdclk_table;
3730                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3731                 }
3732         } else if (IS_ROCKETLAKE(dev_priv)) {
3733                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3734                 dev_priv->display.cdclk.table = rkl_cdclk_table;
3735         } else if (DISPLAY_VER(dev_priv) >= 12) {
3736                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3737                 dev_priv->display.cdclk.table = icl_cdclk_table;
3738         } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
3739                 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
3740                 dev_priv->display.cdclk.table = icl_cdclk_table;
3741         } else if (DISPLAY_VER(dev_priv) >= 11) {
3742                 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
3743                 dev_priv->display.cdclk.table = icl_cdclk_table;
3744         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
3745                 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
3746                 if (IS_GEMINILAKE(dev_priv))
3747                         dev_priv->display.cdclk.table = glk_cdclk_table;
3748                 else
3749                         dev_priv->display.cdclk.table = bxt_cdclk_table;
3750         } else if (DISPLAY_VER(dev_priv) == 9) {
3751                 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
3752         } else if (IS_BROADWELL(dev_priv)) {
3753                 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
3754         } else if (IS_HASWELL(dev_priv)) {
3755                 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
3756         } else if (IS_CHERRYVIEW(dev_priv)) {
3757                 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
3758         } else if (IS_VALLEYVIEW(dev_priv)) {
3759                 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
3760         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
3761                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3762         } else if (IS_IRONLAKE(dev_priv)) {
3763                 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
3764         } else if (IS_GM45(dev_priv)) {
3765                 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
3766         } else if (IS_G45(dev_priv)) {
3767                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3768         } else if (IS_I965GM(dev_priv)) {
3769                 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
3770         } else if (IS_I965G(dev_priv)) {
3771                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3772         } else if (IS_PINEVIEW(dev_priv)) {
3773                 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
3774         } else if (IS_G33(dev_priv)) {
3775                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3776         } else if (IS_I945GM(dev_priv)) {
3777                 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
3778         } else if (IS_I945G(dev_priv)) {
3779                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3780         } else if (IS_I915GM(dev_priv)) {
3781                 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
3782         } else if (IS_I915G(dev_priv)) {
3783                 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
3784         } else if (IS_I865G(dev_priv)) {
3785                 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
3786         } else if (IS_I85X(dev_priv)) {
3787                 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
3788         } else if (IS_I845G(dev_priv)) {
3789                 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
3790         } else if (IS_I830(dev_priv)) {
3791                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3792         }
3793
3794         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
3795                      "Unknown platform. Assuming i830\n"))
3796                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3797 }