drivers/gpu/drm/i915/display/intel_dp_link_training.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_display_types.h"
  25 #include "intel_dp.h"
  26 #include "intel_dp_link_training.h"
  27
  28 static void
  29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE])
  30 {
  31
  32         DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
  33                       link_status[0], link_status[1], link_status[2],
  34                       link_status[3], link_status[4], link_status[5]);
  35 }
  36
  37 static int intel_dp_lttpr_count(struct intel_dp *intel_dp)
  38 {
  39         int count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
  40
  41         /*
  42          * Pretend no LTTPRs in case of LTTPR detection error, or
  43          * if too many (>8) LTTPRs are detected. This translates to link
  44          * training in transparent mode.
  45          */
  46         return count <= 0 ? 0 : count;
  47 }
  48
  49 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
  50 {
  51         intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
  52                                     DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
  53 }
  54
  55 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
  56                                      char *buf, size_t buf_size)
  57 {
  58         if (dp_phy == DP_PHY_DPRX)
  59                 snprintf(buf, buf_size, "DPRX");
  60         else
  61                 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
  62
  63         return buf;
  64 }
  65
  66 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
  67                                    enum drm_dp_phy dp_phy)
  68 {
  69         return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
  70 }
  71
  72 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
  73                                          enum drm_dp_phy dp_phy)
  74 {
  75         u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
  76         char phy_name[10];
  77
  78         intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
  79
  80         if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
  81                 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
  82                             "failed to read the PHY caps for %s\n",
  83                             phy_name);
  84                 return;
  85         }
  86
  87         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
  88                     "%s PHY capabilities: %*ph\n",
  89                     phy_name,
  90                     (int)sizeof(intel_dp->lttpr_phy_caps[0]),
  91                     phy_caps);
  92 }
  93
  94 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
  95 {
  96         if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
  97                                           intel_dp->lttpr_common_caps) < 0) {
  98                 memset(intel_dp->lttpr_common_caps, 0,
  99                        sizeof(intel_dp->lttpr_common_caps));
 100                 return false;
 101         }
 102
 103         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 104                     "LTTPR common capabilities: %*ph\n",
 105                     (int)sizeof(intel_dp->lttpr_common_caps),
 106                     intel_dp->lttpr_common_caps);
 107
 108         return true;
 109 }
 110
 111 static bool
 112 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
 113 {
 114         u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
 115                           DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
 116
 117         return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
 118 }
 119
 120 /**
 121  * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode
 122  * @intel_dp: Intel DP struct
 123  *
 124  * Read the LTTPR common capabilities, switch to non-transparent link training
 125  * mode if any is detected and read the PHY capabilities for all detected
 126  * LTTPRs. In case of an LTTPR detection error or if the number of
 127  * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
 128  * transparent mode link training mode.
 129  *
 130  * Returns:
 131  *   >0  if LTTPRs were detected and the non-transparent LT mode was set
 132  *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
 133  *       detection failure and the transparent LT mode was set
 134  */
 135 int intel_dp_lttpr_init(struct intel_dp *intel_dp)
 136 {
 137         int lttpr_count;
 138         bool ret;
 139         int i;
 140
 141         if (intel_dp_is_edp(intel_dp))
 142                 return 0;
 143
 144         ret = intel_dp_read_lttpr_common_caps(intel_dp);
 145
 146         /*
 147          * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
 148          * non-transparent mode and the disable->enable non-transparent mode
 149          * sequence.
 150          */
 151         intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 152
 153         if (!ret)
 154                 return 0;
 155
 156         lttpr_count = intel_dp_lttpr_count(intel_dp);
 157
 158         /*
 159          * In case of unsupported number of LTTPRs or failing to switch to
 160          * non-transparent mode fall-back to transparent link training mode,
 161          * still taking into account any LTTPR common lane- rate/count limits.
 162          */
 163         if (lttpr_count == 0)
 164                 return 0;
 165
 166         if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
 167                 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 168                             "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
 169
 170                 intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 171                 intel_dp_reset_lttpr_count(intel_dp);
 172
 173                 return 0;
 174         }
 175
 176         for (i = 0; i < lttpr_count; i++)
 177                 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
 178
 179         return lttpr_count;
 180 }
 181 EXPORT_SYMBOL(intel_dp_lttpr_init);
 182
 183 static u8 dp_voltage_max(u8 preemph)
 184 {
 185         switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
 186         case DP_TRAIN_PRE_EMPH_LEVEL_0:
 187                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 188         case DP_TRAIN_PRE_EMPH_LEVEL_1:
 189                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 190         case DP_TRAIN_PRE_EMPH_LEVEL_2:
 191                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 192         case DP_TRAIN_PRE_EMPH_LEVEL_3:
 193         default:
 194                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 195         }
 196 }
 197
 198 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
 199                                      enum drm_dp_phy dp_phy)
 200 {
 201         const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 202
 203         if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
 204                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 205         else
 206                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 207 }
 208
 209 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
 210                                      enum drm_dp_phy dp_phy)
 211 {
 212         const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 213
 214         if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
 215                 return DP_TRAIN_PRE_EMPH_LEVEL_3;
 216         else
 217                 return DP_TRAIN_PRE_EMPH_LEVEL_2;
 218 }
 219
 220 static bool
 221 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
 222                                      enum drm_dp_phy dp_phy)
 223 {
 224         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 225         int lttpr_count = intel_dp_lttpr_count(intel_dp);
 226
 227         drm_WARN_ON_ONCE(&i915->drm, lttpr_count == 0 && dp_phy != DP_PHY_DPRX);
 228
 229         return lttpr_count == 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
 230 }
 231
 232 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
 233                                    const struct intel_crtc_state *crtc_state,
 234                                    enum drm_dp_phy dp_phy)
 235 {
 236         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 237         u8 voltage_max;
 238
 239         /*
 240          * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
 241          * the DPRX_PHY we train.
 242          */
 243         if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 244                 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
 245         else
 246                 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
 247
 248         drm_WARN_ON_ONCE(&i915->drm,
 249                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
 250                          voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
 251
 252         return voltage_max;
 253 }
 254
 255 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
 256                                    enum drm_dp_phy dp_phy)
 257 {
 258         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 259         u8 preemph_max;
 260
 261         /*
 262          * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
 263          * the DPRX_PHY we train.
 264          */
 265         if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 266                 preemph_max = intel_dp->preemph_max(intel_dp);
 267         else
 268                 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
 269
 270         drm_WARN_ON_ONCE(&i915->drm,
 271                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
 272                          preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
 273
 274         return preemph_max;
 275 }
 276
 277 void
 278 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 279                           const struct intel_crtc_state *crtc_state,
 280                           enum drm_dp_phy dp_phy,
 281                           const u8 link_status[DP_LINK_STATUS_SIZE])
 282 {
 283         u8 v = 0;
 284         u8 p = 0;
 285         int lane;
 286         u8 voltage_max;
 287         u8 preemph_max;
 288
 289         for (lane = 0; lane < crtc_state->lane_count; lane++) {
 290                 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 291                 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 292         }
 293
 294         preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
 295         if (p >= preemph_max)
 296                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 297
 298         v = min(v, dp_voltage_max(p));
 299
 300         voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
 301         if (v >= voltage_max)
 302                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 303
 304         for (lane = 0; lane < 4; lane++)
 305                 intel_dp->train_set[lane] = v | p;
 306 }
 307
 308 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
 309                                              enum drm_dp_phy dp_phy)
 310 {
 311         return dp_phy == DP_PHY_DPRX ?
 312                 DP_TRAINING_PATTERN_SET :
 313                 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
 314 }
 315
 316 static bool
 317 intel_dp_set_link_train(struct intel_dp *intel_dp,
 318                         const struct intel_crtc_state *crtc_state,
 319                         enum drm_dp_phy dp_phy,
 320                         u8 dp_train_pat)
 321 {
 322         int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 323         u8 buf[sizeof(intel_dp->train_set) + 1];
 324         int len;
 325
 326         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
 327                                                dp_train_pat);
 328
 329         buf[0] = dp_train_pat;
 330         /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
 331         memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
 332         len = crtc_state->lane_count + 1;
 333
 334         return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 335 }
 336
 337 static bool
 338 intel_dp_reset_link_train(struct intel_dp *intel_dp,
 339                           const struct intel_crtc_state *crtc_state,
 340                           enum drm_dp_phy dp_phy,
 341                           u8 dp_train_pat)
 342 {
 343         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 344         intel_dp_set_signal_levels(intel_dp, crtc_state);
 345         return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 346 }
 347
 348 static bool
 349 intel_dp_update_link_train(struct intel_dp *intel_dp,
 350                            const struct intel_crtc_state *crtc_state,
 351                            enum drm_dp_phy dp_phy)
 352 {
 353         int reg = dp_phy == DP_PHY_DPRX ?
 354                             DP_TRAINING_LANE0_SET :
 355                             DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
 356         int ret;
 357
 358         intel_dp_set_signal_levels(intel_dp, crtc_state);
 359
 360         ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
 361                                 intel_dp->train_set, crtc_state->lane_count);
 362
 363         return ret == crtc_state->lane_count;
 364 }
 365
 366 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 367                                              const struct intel_crtc_state *crtc_state)
 368 {
 369         int lane;
 370
 371         for (lane = 0; lane < crtc_state->lane_count; lane++)
 372                 if ((intel_dp->train_set[lane] &
 373                      DP_TRAIN_MAX_SWING_REACHED) == 0)
 374                         return false;
 375
 376         return true;
 377 }
 378
 379 /*
 380  * Prepare link training by configuring the link parameters. On DDI platforms
 381  * also enable the port here.
 382  */
 383 static bool
 384 intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 385                             const struct intel_crtc_state *crtc_state)
 386 {
 387         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 388         u8 link_config[2];
 389         u8 link_bw, rate_select;
 390
 391         if (intel_dp->prepare_link_retrain)
 392                 intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 393
 394         intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 395                               &link_bw, &rate_select);
 396
 397         if (link_bw)
 398                 drm_dbg_kms(&i915->drm,
 399                             "Using LINK_BW_SET value %02x\n", link_bw);
 400         else
 401                 drm_dbg_kms(&i915->drm,
 402                             "Using LINK_RATE_SET value %02x\n", rate_select);
 403
 404         /* Write the link configuration data */
 405         link_config[0] = link_bw;
 406         link_config[1] = crtc_state->lane_count;
 407         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 408                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 409         drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
 410
 411         /* eDP 1.4 rate select method. */
 412         if (!link_bw)
 413                 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
 414                                   &rate_select, 1);
 415
 416         link_config[0] = 0;
 417         link_config[1] = DP_SET_ANSI_8B10B;
 418         drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 419
 420         intel_dp->DP |= DP_PORT_EN;
 421
 422         return true;
 423 }
 424
 425 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
 426                                                         enum drm_dp_phy dp_phy)
 427 {
 428         if (dp_phy == DP_PHY_DPRX)
 429                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
 430         else
 431                 drm_dp_lttpr_link_train_clock_recovery_delay();
 432 }
 433
 434 /*
 435  * Perform the link training clock recovery phase on the given DP PHY using
 436  * training pattern 1.
 437  */
 438 static bool
 439 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 440                                       const struct intel_crtc_state *crtc_state,
 441                                       enum drm_dp_phy dp_phy)
 442 {
 443         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 444         u8 voltage;
 445         int voltage_tries, cr_tries, max_cr_tries;
 446         bool max_vswing_reached = false;
 447
 448         /* clock recovery */
 449         if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
 450                                        DP_TRAINING_PATTERN_1 |
 451                                        DP_LINK_SCRAMBLING_DISABLE)) {
 452                 drm_err(&i915->drm, "failed to enable link training\n");
 453                 return false;
 454         }
 455
 456         /*
 457          * The DP 1.4 spec defines the max clock recovery retries value
 458          * as 10 but for pre-DP 1.4 devices we set a very tolerant
 459          * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 460          * x 5 identical voltage retries). Since the previous specs didn't
 461          * define a limit and created the possibility of an infinite loop
 462          * we want to prevent any sync from triggering that corner case.
 463          */
 464         if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 465                 max_cr_tries = 10;
 466         else
 467                 max_cr_tries = 80;
 468
 469         voltage_tries = 1;
 470         for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 471                 u8 link_status[DP_LINK_STATUS_SIZE];
 472
 473                 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
 474
 475                 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 476                                                      link_status) < 0) {
 477                         drm_err(&i915->drm, "failed to get link status\n");
 478                         return false;
 479                 }
 480
 481                 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 482                         drm_dbg_kms(&i915->drm, "clock recovery OK\n");
 483                         return true;
 484                 }
 485
 486                 if (voltage_tries == 5) {
 487                         drm_dbg_kms(&i915->drm,
 488                                     "Same voltage tried 5 times\n");
 489                         return false;
 490                 }
 491
 492                 if (max_vswing_reached) {
 493                         drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
 494                         return false;
 495                 }
 496
 497                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
 498
 499                 /* Update training set as requested by target */
 500                 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
 501                                           link_status);
 502                 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 503                         drm_err(&i915->drm,
 504                                 "failed to update link training\n");
 505                         return false;
 506                 }
 507
 508                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
 509                     voltage)
 510                         ++voltage_tries;
 511                 else
 512                         voltage_tries = 1;
 513
 514                 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 515                         max_vswing_reached = true;
 516
 517         }
 518         drm_err(&i915->drm,
 519                 "Failed clock recovery %d times, giving up!\n", max_cr_tries);
 520         return false;
 521 }
 522
 523 /*
 524  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
 525  * or for 1.4 devices that support it, training Pattern 3 for HBR2
 526  * or 1.2 devices that support it, Training Pattern 2 otherwise.
 527  */
 528 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 529                                      const struct intel_crtc_state *crtc_state,
 530                                      enum drm_dp_phy dp_phy)
 531 {
 532         bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 533
 534         /*
 535          * Intel platforms that support HBR3 also support TPS4. It is mandatory
 536          * for all downstream devices that support HBR3. There are no known eDP
 537          * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
 538          * specification.
 539          * LTTPRs must support TPS4.
 540          */
 541         source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
 542         sink_tps4 = dp_phy != DP_PHY_DPRX ||
 543                     drm_dp_tps4_supported(intel_dp->dpcd);
 544         if (source_tps4 && sink_tps4) {
 545                 return DP_TRAINING_PATTERN_4;
 546         } else if (crtc_state->port_clock == 810000) {
 547                 if (!source_tps4)
 548                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 549                                     "8.1 Gbps link rate without source HBR3/TPS4 support\n");
 550                 if (!sink_tps4)
 551                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 552                                     "8.1 Gbps link rate without sink TPS4 support\n");
 553         }
 554         /*
 555          * Intel platforms that support HBR2 also support TPS3. TPS3 support is
 556          * also mandatory for downstream devices that support HBR2. However, not
 557          * all sinks follow the spec.
 558          */
 559         source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
 560         sink_tps3 = dp_phy != DP_PHY_DPRX ||
 561                     drm_dp_tps3_supported(intel_dp->dpcd);
 562         if (source_tps3 && sink_tps3) {
 563                 return  DP_TRAINING_PATTERN_3;
 564         } else if (crtc_state->port_clock >= 540000) {
 565                 if (!source_tps3)
 566                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 567                                     ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
 568                 if (!sink_tps3)
 569                         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 570                                     ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
 571         }
 572
 573         return DP_TRAINING_PATTERN_2;
 574 }
 575
 576 static void
 577 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
 578                                                   enum drm_dp_phy dp_phy)
 579 {
 580         if (dp_phy == DP_PHY_DPRX) {
 581                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
 582         } else {
 583                 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 584
 585                 drm_dp_lttpr_link_train_channel_eq_delay(phy_caps);
 586         }
 587 }
 588
 589 /*
 590  * Perform the link training channel equalization phase on the given DP PHY
 591  * using one of training pattern 2, 3 or 4 depending on the source and
 592  * sink capabilities.
 593  */
 594 static bool
 595 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 596                                             const struct intel_crtc_state *crtc_state,
 597                                             enum drm_dp_phy dp_phy)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         int tries;
 601         u32 training_pattern;
 602         u8 link_status[DP_LINK_STATUS_SIZE];
 603         bool channel_eq = false;
 604
 605         training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
 606         /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
 607         if (training_pattern != DP_TRAINING_PATTERN_4)
 608                 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
 609
 610         /* channel equalization */
 611         if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
 612                                      training_pattern)) {
 613                 drm_err(&i915->drm, "failed to start channel equalization\n");
 614                 return false;
 615         }
 616
 617         for (tries = 0; tries < 5; tries++) {
 618                 intel_dp_link_training_channel_equalization_delay(intel_dp,
 619                                                                   dp_phy);
 620                 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 621                                                      link_status) < 0) {
 622                         drm_err(&i915->drm,
 623                                 "failed to get link status\n");
 624                         break;
 625                 }
 626
 627                 /* Make sure clock is still ok */
 628                 if (!drm_dp_clock_recovery_ok(link_status,
 629                                               crtc_state->lane_count)) {
 630                         intel_dp_dump_link_status(link_status);
 631                         drm_dbg_kms(&i915->drm,
 632                                     "Clock recovery check failed, cannot "
 633                                     "continue channel equalization\n");
 634                         break;
 635                 }
 636
 637                 if (drm_dp_channel_eq_ok(link_status,
 638                                          crtc_state->lane_count)) {
 639                         channel_eq = true;
 640                         drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
 641                                     "successful\n");
 642                         break;
 643                 }
 644
 645                 /* Update training set as requested by target */
 646                 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
 647                                           link_status);
 648                 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 649                         drm_err(&i915->drm,
 650                                 "failed to update link training\n");
 651                         break;
 652                 }
 653         }
 654
 655         /* Try 5 times, else fail and try at lower BW */
 656         if (tries == 5) {
 657                 intel_dp_dump_link_status(link_status);
 658                 drm_dbg_kms(&i915->drm,
 659                             "Channel equalization failed 5 times\n");
 660         }
 661
 662         return channel_eq;
 663 }
 664
 665 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
 666                                                    enum drm_dp_phy dp_phy)
 667 {
 668         int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 669         u8 val = DP_TRAINING_PATTERN_DISABLE;
 670
 671         return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
 672 }
 673
 674 /**
 675  * intel_dp_stop_link_train - stop link training
 676  * @intel_dp: DP struct
 677  * @crtc_state: state for CRTC attached to the encoder
 678  *
 679  * Stop the link training of the @intel_dp port, disabling the test pattern
 680  * symbol generation on the port and disabling the training pattern in
 681  * the sink's DPCD.
 682  *
 683  * What symbols are output on the port after this point is
 684  * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
 685  * with the pipe being disabled, on older platforms it's HW specific if/how an
 686  * idle pattern is generated, as the pipe is already enabled here for those.
 687  *
 688  * This function must be called after intel_dp_start_link_train().
 689  */
 690 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
 691                               const struct intel_crtc_state *crtc_state)
 692 {
 693         intel_dp->link_trained = true;
 694
 695         intel_dp_program_link_training_pattern(intel_dp,
 696                                                crtc_state,
 697                                                DP_TRAINING_PATTERN_DISABLE);
 698         intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
 699 }
 700
 701 static bool
 702 intel_dp_link_train_phy(struct intel_dp *intel_dp,
 703                         const struct intel_crtc_state *crtc_state,
 704                         enum drm_dp_phy dp_phy)
 705 {
 706         struct intel_connector *intel_connector = intel_dp->attached_connector;
 707         char phy_name[10];
 708         bool ret = false;
 709
 710         if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
 711                 goto out;
 712
 713         if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
 714                 goto out;
 715
 716         ret = true;
 717
 718 out:
 719         drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 720                     "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s",
 721                     intel_connector->base.base.id,
 722                     intel_connector->base.name,
 723                     ret ? "passed" : "failed",
 724                     crtc_state->port_clock, crtc_state->lane_count,
 725                     intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
 726
 727         return ret;
 728 }
 729
 730 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
 731                                                      const struct intel_crtc_state *crtc_state)
 732 {
 733         struct intel_connector *intel_connector = intel_dp->attached_connector;
 734
 735         if (intel_dp->hobl_active) {
 736                 drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
 737                             "Link Training failed with HOBL active, not enabling it from now on");
 738                 intel_dp->hobl_failed = true;
 739         } else if (intel_dp_get_link_train_fallback_values(intel_dp,
 740                                                            crtc_state->port_clock,
 741                                                            crtc_state->lane_count)) {
 742                 return;
 743         }
 744
 745         /* Schedule a Hotplug Uevent to userspace to start modeset */
 746         schedule_work(&intel_connector->modeset_retry_work);
 747 }
 748
 749 /* Perform the link training on all LTTPRs and the DPRX on a link. */
 750 static bool
 751 intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
 752                              const struct intel_crtc_state *crtc_state,
 753                              int lttpr_count)
 754 {
 755         bool ret = true;
 756         int i;
 757
 758         intel_dp_prepare_link_train(intel_dp, crtc_state);
 759
 760         for (i = lttpr_count - 1; i >= 0; i--) {
 761                 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
 762
 763                 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
 764                 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
 765
 766                 if (!ret)
 767                         break;
 768         }
 769
 770         if (ret)
 771                 intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
 772
 773         if (intel_dp->set_idle_link_train)
 774                 intel_dp->set_idle_link_train(intel_dp, crtc_state);
 775
 776         return ret;
 777 }
 778
 779 /**
 780  * intel_dp_start_link_train - start link training
 781  * @intel_dp: DP struct
 782  * @crtc_state: state for CRTC attached to the encoder
 783  *
 784  * Start the link training of the @intel_dp port, scheduling a fallback
 785  * retraining with reduced link rate/lane parameters if the link training
 786  * fails.
 787  * After calling this function intel_dp_stop_link_train() must be called.
 788  */
 789 void intel_dp_start_link_train(struct intel_dp *intel_dp,
 790                                const struct intel_crtc_state *crtc_state)
 791 {
 792         /*
 793          * TODO: Reiniting LTTPRs here won't be needed once proper connector
 794          * HW state readout is added.
 795          */
 796         int lttpr_count = intel_dp_lttpr_init(intel_dp);
 797
 798         if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
 799                 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
 800 }