drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_drv.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "atom.h"
  31 #include <linux/pci.h>
  32 #include <linux/hwmon.h>
  33 #include <linux/hwmon-sysfs.h>
  34 #include <linux/nospec.h>
  35 #include <linux/pm_runtime.h>
  36 #include <asm/processor.h>
  37 #include "hwmgr.h"
  38
  39 static const struct cg_flag_name clocks[] = {
  40         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  42         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  43         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  48         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  51         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  52         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  54         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  56         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  57         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  59         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  60         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  62         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  63         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  65         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  67         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  68         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  69         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  70
  71         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  72         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  73         {0, NULL},
  74 };
  75
  76 static const struct hwmon_temp_label {
  77         enum PP_HWMON_TEMP channel;
  78         const char *label;
  79 } temp_label[] = {
  80         {PP_TEMP_EDGE, "edge"},
  81         {PP_TEMP_JUNCTION, "junction"},
  82         {PP_TEMP_MEM, "mem"},
  83 };
  84
  85 /**
  86  * DOC: power_dpm_state
  87  *
  88  * The power_dpm_state file is a legacy interface and is only provided for
  89  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  90  * certain power related parameters.  The file power_dpm_state is used for this.
  91  * It accepts the following arguments:
  92  *
  93  * - battery
  94  *
  95  * - balanced
  96  *
  97  * - performance
  98  *
  99  * battery
 100  *
 101  * On older GPUs, the vbios provided a special power state for battery
 102  * operation.  Selecting battery switched to this state.  This is no
 103  * longer provided on newer GPUs so the option does nothing in that case.
 104  *
 105  * balanced
 106  *
 107  * On older GPUs, the vbios provided a special power state for balanced
 108  * operation.  Selecting balanced switched to this state.  This is no
 109  * longer provided on newer GPUs so the option does nothing in that case.
 110  *
 111  * performance
 112  *
 113  * On older GPUs, the vbios provided a special power state for performance
 114  * operation.  Selecting performance switched to this state.  This is no
 115  * longer provided on newer GPUs so the option does nothing in that case.
 116  *
 117  */
 118
 119 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 120                                           struct device_attribute *attr,
 121                                           char *buf)
 122 {
 123         struct drm_device *ddev = dev_get_drvdata(dev);
 124         struct amdgpu_device *adev = drm_to_adev(ddev);
 125         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 126         enum amd_pm_state_type pm;
 127         int ret;
 128
 129         if (amdgpu_in_reset(adev))
 130                 return -EPERM;
 131         if (adev->in_suspend && !adev->in_runpm)
 132                 return -EPERM;
 133
 134         ret = pm_runtime_get_sync(ddev->dev);
 135         if (ret < 0) {
 136                 pm_runtime_put_autosuspend(ddev->dev);
 137                 return ret;
 138         }
 139
 140         if (pp_funcs->get_current_power_state) {
 141                 pm = amdgpu_dpm_get_current_power_state(adev);
 142         } else {
 143                 pm = adev->pm.dpm.user_state;
 144         }
 145
 146         pm_runtime_mark_last_busy(ddev->dev);
 147         pm_runtime_put_autosuspend(ddev->dev);
 148
 149         return sysfs_emit(buf, "%s\n",
 150                           (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 151                           (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 152 }
 153
 154 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 155                                           struct device_attribute *attr,
 156                                           const char *buf,
 157                                           size_t count)
 158 {
 159         struct drm_device *ddev = dev_get_drvdata(dev);
 160         struct amdgpu_device *adev = drm_to_adev(ddev);
 161         enum amd_pm_state_type  state;
 162         int ret;
 163
 164         if (amdgpu_in_reset(adev))
 165                 return -EPERM;
 166         if (adev->in_suspend && !adev->in_runpm)
 167                 return -EPERM;
 168
 169         if (strncmp("battery", buf, strlen("battery")) == 0)
 170                 state = POWER_STATE_TYPE_BATTERY;
 171         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 172                 state = POWER_STATE_TYPE_BALANCED;
 173         else if (strncmp("performance", buf, strlen("performance")) == 0)
 174                 state = POWER_STATE_TYPE_PERFORMANCE;
 175         else
 176                 return -EINVAL;
 177
 178         ret = pm_runtime_get_sync(ddev->dev);
 179         if (ret < 0) {
 180                 pm_runtime_put_autosuspend(ddev->dev);
 181                 return ret;
 182         }
 183
 184         if (is_support_sw_smu(adev)) {
 185                 mutex_lock(&adev->pm.mutex);
 186                 adev->pm.dpm.user_state = state;
 187                 mutex_unlock(&adev->pm.mutex);
 188         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 189                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 190         } else {
 191                 mutex_lock(&adev->pm.mutex);
 192                 adev->pm.dpm.user_state = state;
 193                 mutex_unlock(&adev->pm.mutex);
 194
 195                 amdgpu_pm_compute_clocks(adev);
 196         }
 197         pm_runtime_mark_last_busy(ddev->dev);
 198         pm_runtime_put_autosuspend(ddev->dev);
 199
 200         return count;
 201 }
 202
 203
 204 /**
 205  * DOC: power_dpm_force_performance_level
 206  *
 207  * The amdgpu driver provides a sysfs API for adjusting certain power
 208  * related parameters.  The file power_dpm_force_performance_level is
 209  * used for this.  It accepts the following arguments:
 210  *
 211  * - auto
 212  *
 213  * - low
 214  *
 215  * - high
 216  *
 217  * - manual
 218  *
 219  * - profile_standard
 220  *
 221  * - profile_min_sclk
 222  *
 223  * - profile_min_mclk
 224  *
 225  * - profile_peak
 226  *
 227  * auto
 228  *
 229  * When auto is selected, the driver will attempt to dynamically select
 230  * the optimal power profile for current conditions in the driver.
 231  *
 232  * low
 233  *
 234  * When low is selected, the clocks are forced to the lowest power state.
 235  *
 236  * high
 237  *
 238  * When high is selected, the clocks are forced to the highest power state.
 239  *
 240  * manual
 241  *
 242  * When manual is selected, the user can manually adjust which power states
 243  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 244  * and pp_dpm_pcie files and adjust the power state transition heuristics
 245  * via the pp_power_profile_mode sysfs file.
 246  *
 247  * profile_standard
 248  * profile_min_sclk
 249  * profile_min_mclk
 250  * profile_peak
 251  *
 252  * When the profiling modes are selected, clock and power gating are
 253  * disabled and the clocks are set for different profiling cases. This
 254  * mode is recommended for profiling specific work loads where you do
 255  * not want clock or power gating for clock fluctuation to interfere
 256  * with your results. profile_standard sets the clocks to a fixed clock
 257  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 258  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 259  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 260  *
 261  */
 262
 263 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 264                                                             struct device_attribute *attr,
 265                                                             char *buf)
 266 {
 267         struct drm_device *ddev = dev_get_drvdata(dev);
 268         struct amdgpu_device *adev = drm_to_adev(ddev);
 269         enum amd_dpm_forced_level level = 0xff;
 270         int ret;
 271
 272         if (amdgpu_in_reset(adev))
 273                 return -EPERM;
 274         if (adev->in_suspend && !adev->in_runpm)
 275                 return -EPERM;
 276
 277         ret = pm_runtime_get_sync(ddev->dev);
 278         if (ret < 0) {
 279                 pm_runtime_put_autosuspend(ddev->dev);
 280                 return ret;
 281         }
 282
 283         if (adev->powerplay.pp_funcs->get_performance_level)
 284                 level = amdgpu_dpm_get_performance_level(adev);
 285         else
 286                 level = adev->pm.dpm.forced_level;
 287
 288         pm_runtime_mark_last_busy(ddev->dev);
 289         pm_runtime_put_autosuspend(ddev->dev);
 290
 291         return sysfs_emit(buf, "%s\n",
 292                           (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 293                           (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 294                           (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 295                           (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 296                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 297                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 298                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 299                           (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 300                           (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 301                           "unknown");
 302 }
 303
 304 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 305                                                             struct device_attribute *attr,
 306                                                             const char *buf,
 307                                                             size_t count)
 308 {
 309         struct drm_device *ddev = dev_get_drvdata(dev);
 310         struct amdgpu_device *adev = drm_to_adev(ddev);
 311         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 312         enum amd_dpm_forced_level level;
 313         enum amd_dpm_forced_level current_level;
 314         int ret = 0;
 315
 316         if (amdgpu_in_reset(adev))
 317                 return -EPERM;
 318         if (adev->in_suspend && !adev->in_runpm)
 319                 return -EPERM;
 320
 321         if (strncmp("low", buf, strlen("low")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_LOW;
 323         } else if (strncmp("high", buf, strlen("high")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 325         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 327         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 329         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 331         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 333         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 335         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 337         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 338                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 339         } else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 340                 level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 341         }  else {
 342                 return -EINVAL;
 343         }
 344
 345         ret = pm_runtime_get_sync(ddev->dev);
 346         if (ret < 0) {
 347                 pm_runtime_put_autosuspend(ddev->dev);
 348                 return ret;
 349         }
 350
 351         if (pp_funcs->get_performance_level)
 352                 current_level = amdgpu_dpm_get_performance_level(adev);
 353         else
 354                 current_level = adev->pm.dpm.forced_level;
 355
 356         if (current_level == level) {
 357                 pm_runtime_mark_last_busy(ddev->dev);
 358                 pm_runtime_put_autosuspend(ddev->dev);
 359                 return count;
 360         }
 361
 362         if (adev->asic_type == CHIP_RAVEN) {
 363                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 364                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 365                                 amdgpu_gfx_off_ctrl(adev, false);
 366                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 367                                 amdgpu_gfx_off_ctrl(adev, true);
 368                 }
 369         }
 370
 371         /* profile_exit setting is valid only when current mode is in profile mode */
 372         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 373             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 374             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 375             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 376             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 377                 pr_err("Currently not in any profile mode!\n");
 378                 pm_runtime_mark_last_busy(ddev->dev);
 379                 pm_runtime_put_autosuspend(ddev->dev);
 380                 return -EINVAL;
 381         }
 382
 383         if (pp_funcs->force_performance_level) {
 384                 mutex_lock(&adev->pm.mutex);
 385                 if (adev->pm.dpm.thermal_active) {
 386                         mutex_unlock(&adev->pm.mutex);
 387                         pm_runtime_mark_last_busy(ddev->dev);
 388                         pm_runtime_put_autosuspend(ddev->dev);
 389                         return -EINVAL;
 390                 }
 391                 ret = amdgpu_dpm_force_performance_level(adev, level);
 392                 if (ret) {
 393                         mutex_unlock(&adev->pm.mutex);
 394                         pm_runtime_mark_last_busy(ddev->dev);
 395                         pm_runtime_put_autosuspend(ddev->dev);
 396                         return -EINVAL;
 397                 } else {
 398                         adev->pm.dpm.forced_level = level;
 399                 }
 400                 mutex_unlock(&adev->pm.mutex);
 401         }
 402         pm_runtime_mark_last_busy(ddev->dev);
 403         pm_runtime_put_autosuspend(ddev->dev);
 404
 405         return count;
 406 }
 407
 408 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 409                 struct device_attribute *attr,
 410                 char *buf)
 411 {
 412         struct drm_device *ddev = dev_get_drvdata(dev);
 413         struct amdgpu_device *adev = drm_to_adev(ddev);
 414         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 415         struct pp_states_info data;
 416         uint32_t i;
 417         int buf_len, ret;
 418
 419         if (amdgpu_in_reset(adev))
 420                 return -EPERM;
 421         if (adev->in_suspend && !adev->in_runpm)
 422                 return -EPERM;
 423
 424         ret = pm_runtime_get_sync(ddev->dev);
 425         if (ret < 0) {
 426                 pm_runtime_put_autosuspend(ddev->dev);
 427                 return ret;
 428         }
 429
 430         if (pp_funcs->get_pp_num_states) {
 431                 amdgpu_dpm_get_pp_num_states(adev, &data);
 432         } else {
 433                 memset(&data, 0, sizeof(data));
 434         }
 435
 436         pm_runtime_mark_last_busy(ddev->dev);
 437         pm_runtime_put_autosuspend(ddev->dev);
 438
 439         buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 440         for (i = 0; i < data.nums; i++)
 441                 buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 442                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 443                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 444                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 445                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 446
 447         return buf_len;
 448 }
 449
 450 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 451                 struct device_attribute *attr,
 452                 char *buf)
 453 {
 454         struct drm_device *ddev = dev_get_drvdata(dev);
 455         struct amdgpu_device *adev = drm_to_adev(ddev);
 456         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
 457         struct pp_states_info data = {0};
 458         enum amd_pm_state_type pm = 0;
 459         int i = 0, ret = 0;
 460
 461         if (amdgpu_in_reset(adev))
 462                 return -EPERM;
 463         if (adev->in_suspend && !adev->in_runpm)
 464                 return -EPERM;
 465
 466         ret = pm_runtime_get_sync(ddev->dev);
 467         if (ret < 0) {
 468                 pm_runtime_put_autosuspend(ddev->dev);
 469                 return ret;
 470         }
 471
 472         if (pp_funcs->get_current_power_state
 473                  && pp_funcs->get_pp_num_states) {
 474                 pm = amdgpu_dpm_get_current_power_state(adev);
 475                 amdgpu_dpm_get_pp_num_states(adev, &data);
 476         }
 477
 478         pm_runtime_mark_last_busy(ddev->dev);
 479         pm_runtime_put_autosuspend(ddev->dev);
 480
 481         for (i = 0; i < data.nums; i++) {
 482                 if (pm == data.states[i])
 483                         break;
 484         }
 485
 486         if (i == data.nums)
 487                 i = -EINVAL;
 488
 489         return sysfs_emit(buf, "%d\n", i);
 490 }
 491
 492 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 493                 struct device_attribute *attr,
 494                 char *buf)
 495 {
 496         struct drm_device *ddev = dev_get_drvdata(dev);
 497         struct amdgpu_device *adev = drm_to_adev(ddev);
 498
 499         if (amdgpu_in_reset(adev))
 500                 return -EPERM;
 501         if (adev->in_suspend && !adev->in_runpm)
 502                 return -EPERM;
 503
 504         if (adev->pp_force_state_enabled)
 505                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 506         else
 507                 return sysfs_emit(buf, "\n");
 508 }
 509
 510 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 511                 struct device_attribute *attr,
 512                 const char *buf,
 513                 size_t count)
 514 {
 515         struct drm_device *ddev = dev_get_drvdata(dev);
 516         struct amdgpu_device *adev = drm_to_adev(ddev);
 517         enum amd_pm_state_type state = 0;
 518         unsigned long idx;
 519         int ret;
 520
 521         if (amdgpu_in_reset(adev))
 522                 return -EPERM;
 523         if (adev->in_suspend && !adev->in_runpm)
 524                 return -EPERM;
 525
 526         if (strlen(buf) == 1)
 527                 adev->pp_force_state_enabled = false;
 528         else if (is_support_sw_smu(adev))
 529                 adev->pp_force_state_enabled = false;
 530         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 531                         adev->powerplay.pp_funcs->get_pp_num_states) {
 532                 struct pp_states_info data;
 533
 534                 ret = kstrtoul(buf, 0, &idx);
 535                 if (ret || idx >= ARRAY_SIZE(data.states))
 536                         return -EINVAL;
 537
 538                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 539
 540                 amdgpu_dpm_get_pp_num_states(adev, &data);
 541                 state = data.states[idx];
 542
 543                 ret = pm_runtime_get_sync(ddev->dev);
 544                 if (ret < 0) {
 545                         pm_runtime_put_autosuspend(ddev->dev);
 546                         return ret;
 547                 }
 548
 549                 /* only set user selected power states */
 550                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 551                     state != POWER_STATE_TYPE_DEFAULT) {
 552                         amdgpu_dpm_dispatch_task(adev,
 553                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 554                         adev->pp_force_state_enabled = true;
 555                 }
 556                 pm_runtime_mark_last_busy(ddev->dev);
 557                 pm_runtime_put_autosuspend(ddev->dev);
 558         }
 559
 560         return count;
 561 }
 562
 563 /**
 564  * DOC: pp_table
 565  *
 566  * The amdgpu driver provides a sysfs API for uploading new powerplay
 567  * tables.  The file pp_table is used for this.  Reading the file
 568  * will dump the current power play table.  Writing to the file
 569  * will attempt to upload a new powerplay table and re-initialize
 570  * powerplay using that new table.
 571  *
 572  */
 573
 574 static ssize_t amdgpu_get_pp_table(struct device *dev,
 575                 struct device_attribute *attr,
 576                 char *buf)
 577 {
 578         struct drm_device *ddev = dev_get_drvdata(dev);
 579         struct amdgpu_device *adev = drm_to_adev(ddev);
 580         char *table = NULL;
 581         int size, ret;
 582
 583         if (amdgpu_in_reset(adev))
 584                 return -EPERM;
 585         if (adev->in_suspend && !adev->in_runpm)
 586                 return -EPERM;
 587
 588         ret = pm_runtime_get_sync(ddev->dev);
 589         if (ret < 0) {
 590                 pm_runtime_put_autosuspend(ddev->dev);
 591                 return ret;
 592         }
 593
 594         if (adev->powerplay.pp_funcs->get_pp_table) {
 595                 size = amdgpu_dpm_get_pp_table(adev, &table);
 596                 pm_runtime_mark_last_busy(ddev->dev);
 597                 pm_runtime_put_autosuspend(ddev->dev);
 598                 if (size < 0)
 599                         return size;
 600         } else {
 601                 pm_runtime_mark_last_busy(ddev->dev);
 602                 pm_runtime_put_autosuspend(ddev->dev);
 603                 return 0;
 604         }
 605
 606         if (size >= PAGE_SIZE)
 607                 size = PAGE_SIZE - 1;
 608
 609         memcpy(buf, table, size);
 610
 611         return size;
 612 }
 613
 614 static ssize_t amdgpu_set_pp_table(struct device *dev,
 615                 struct device_attribute *attr,
 616                 const char *buf,
 617                 size_t count)
 618 {
 619         struct drm_device *ddev = dev_get_drvdata(dev);
 620         struct amdgpu_device *adev = drm_to_adev(ddev);
 621         int ret = 0;
 622
 623         if (amdgpu_in_reset(adev))
 624                 return -EPERM;
 625         if (adev->in_suspend && !adev->in_runpm)
 626                 return -EPERM;
 627
 628         ret = pm_runtime_get_sync(ddev->dev);
 629         if (ret < 0) {
 630                 pm_runtime_put_autosuspend(ddev->dev);
 631                 return ret;
 632         }
 633
 634         ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 635         if (ret) {
 636                 pm_runtime_mark_last_busy(ddev->dev);
 637                 pm_runtime_put_autosuspend(ddev->dev);
 638                 return ret;
 639         }
 640
 641         pm_runtime_mark_last_busy(ddev->dev);
 642         pm_runtime_put_autosuspend(ddev->dev);
 643
 644         return count;
 645 }
 646
 647 /**
 648  * DOC: pp_od_clk_voltage
 649  *
 650  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 651  * in each power level within a power state.  The pp_od_clk_voltage is used for
 652  * this.
 653  *
 654  * Note that the actual memory controller clock rate are exposed, not
 655  * the effective memory clock of the DRAMs. To translate it, use the
 656  * following formula:
 657  *
 658  * Clock conversion (Mhz):
 659  *
 660  * HBM: effective_memory_clock = memory_controller_clock * 1
 661  *
 662  * G5: effective_memory_clock = memory_controller_clock * 1
 663  *
 664  * G6: effective_memory_clock = memory_controller_clock * 2
 665  *
 666  * DRAM data rate (MT/s):
 667  *
 668  * HBM: effective_memory_clock * 2 = data_rate
 669  *
 670  * G5: effective_memory_clock * 4 = data_rate
 671  *
 672  * G6: effective_memory_clock * 8 = data_rate
 673  *
 674  * Bandwidth (MB/s):
 675  *
 676  * data_rate * vram_bit_width / 8 = memory_bandwidth
 677  *
 678  * Some examples:
 679  *
 680  * G5 on RX460:
 681  *
 682  * memory_controller_clock = 1750 Mhz
 683  *
 684  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 685  *
 686  * data rate = 1750 * 4 = 7000 MT/s
 687  *
 688  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 689  *
 690  * G6 on RX5700:
 691  *
 692  * memory_controller_clock = 875 Mhz
 693  *
 694  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 695  *
 696  * data rate = 1750 * 8 = 14000 MT/s
 697  *
 698  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 699  *
 700  * < For Vega10 and previous ASICs >
 701  *
 702  * Reading the file will display:
 703  *
 704  * - a list of engine clock levels and voltages labeled OD_SCLK
 705  *
 706  * - a list of memory clock levels and voltages labeled OD_MCLK
 707  *
 708  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 709  *
 710  * To manually adjust these settings, first select manual using
 711  * power_dpm_force_performance_level. Enter a new value for each
 712  * level by writing a string that contains "s/m level clock voltage" to
 713  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 714  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 715  * 810 mV.  When you have edited all of the states as needed, write
 716  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 717  * default power levels, write "r" (reset) to the file to reset them.
 718  *
 719  *
 720  * < For Vega20 and newer ASICs >
 721  *
 722  * Reading the file will display:
 723  *
 724  * - minimum and maximum engine clock labeled OD_SCLK
 725  *
 726  * - minimum(not available for Vega20 and Navi1x) and maximum memory
 727  *   clock labeled OD_MCLK
 728  *
 729  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 730  *   They can be used to calibrate the sclk voltage curve.
 731  *
 732  * - voltage offset(in mV) applied on target voltage calculation.
 733  *   This is available for Sienna Cichlid, Navy Flounder and Dimgrey
 734  *   Cavefish. For these ASICs, the target voltage calculation can be
 735  *   illustrated by "voltage = voltage calculated from v/f curve +
 736  *   overdrive vddgfx offset"
 737  *
 738  * - a list of valid ranges for sclk, mclk, and voltage curve points
 739  *   labeled OD_RANGE
 740  *
 741  * < For APUs >
 742  *
 743  * Reading the file will display:
 744  *
 745  * - minimum and maximum engine clock labeled OD_SCLK
 746  *
 747  * - a list of valid ranges for sclk labeled OD_RANGE
 748  *
 749  * < For VanGogh >
 750  *
 751  * Reading the file will display:
 752  *
 753  * - minimum and maximum engine clock labeled OD_SCLK
 754  * - minimum and maximum core clocks labeled OD_CCLK
 755  *
 756  * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 757  *
 758  * To manually adjust these settings:
 759  *
 760  * - First select manual using power_dpm_force_performance_level
 761  *
 762  * - For clock frequency setting, enter a new value by writing a
 763  *   string that contains "s/m index clock" to the file. The index
 764  *   should be 0 if to set minimum clock. And 1 if to set maximum
 765  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 766  *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 767  *   clocks on VanGogh, the string contains "p core index clock".
 768  *   E.g., "p 2 0 800" would set the minimum core clock on core
 769  *   2 to 800Mhz.
 770  *
 771  *   For sclk voltage curve, enter the new values by writing a
 772  *   string that contains "vc point clock voltage" to the file. The
 773  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 774  *   update point1 with clock set as 300Mhz and voltage as
 775  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 776  *   as 1000Mhz and voltage 1000mV.
 777  *
 778  *   To update the voltage offset applied for gfxclk/voltage calculation,
 779  *   enter the new value by writing a string that contains "vo offset".
 780  *   This is supported by Sienna Cichlid, Navy Flounder and Dimgrey Cavefish.
 781  *   And the offset can be a positive or negative value.
 782  *
 783  * - When you have edited all of the states as needed, write "c" (commit)
 784  *   to the file to commit your changes
 785  *
 786  * - If you want to reset to the default power levels, write "r" (reset)
 787  *   to the file to reset them
 788  *
 789  */
 790
 791 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 792                 struct device_attribute *attr,
 793                 const char *buf,
 794                 size_t count)
 795 {
 796         struct drm_device *ddev = dev_get_drvdata(dev);
 797         struct amdgpu_device *adev = drm_to_adev(ddev);
 798         int ret;
 799         uint32_t parameter_size = 0;
 800         long parameter[64];
 801         char buf_cpy[128];
 802         char *tmp_str;
 803         char *sub_str;
 804         const char delimiter[3] = {' ', '\n', '\0'};
 805         uint32_t type;
 806
 807         if (amdgpu_in_reset(adev))
 808                 return -EPERM;
 809         if (adev->in_suspend && !adev->in_runpm)
 810                 return -EPERM;
 811
 812         if (count > 127)
 813                 return -EINVAL;
 814
 815         if (*buf == 's')
 816                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 817         else if (*buf == 'p')
 818                 type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 819         else if (*buf == 'm')
 820                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 821         else if(*buf == 'r')
 822                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 823         else if (*buf == 'c')
 824                 type = PP_OD_COMMIT_DPM_TABLE;
 825         else if (!strncmp(buf, "vc", 2))
 826                 type = PP_OD_EDIT_VDDC_CURVE;
 827         else if (!strncmp(buf, "vo", 2))
 828                 type = PP_OD_EDIT_VDDGFX_OFFSET;
 829         else
 830                 return -EINVAL;
 831
 832         memcpy(buf_cpy, buf, count+1);
 833
 834         tmp_str = buf_cpy;
 835
 836         if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 837              (type == PP_OD_EDIT_VDDGFX_OFFSET))
 838                 tmp_str++;
 839         while (isspace(*++tmp_str));
 840
 841         while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 842                 if (strlen(sub_str) == 0)
 843                         continue;
 844                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 845                 if (ret)
 846                         return -EINVAL;
 847                 parameter_size++;
 848
 849                 while (isspace(*tmp_str))
 850                         tmp_str++;
 851         }
 852
 853         ret = pm_runtime_get_sync(ddev->dev);
 854         if (ret < 0) {
 855                 pm_runtime_put_autosuspend(ddev->dev);
 856                 return ret;
 857         }
 858
 859         if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
 860                 ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
 861                                                         parameter,
 862                                                         parameter_size);
 863                 if (ret) {
 864                         pm_runtime_mark_last_busy(ddev->dev);
 865                         pm_runtime_put_autosuspend(ddev->dev);
 866                         return -EINVAL;
 867                 }
 868         }
 869
 870         if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 871                 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 872                                                     parameter, parameter_size);
 873                 if (ret) {
 874                         pm_runtime_mark_last_busy(ddev->dev);
 875                         pm_runtime_put_autosuspend(ddev->dev);
 876                         return -EINVAL;
 877                 }
 878         }
 879
 880         if (type == PP_OD_COMMIT_DPM_TABLE) {
 881                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
 882                         amdgpu_dpm_dispatch_task(adev,
 883                                                  AMD_PP_TASK_READJUST_POWER_STATE,
 884                                                  NULL);
 885                         pm_runtime_mark_last_busy(ddev->dev);
 886                         pm_runtime_put_autosuspend(ddev->dev);
 887                         return count;
 888                 } else {
 889                         pm_runtime_mark_last_busy(ddev->dev);
 890                         pm_runtime_put_autosuspend(ddev->dev);
 891                         return -EINVAL;
 892                 }
 893         }
 894
 895         pm_runtime_mark_last_busy(ddev->dev);
 896         pm_runtime_put_autosuspend(ddev->dev);
 897
 898         return count;
 899 }
 900
 901 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 902                 struct device_attribute *attr,
 903                 char *buf)
 904 {
 905         struct drm_device *ddev = dev_get_drvdata(dev);
 906         struct amdgpu_device *adev = drm_to_adev(ddev);
 907         ssize_t size;
 908         int ret;
 909
 910         if (amdgpu_in_reset(adev))
 911                 return -EPERM;
 912         if (adev->in_suspend && !adev->in_runpm)
 913                 return -EPERM;
 914
 915         ret = pm_runtime_get_sync(ddev->dev);
 916         if (ret < 0) {
 917                 pm_runtime_put_autosuspend(ddev->dev);
 918                 return ret;
 919         }
 920
 921         if (adev->powerplay.pp_funcs->print_clock_levels) {
 922                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 923                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 924                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 925                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf+size);
 926                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 927                 size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf+size);
 928         } else {
 929                 size = sysfs_emit(buf, "\n");
 930         }
 931         pm_runtime_mark_last_busy(ddev->dev);
 932         pm_runtime_put_autosuspend(ddev->dev);
 933
 934         return size;
 935 }
 936
 937 /**
 938  * DOC: pp_features
 939  *
 940  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 941  * features to be enabled. The file pp_features is used for this. And
 942  * this is only available for Vega10 and later dGPUs.
 943  *
 944  * Reading back the file will show you the followings:
 945  * - Current ppfeature masks
 946  * - List of the all supported powerplay features with their naming,
 947  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 948  *
 949  * To manually enable or disable a specific feature, just set or clear
 950  * the corresponding bit from original ppfeature masks and input the
 951  * new ppfeature masks.
 952  */
 953 static ssize_t amdgpu_set_pp_features(struct device *dev,
 954                                       struct device_attribute *attr,
 955                                       const char *buf,
 956                                       size_t count)
 957 {
 958         struct drm_device *ddev = dev_get_drvdata(dev);
 959         struct amdgpu_device *adev = drm_to_adev(ddev);
 960         uint64_t featuremask;
 961         int ret;
 962
 963         if (amdgpu_in_reset(adev))
 964                 return -EPERM;
 965         if (adev->in_suspend && !adev->in_runpm)
 966                 return -EPERM;
 967
 968         ret = kstrtou64(buf, 0, &featuremask);
 969         if (ret)
 970                 return -EINVAL;
 971
 972         ret = pm_runtime_get_sync(ddev->dev);
 973         if (ret < 0) {
 974                 pm_runtime_put_autosuspend(ddev->dev);
 975                 return ret;
 976         }
 977
 978         if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 979                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 980                 if (ret) {
 981                         pm_runtime_mark_last_busy(ddev->dev);
 982                         pm_runtime_put_autosuspend(ddev->dev);
 983                         return -EINVAL;
 984                 }
 985         }
 986         pm_runtime_mark_last_busy(ddev->dev);
 987         pm_runtime_put_autosuspend(ddev->dev);
 988
 989         return count;
 990 }
 991
 992 static ssize_t amdgpu_get_pp_features(struct device *dev,
 993                                       struct device_attribute *attr,
 994                                       char *buf)
 995 {
 996         struct drm_device *ddev = dev_get_drvdata(dev);
 997         struct amdgpu_device *adev = drm_to_adev(ddev);
 998         ssize_t size;
 999         int ret;
1000
1001         if (amdgpu_in_reset(adev))
1002                 return -EPERM;
1003         if (adev->in_suspend && !adev->in_runpm)
1004                 return -EPERM;
1005
1006         ret = pm_runtime_get_sync(ddev->dev);
1007         if (ret < 0) {
1008                 pm_runtime_put_autosuspend(ddev->dev);
1009                 return ret;
1010         }
1011
1012         if (adev->powerplay.pp_funcs->get_ppfeature_status)
1013                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
1014         else
1015                 size = sysfs_emit(buf, "\n");
1016
1017         pm_runtime_mark_last_busy(ddev->dev);
1018         pm_runtime_put_autosuspend(ddev->dev);
1019
1020         return size;
1021 }
1022
1023 /**
1024  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1025  *
1026  * The amdgpu driver provides a sysfs API for adjusting what power levels
1027  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1028  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1029  * this.
1030  *
1031  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1032  * Vega10 and later ASICs.
1033  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1034  *
1035  * Reading back the files will show you the available power levels within
1036  * the power state and the clock information for those levels.
1037  *
1038  * To manually adjust these states, first select manual using
1039  * power_dpm_force_performance_level.
1040  * Secondly, enter a new value for each level by inputing a string that
1041  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1042  * E.g.,
1043  *
1044  * .. code-block:: bash
1045  *
1046  *      echo "4 5 6" > pp_dpm_sclk
1047  *
1048  * will enable sclk levels 4, 5, and 6.
1049  *
1050  * NOTE: change to the dcefclk max dpm level is not supported now
1051  */
1052
1053 static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1054                 enum pp_clock_type type,
1055                 char *buf)
1056 {
1057         struct drm_device *ddev = dev_get_drvdata(dev);
1058         struct amdgpu_device *adev = drm_to_adev(ddev);
1059         ssize_t size;
1060         int ret;
1061
1062         if (amdgpu_in_reset(adev))
1063                 return -EPERM;
1064         if (adev->in_suspend && !adev->in_runpm)
1065                 return -EPERM;
1066
1067         ret = pm_runtime_get_sync(ddev->dev);
1068         if (ret < 0) {
1069                 pm_runtime_put_autosuspend(ddev->dev);
1070                 return ret;
1071         }
1072
1073         if (adev->powerplay.pp_funcs->print_clock_levels)
1074                 size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1075         else
1076                 size = sysfs_emit(buf, "\n");
1077
1078         pm_runtime_mark_last_busy(ddev->dev);
1079         pm_runtime_put_autosuspend(ddev->dev);
1080
1081         return size;
1082 }
1083
1084 /*
1085  * Worst case: 32 bits individually specified, in octal at 12 characters
1086  * per line (+1 for \n).
1087  */
1088 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1089
1090 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1091 {
1092         int ret;
1093         unsigned long level;
1094         char *sub_str = NULL;
1095         char *tmp;
1096         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1097         const char delimiter[3] = {' ', '\n', '\0'};
1098         size_t bytes;
1099
1100         *mask = 0;
1101
1102         bytes = min(count, sizeof(buf_cpy) - 1);
1103         memcpy(buf_cpy, buf, bytes);
1104         buf_cpy[bytes] = '\0';
1105         tmp = buf_cpy;
1106         while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1107                 if (strlen(sub_str)) {
1108                         ret = kstrtoul(sub_str, 0, &level);
1109                         if (ret || level > 31)
1110                                 return -EINVAL;
1111                         *mask |= 1 << level;
1112                 } else
1113                         break;
1114         }
1115
1116         return 0;
1117 }
1118
1119 static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1120                 enum pp_clock_type type,
1121                 const char *buf,
1122                 size_t count)
1123 {
1124         struct drm_device *ddev = dev_get_drvdata(dev);
1125         struct amdgpu_device *adev = drm_to_adev(ddev);
1126         int ret;
1127         uint32_t mask = 0;
1128
1129         if (amdgpu_in_reset(adev))
1130                 return -EPERM;
1131         if (adev->in_suspend && !adev->in_runpm)
1132                 return -EPERM;
1133
1134         ret = amdgpu_read_mask(buf, count, &mask);
1135         if (ret)
1136                 return ret;
1137
1138         ret = pm_runtime_get_sync(ddev->dev);
1139         if (ret < 0) {
1140                 pm_runtime_put_autosuspend(ddev->dev);
1141                 return ret;
1142         }
1143
1144         if (adev->powerplay.pp_funcs->force_clock_level)
1145                 ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1146         else
1147                 ret = 0;
1148
1149         pm_runtime_mark_last_busy(ddev->dev);
1150         pm_runtime_put_autosuspend(ddev->dev);
1151
1152         if (ret)
1153                 return -EINVAL;
1154
1155         return count;
1156 }
1157
1158 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1159                 struct device_attribute *attr,
1160                 char *buf)
1161 {
1162         return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1163 }
1164
1165 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1166                 struct device_attribute *attr,
1167                 const char *buf,
1168                 size_t count)
1169 {
1170         return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1171 }
1172
1173 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1174                 struct device_attribute *attr,
1175                 char *buf)
1176 {
1177         return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1178 }
1179
1180 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1181                 struct device_attribute *attr,
1182                 const char *buf,
1183                 size_t count)
1184 {
1185         return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1186 }
1187
1188 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1189                 struct device_attribute *attr,
1190                 char *buf)
1191 {
1192         return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1193 }
1194
1195 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1196                 struct device_attribute *attr,
1197                 const char *buf,
1198                 size_t count)
1199 {
1200         return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1201 }
1202
1203 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1204                 struct device_attribute *attr,
1205                 char *buf)
1206 {
1207         return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1208 }
1209
1210 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1211                 struct device_attribute *attr,
1212                 const char *buf,
1213                 size_t count)
1214 {
1215         return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1216 }
1217
1218 static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1219                 struct device_attribute *attr,
1220                 char *buf)
1221 {
1222         return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1223 }
1224
1225 static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1226                 struct device_attribute *attr,
1227                 const char *buf,
1228                 size_t count)
1229 {
1230         return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1231 }
1232
1233 static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1234                 struct device_attribute *attr,
1235                 char *buf)
1236 {
1237         return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1238 }
1239
1240 static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1241                 struct device_attribute *attr,
1242                 const char *buf,
1243                 size_t count)
1244 {
1245         return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1246 }
1247
1248 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1249                 struct device_attribute *attr,
1250                 char *buf)
1251 {
1252         return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1253 }
1254
1255 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1256                 struct device_attribute *attr,
1257                 const char *buf,
1258                 size_t count)
1259 {
1260         return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1261 }
1262
1263 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1264                 struct device_attribute *attr,
1265                 char *buf)
1266 {
1267         return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1268 }
1269
1270 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1271                 struct device_attribute *attr,
1272                 const char *buf,
1273                 size_t count)
1274 {
1275         return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1276 }
1277
1278 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1279                 struct device_attribute *attr,
1280                 char *buf)
1281 {
1282         struct drm_device *ddev = dev_get_drvdata(dev);
1283         struct amdgpu_device *adev = drm_to_adev(ddev);
1284         uint32_t value = 0;
1285         int ret;
1286
1287         if (amdgpu_in_reset(adev))
1288                 return -EPERM;
1289         if (adev->in_suspend && !adev->in_runpm)
1290                 return -EPERM;
1291
1292         ret = pm_runtime_get_sync(ddev->dev);
1293         if (ret < 0) {
1294                 pm_runtime_put_autosuspend(ddev->dev);
1295                 return ret;
1296         }
1297
1298         if (is_support_sw_smu(adev))
1299                 value = 0;
1300         else if (adev->powerplay.pp_funcs->get_sclk_od)
1301                 value = amdgpu_dpm_get_sclk_od(adev);
1302
1303         pm_runtime_mark_last_busy(ddev->dev);
1304         pm_runtime_put_autosuspend(ddev->dev);
1305
1306         return sysfs_emit(buf, "%d\n", value);
1307 }
1308
1309 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1310                 struct device_attribute *attr,
1311                 const char *buf,
1312                 size_t count)
1313 {
1314         struct drm_device *ddev = dev_get_drvdata(dev);
1315         struct amdgpu_device *adev = drm_to_adev(ddev);
1316         int ret;
1317         long int value;
1318
1319         if (amdgpu_in_reset(adev))
1320                 return -EPERM;
1321         if (adev->in_suspend && !adev->in_runpm)
1322                 return -EPERM;
1323
1324         ret = kstrtol(buf, 0, &value);
1325
1326         if (ret)
1327                 return -EINVAL;
1328
1329         ret = pm_runtime_get_sync(ddev->dev);
1330         if (ret < 0) {
1331                 pm_runtime_put_autosuspend(ddev->dev);
1332                 return ret;
1333         }
1334
1335         if (is_support_sw_smu(adev)) {
1336                 value = 0;
1337         } else {
1338                 if (adev->powerplay.pp_funcs->set_sclk_od)
1339                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1340
1341                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1342                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1343                 } else {
1344                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1345                         amdgpu_pm_compute_clocks(adev);
1346                 }
1347         }
1348
1349         pm_runtime_mark_last_busy(ddev->dev);
1350         pm_runtime_put_autosuspend(ddev->dev);
1351
1352         return count;
1353 }
1354
1355 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1356                 struct device_attribute *attr,
1357                 char *buf)
1358 {
1359         struct drm_device *ddev = dev_get_drvdata(dev);
1360         struct amdgpu_device *adev = drm_to_adev(ddev);
1361         uint32_t value = 0;
1362         int ret;
1363
1364         if (amdgpu_in_reset(adev))
1365                 return -EPERM;
1366         if (adev->in_suspend && !adev->in_runpm)
1367                 return -EPERM;
1368
1369         ret = pm_runtime_get_sync(ddev->dev);
1370         if (ret < 0) {
1371                 pm_runtime_put_autosuspend(ddev->dev);
1372                 return ret;
1373         }
1374
1375         if (is_support_sw_smu(adev))
1376                 value = 0;
1377         else if (adev->powerplay.pp_funcs->get_mclk_od)
1378                 value = amdgpu_dpm_get_mclk_od(adev);
1379
1380         pm_runtime_mark_last_busy(ddev->dev);
1381         pm_runtime_put_autosuspend(ddev->dev);
1382
1383         return sysfs_emit(buf, "%d\n", value);
1384 }
1385
1386 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1387                 struct device_attribute *attr,
1388                 const char *buf,
1389                 size_t count)
1390 {
1391         struct drm_device *ddev = dev_get_drvdata(dev);
1392         struct amdgpu_device *adev = drm_to_adev(ddev);
1393         int ret;
1394         long int value;
1395
1396         if (amdgpu_in_reset(adev))
1397                 return -EPERM;
1398         if (adev->in_suspend && !adev->in_runpm)
1399                 return -EPERM;
1400
1401         ret = kstrtol(buf, 0, &value);
1402
1403         if (ret)
1404                 return -EINVAL;
1405
1406         ret = pm_runtime_get_sync(ddev->dev);
1407         if (ret < 0) {
1408                 pm_runtime_put_autosuspend(ddev->dev);
1409                 return ret;
1410         }
1411
1412         if (is_support_sw_smu(adev)) {
1413                 value = 0;
1414         } else {
1415                 if (adev->powerplay.pp_funcs->set_mclk_od)
1416                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1417
1418                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1419                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1420                 } else {
1421                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1422                         amdgpu_pm_compute_clocks(adev);
1423                 }
1424         }
1425
1426         pm_runtime_mark_last_busy(ddev->dev);
1427         pm_runtime_put_autosuspend(ddev->dev);
1428
1429         return count;
1430 }
1431
1432 /**
1433  * DOC: pp_power_profile_mode
1434  *
1435  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1436  * related to switching between power levels in a power state.  The file
1437  * pp_power_profile_mode is used for this.
1438  *
1439  * Reading this file outputs a list of all of the predefined power profiles
1440  * and the relevant heuristics settings for that profile.
1441  *
1442  * To select a profile or create a custom profile, first select manual using
1443  * power_dpm_force_performance_level.  Writing the number of a predefined
1444  * profile to pp_power_profile_mode will enable those heuristics.  To
1445  * create a custom set of heuristics, write a string of numbers to the file
1446  * starting with the number of the custom profile along with a setting
1447  * for each heuristic parameter.  Due to differences across asic families
1448  * the heuristic parameters vary from family to family.
1449  *
1450  */
1451
1452 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1453                 struct device_attribute *attr,
1454                 char *buf)
1455 {
1456         struct drm_device *ddev = dev_get_drvdata(dev);
1457         struct amdgpu_device *adev = drm_to_adev(ddev);
1458         ssize_t size;
1459         int ret;
1460
1461         if (amdgpu_in_reset(adev))
1462                 return -EPERM;
1463         if (adev->in_suspend && !adev->in_runpm)
1464                 return -EPERM;
1465
1466         ret = pm_runtime_get_sync(ddev->dev);
1467         if (ret < 0) {
1468                 pm_runtime_put_autosuspend(ddev->dev);
1469                 return ret;
1470         }
1471
1472         if (adev->powerplay.pp_funcs->get_power_profile_mode)
1473                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1474         else
1475                 size = sysfs_emit(buf, "\n");
1476
1477         pm_runtime_mark_last_busy(ddev->dev);
1478         pm_runtime_put_autosuspend(ddev->dev);
1479
1480         return size;
1481 }
1482
1483
1484 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1485                 struct device_attribute *attr,
1486                 const char *buf,
1487                 size_t count)
1488 {
1489         int ret;
1490         struct drm_device *ddev = dev_get_drvdata(dev);
1491         struct amdgpu_device *adev = drm_to_adev(ddev);
1492         uint32_t parameter_size = 0;
1493         long parameter[64];
1494         char *sub_str, buf_cpy[128];
1495         char *tmp_str;
1496         uint32_t i = 0;
1497         char tmp[2];
1498         long int profile_mode = 0;
1499         const char delimiter[3] = {' ', '\n', '\0'};
1500
1501         if (amdgpu_in_reset(adev))
1502                 return -EPERM;
1503         if (adev->in_suspend && !adev->in_runpm)
1504                 return -EPERM;
1505
1506         tmp[0] = *(buf);
1507         tmp[1] = '\0';
1508         ret = kstrtol(tmp, 0, &profile_mode);
1509         if (ret)
1510                 return -EINVAL;
1511
1512         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1513                 if (count < 2 || count > 127)
1514                         return -EINVAL;
1515                 while (isspace(*++buf))
1516                         i++;
1517                 memcpy(buf_cpy, buf, count-i);
1518                 tmp_str = buf_cpy;
1519                 while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1520                         if (strlen(sub_str) == 0)
1521                                 continue;
1522                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1523                         if (ret)
1524                                 return -EINVAL;
1525                         parameter_size++;
1526                         while (isspace(*tmp_str))
1527                                 tmp_str++;
1528                 }
1529         }
1530         parameter[parameter_size] = profile_mode;
1531
1532         ret = pm_runtime_get_sync(ddev->dev);
1533         if (ret < 0) {
1534                 pm_runtime_put_autosuspend(ddev->dev);
1535                 return ret;
1536         }
1537
1538         if (adev->powerplay.pp_funcs->set_power_profile_mode)
1539                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1540
1541         pm_runtime_mark_last_busy(ddev->dev);
1542         pm_runtime_put_autosuspend(ddev->dev);
1543
1544         if (!ret)
1545                 return count;
1546
1547         return -EINVAL;
1548 }
1549
1550 /**
1551  * DOC: gpu_busy_percent
1552  *
1553  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1554  * is as a percentage.  The file gpu_busy_percent is used for this.
1555  * The SMU firmware computes a percentage of load based on the
1556  * aggregate activity level in the IP cores.
1557  */
1558 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1559                                            struct device_attribute *attr,
1560                                            char *buf)
1561 {
1562         struct drm_device *ddev = dev_get_drvdata(dev);
1563         struct amdgpu_device *adev = drm_to_adev(ddev);
1564         int r, value, size = sizeof(value);
1565
1566         if (amdgpu_in_reset(adev))
1567                 return -EPERM;
1568         if (adev->in_suspend && !adev->in_runpm)
1569                 return -EPERM;
1570
1571         r = pm_runtime_get_sync(ddev->dev);
1572         if (r < 0) {
1573                 pm_runtime_put_autosuspend(ddev->dev);
1574                 return r;
1575         }
1576
1577         /* read the IP busy sensor */
1578         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1579                                    (void *)&value, &size);
1580
1581         pm_runtime_mark_last_busy(ddev->dev);
1582         pm_runtime_put_autosuspend(ddev->dev);
1583
1584         if (r)
1585                 return r;
1586
1587         return sysfs_emit(buf, "%d\n", value);
1588 }
1589
1590 /**
1591  * DOC: mem_busy_percent
1592  *
1593  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1594  * is as a percentage.  The file mem_busy_percent is used for this.
1595  * The SMU firmware computes a percentage of load based on the
1596  * aggregate activity level in the IP cores.
1597  */
1598 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1599                                            struct device_attribute *attr,
1600                                            char *buf)
1601 {
1602         struct drm_device *ddev = dev_get_drvdata(dev);
1603         struct amdgpu_device *adev = drm_to_adev(ddev);
1604         int r, value, size = sizeof(value);
1605
1606         if (amdgpu_in_reset(adev))
1607                 return -EPERM;
1608         if (adev->in_suspend && !adev->in_runpm)
1609                 return -EPERM;
1610
1611         r = pm_runtime_get_sync(ddev->dev);
1612         if (r < 0) {
1613                 pm_runtime_put_autosuspend(ddev->dev);
1614                 return r;
1615         }
1616
1617         /* read the IP busy sensor */
1618         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1619                                    (void *)&value, &size);
1620
1621         pm_runtime_mark_last_busy(ddev->dev);
1622         pm_runtime_put_autosuspend(ddev->dev);
1623
1624         if (r)
1625                 return r;
1626
1627         return sysfs_emit(buf, "%d\n", value);
1628 }
1629
1630 /**
1631  * DOC: pcie_bw
1632  *
1633  * The amdgpu driver provides a sysfs API for estimating how much data
1634  * has been received and sent by the GPU in the last second through PCIe.
1635  * The file pcie_bw is used for this.
1636  * The Perf counters count the number of received and sent messages and return
1637  * those values, as well as the maximum payload size of a PCIe packet (mps).
1638  * Note that it is not possible to easily and quickly obtain the size of each
1639  * packet transmitted, so we output the max payload size (mps) to allow for
1640  * quick estimation of the PCIe bandwidth usage
1641  */
1642 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1643                 struct device_attribute *attr,
1644                 char *buf)
1645 {
1646         struct drm_device *ddev = dev_get_drvdata(dev);
1647         struct amdgpu_device *adev = drm_to_adev(ddev);
1648         uint64_t count0 = 0, count1 = 0;
1649         int ret;
1650
1651         if (amdgpu_in_reset(adev))
1652                 return -EPERM;
1653         if (adev->in_suspend && !adev->in_runpm)
1654                 return -EPERM;
1655
1656         if (adev->flags & AMD_IS_APU)
1657                 return -ENODATA;
1658
1659         if (!adev->asic_funcs->get_pcie_usage)
1660                 return -ENODATA;
1661
1662         ret = pm_runtime_get_sync(ddev->dev);
1663         if (ret < 0) {
1664                 pm_runtime_put_autosuspend(ddev->dev);
1665                 return ret;
1666         }
1667
1668         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1669
1670         pm_runtime_mark_last_busy(ddev->dev);
1671         pm_runtime_put_autosuspend(ddev->dev);
1672
1673         return sysfs_emit(buf, "%llu %llu %i\n",
1674                           count0, count1, pcie_get_mps(adev->pdev));
1675 }
1676
1677 /**
1678  * DOC: unique_id
1679  *
1680  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1681  * The file unique_id is used for this.
1682  * This will provide a Unique ID that will persist from machine to machine
1683  *
1684  * NOTE: This will only work for GFX9 and newer. This file will be absent
1685  * on unsupported ASICs (GFX8 and older)
1686  */
1687 static ssize_t amdgpu_get_unique_id(struct device *dev,
1688                 struct device_attribute *attr,
1689                 char *buf)
1690 {
1691         struct drm_device *ddev = dev_get_drvdata(dev);
1692         struct amdgpu_device *adev = drm_to_adev(ddev);
1693
1694         if (amdgpu_in_reset(adev))
1695                 return -EPERM;
1696         if (adev->in_suspend && !adev->in_runpm)
1697                 return -EPERM;
1698
1699         if (adev->unique_id)
1700                 return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * DOC: thermal_throttling_logging
1707  *
1708  * Thermal throttling pulls down the clock frequency and thus the performance.
1709  * It's an useful mechanism to protect the chip from overheating. Since it
1710  * impacts performance, the user controls whether it is enabled and if so,
1711  * the log frequency.
1712  *
1713  * Reading back the file shows you the status(enabled or disabled) and
1714  * the interval(in seconds) between each thermal logging.
1715  *
1716  * Writing an integer to the file, sets a new logging interval, in seconds.
1717  * The value should be between 1 and 3600. If the value is less than 1,
1718  * thermal logging is disabled. Values greater than 3600 are ignored.
1719  */
1720 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1721                                                      struct device_attribute *attr,
1722                                                      char *buf)
1723 {
1724         struct drm_device *ddev = dev_get_drvdata(dev);
1725         struct amdgpu_device *adev = drm_to_adev(ddev);
1726
1727         return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1728                           adev_to_drm(adev)->unique,
1729                           atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1730                           adev->throttling_logging_rs.interval / HZ + 1);
1731 }
1732
1733 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1734                                                      struct device_attribute *attr,
1735                                                      const char *buf,
1736                                                      size_t count)
1737 {
1738         struct drm_device *ddev = dev_get_drvdata(dev);
1739         struct amdgpu_device *adev = drm_to_adev(ddev);
1740         long throttling_logging_interval;
1741         unsigned long flags;
1742         int ret = 0;
1743
1744         ret = kstrtol(buf, 0, &throttling_logging_interval);
1745         if (ret)
1746                 return ret;
1747
1748         if (throttling_logging_interval > 3600)
1749                 return -EINVAL;
1750
1751         if (throttling_logging_interval > 0) {
1752                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1753                 /*
1754                  * Reset the ratelimit timer internals.
1755                  * This can effectively restart the timer.
1756                  */
1757                 adev->throttling_logging_rs.interval =
1758                         (throttling_logging_interval - 1) * HZ;
1759                 adev->throttling_logging_rs.begin = 0;
1760                 adev->throttling_logging_rs.printed = 0;
1761                 adev->throttling_logging_rs.missed = 0;
1762                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1763
1764                 atomic_set(&adev->throttling_logging_enabled, 1);
1765         } else {
1766                 atomic_set(&adev->throttling_logging_enabled, 0);
1767         }
1768
1769         return count;
1770 }
1771
1772 /**
1773  * DOC: gpu_metrics
1774  *
1775  * The amdgpu driver provides a sysfs API for retrieving current gpu
1776  * metrics data. The file gpu_metrics is used for this. Reading the
1777  * file will dump all the current gpu metrics data.
1778  *
1779  * These data include temperature, frequency, engines utilization,
1780  * power consume, throttler status, fan speed and cpu core statistics(
1781  * available for APU only). That's it will give a snapshot of all sensors
1782  * at the same time.
1783  */
1784 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1785                                       struct device_attribute *attr,
1786                                       char *buf)
1787 {
1788         struct drm_device *ddev = dev_get_drvdata(dev);
1789         struct amdgpu_device *adev = drm_to_adev(ddev);
1790         void *gpu_metrics;
1791         ssize_t size = 0;
1792         int ret;
1793
1794         if (amdgpu_in_reset(adev))
1795                 return -EPERM;
1796         if (adev->in_suspend && !adev->in_runpm)
1797                 return -EPERM;
1798
1799         ret = pm_runtime_get_sync(ddev->dev);
1800         if (ret < 0) {
1801                 pm_runtime_put_autosuspend(ddev->dev);
1802                 return ret;
1803         }
1804
1805         if (adev->powerplay.pp_funcs->get_gpu_metrics)
1806                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1807
1808         if (size <= 0)
1809                 goto out;
1810
1811         if (size >= PAGE_SIZE)
1812                 size = PAGE_SIZE - 1;
1813
1814         memcpy(buf, gpu_metrics, size);
1815
1816 out:
1817         pm_runtime_mark_last_busy(ddev->dev);
1818         pm_runtime_put_autosuspend(ddev->dev);
1819
1820         return size;
1821 }
1822
1823 /**
1824  * DOC: smartshift_apu_power
1825  *
1826  * The amdgpu driver provides a sysfs API for reporting APU power
1827  * share if it supports smartshift. The value is expressed as
1828  * the proportion of stapm limit where stapm limit is the total APU
1829  * power limit. The result is in percentage. If APU power is 130% of
1830  * STAPM, then APU is using 30% of the dGPU's headroom.
1831  */
1832
1833 static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1834                                                char *buf)
1835 {
1836         struct drm_device *ddev = dev_get_drvdata(dev);
1837         struct amdgpu_device *adev = drm_to_adev(ddev);
1838         uint32_t ss_power, size;
1839         int r = 0;
1840
1841         if (amdgpu_in_reset(adev))
1842                 return -EPERM;
1843         if (adev->in_suspend && !adev->in_runpm)
1844                 return -EPERM;
1845
1846         r = pm_runtime_get_sync(ddev->dev);
1847         if (r < 0) {
1848                 pm_runtime_put_autosuspend(ddev->dev);
1849                 return r;
1850         }
1851
1852         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1853                                    (void *)&ss_power, &size);
1854         if (r)
1855                 goto out;
1856
1857         r = sysfs_emit(buf, "%u%%\n", ss_power);
1858
1859 out:
1860         pm_runtime_mark_last_busy(ddev->dev);
1861         pm_runtime_put_autosuspend(ddev->dev);
1862         return r;
1863 }
1864
1865 /**
1866  * DOC: smartshift_dgpu_power
1867  *
1868  * The amdgpu driver provides a sysfs API for reporting the dGPU power
1869  * share if the device is in HG and supports smartshift. The value
1870  * is expressed as the proportion of stapm limit where stapm limit
1871  * is the total APU power limit. The value is in percentage. If dGPU
1872  * power is 20% higher than STAPM power(120%), it's using 20% of the
1873  * APU's power headroom.
1874  */
1875
1876 static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1877                                                 char *buf)
1878 {
1879         struct drm_device *ddev = dev_get_drvdata(dev);
1880         struct amdgpu_device *adev = drm_to_adev(ddev);
1881         uint32_t ss_power, size;
1882         int r = 0;
1883
1884         if (amdgpu_in_reset(adev))
1885                 return -EPERM;
1886         if (adev->in_suspend && !adev->in_runpm)
1887                 return -EPERM;
1888
1889         r = pm_runtime_get_sync(ddev->dev);
1890         if (r < 0) {
1891                 pm_runtime_put_autosuspend(ddev->dev);
1892                 return r;
1893         }
1894
1895         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1896                                    (void *)&ss_power, &size);
1897
1898         if (r)
1899                 goto out;
1900
1901         r = sysfs_emit(buf, "%u%%\n", ss_power);
1902
1903 out:
1904         pm_runtime_mark_last_busy(ddev->dev);
1905         pm_runtime_put_autosuspend(ddev->dev);
1906         return r;
1907 }
1908
1909 /**
1910  * DOC: smartshift_bias
1911  *
1912  * The amdgpu driver provides a sysfs API for reporting the
1913  * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1914  * and the default is 0. -100 sets maximum preference to APU
1915  * and 100 sets max perference to dGPU.
1916  */
1917
1918 static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1919                                           struct device_attribute *attr,
1920                                           char *buf)
1921 {
1922         int r = 0;
1923
1924         r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1925
1926         return r;
1927 }
1928
1929 static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1930                                           struct device_attribute *attr,
1931                                           const char *buf, size_t count)
1932 {
1933         struct drm_device *ddev = dev_get_drvdata(dev);
1934         struct amdgpu_device *adev = drm_to_adev(ddev);
1935         int r = 0;
1936         int bias = 0;
1937
1938         if (amdgpu_in_reset(adev))
1939                 return -EPERM;
1940         if (adev->in_suspend && !adev->in_runpm)
1941                 return -EPERM;
1942
1943         r = pm_runtime_get_sync(ddev->dev);
1944         if (r < 0) {
1945                 pm_runtime_put_autosuspend(ddev->dev);
1946                 return r;
1947         }
1948
1949         r = kstrtoint(buf, 10, &bias);
1950         if (r)
1951                 goto out;
1952
1953         if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1954                 bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1955         else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1956                 bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1957
1958         amdgpu_smartshift_bias = bias;
1959         r = count;
1960
1961         /* TODO: upadte bias level with SMU message */
1962
1963 out:
1964         pm_runtime_mark_last_busy(ddev->dev);
1965         pm_runtime_put_autosuspend(ddev->dev);
1966         return r;
1967 }
1968
1969
1970 static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1971                                 uint32_t mask, enum amdgpu_device_attr_states *states)
1972 {
1973         uint32_t ss_power, size;
1974
1975         if (!amdgpu_acpi_is_power_shift_control_supported())
1976                 *states = ATTR_STATE_UNSUPPORTED;
1977         else if ((adev->flags & AMD_IS_PX) &&
1978                  !amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1979                 *states = ATTR_STATE_UNSUPPORTED;
1980         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1981                  (void *)&ss_power, &size))
1982                 *states = ATTR_STATE_UNSUPPORTED;
1983         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
1984                  (void *)&ss_power, &size))
1985                 *states = ATTR_STATE_UNSUPPORTED;
1986
1987         return 0;
1988 }
1989
1990 static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
1991                                uint32_t mask, enum amdgpu_device_attr_states *states)
1992 {
1993         uint32_t ss_power, size;
1994
1995         if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
1996                 *states = ATTR_STATE_UNSUPPORTED;
1997         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
1998                  (void *)&ss_power, &size))
1999                 *states = ATTR_STATE_UNSUPPORTED;
2000         else if (amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
2001                  (void *)&ss_power, &size))
2002                 *states = ATTR_STATE_UNSUPPORTED;
2003
2004         return 0;
2005 }
2006
2007 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2008         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2009         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2010         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2011         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2012         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2013         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2014         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2015         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2016         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2017         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2018         AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2019         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2020         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
2021         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
2022         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2023         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2024         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2025         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2026         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2027         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2028         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2029         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2030         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2031         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2032         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2033         AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,                     ATTR_FLAG_BASIC,
2034                               .attr_update = ss_power_attr_update),
2035         AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,                    ATTR_FLAG_BASIC,
2036                               .attr_update = ss_power_attr_update),
2037         AMDGPU_DEVICE_ATTR_RW(smartshift_bias,                          ATTR_FLAG_BASIC,
2038                               .attr_update = ss_bias_attr_update),
2039 };
2040
2041 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2042                                uint32_t mask, enum amdgpu_device_attr_states *states)
2043 {
2044         struct device_attribute *dev_attr = &attr->dev_attr;
2045         const char *attr_name = dev_attr->attr.name;
2046         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2047         enum amd_asic_type asic_type = adev->asic_type;
2048
2049         if (!(attr->flags & mask)) {
2050                 *states = ATTR_STATE_UNSUPPORTED;
2051                 return 0;
2052         }
2053
2054 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2055
2056         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2057                 if (asic_type < CHIP_VEGA10)
2058                         *states = ATTR_STATE_UNSUPPORTED;
2059         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2060                 if (asic_type < CHIP_VEGA10 ||
2061                     asic_type == CHIP_ARCTURUS ||
2062                     asic_type == CHIP_ALDEBARAN)
2063                         *states = ATTR_STATE_UNSUPPORTED;
2064         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2065                 if (asic_type < CHIP_VEGA20)
2066                         *states = ATTR_STATE_UNSUPPORTED;
2067         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2068                 *states = ATTR_STATE_UNSUPPORTED;
2069                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2070                     (is_support_sw_smu(adev) && adev->smu.is_apu) ||
2071                         (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2072                         *states = ATTR_STATE_SUPPORTED;
2073         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2074                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2075                         *states = ATTR_STATE_UNSUPPORTED;
2076         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2077                 /* PCIe Perf counters won't work on APU nodes */
2078                 if (adev->flags & AMD_IS_APU)
2079                         *states = ATTR_STATE_UNSUPPORTED;
2080         } else if (DEVICE_ATTR_IS(unique_id)) {
2081                 if (asic_type != CHIP_VEGA10 &&
2082                     asic_type != CHIP_VEGA20 &&
2083                     asic_type != CHIP_ARCTURUS)
2084                         *states = ATTR_STATE_UNSUPPORTED;
2085         } else if (DEVICE_ATTR_IS(pp_features)) {
2086                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2087                         *states = ATTR_STATE_UNSUPPORTED;
2088         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2089                 if (asic_type < CHIP_VEGA12)
2090                         *states = ATTR_STATE_UNSUPPORTED;
2091         } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2092                 if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID))
2093                         *states = ATTR_STATE_UNSUPPORTED;
2094         } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2095                 if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID))
2096                         *states = ATTR_STATE_UNSUPPORTED;
2097         }
2098
2099         switch (asic_type) {
2100         case CHIP_ARCTURUS:
2101         case CHIP_ALDEBARAN:
2102                 /* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2103                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2104                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2105                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2106                         dev_attr->attr.mode &= ~S_IWUGO;
2107                         dev_attr->store = NULL;
2108                 }
2109                 break;
2110         default:
2111                 break;
2112         }
2113
2114         if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2115                 /* SMU MP1 does not support dcefclk level setting */
2116                 if (asic_type >= CHIP_NAVI10) {
2117                         dev_attr->attr.mode &= ~S_IWUGO;
2118                         dev_attr->store = NULL;
2119                 }
2120         }
2121
2122 #undef DEVICE_ATTR_IS
2123
2124         return 0;
2125 }
2126
2127
2128 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2129                                      struct amdgpu_device_attr *attr,
2130                                      uint32_t mask, struct list_head *attr_list)
2131 {
2132         int ret = 0;
2133         struct device_attribute *dev_attr = &attr->dev_attr;
2134         const char *name = dev_attr->attr.name;
2135         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2136         struct amdgpu_device_attr_entry *attr_entry;
2137
2138         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2139                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2140
2141         BUG_ON(!attr);
2142
2143         attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2144
2145         ret = attr_update(adev, attr, mask, &attr_states);
2146         if (ret) {
2147                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2148                         name, ret);
2149                 return ret;
2150         }
2151
2152         if (attr_states == ATTR_STATE_UNSUPPORTED)
2153                 return 0;
2154
2155         ret = device_create_file(adev->dev, dev_attr);
2156         if (ret) {
2157                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2158                         name, ret);
2159         }
2160
2161         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2162         if (!attr_entry)
2163                 return -ENOMEM;
2164
2165         attr_entry->attr = attr;
2166         INIT_LIST_HEAD(&attr_entry->entry);
2167
2168         list_add_tail(&attr_entry->entry, attr_list);
2169
2170         return ret;
2171 }
2172
2173 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2174 {
2175         struct device_attribute *dev_attr = &attr->dev_attr;
2176
2177         device_remove_file(adev->dev, dev_attr);
2178 }
2179
2180 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2181                                              struct list_head *attr_list);
2182
2183 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2184                                             struct amdgpu_device_attr *attrs,
2185                                             uint32_t counts,
2186                                             uint32_t mask,
2187                                             struct list_head *attr_list)
2188 {
2189         int ret = 0;
2190         uint32_t i = 0;
2191
2192         for (i = 0; i < counts; i++) {
2193                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2194                 if (ret)
2195                         goto failed;
2196         }
2197
2198         return 0;
2199
2200 failed:
2201         amdgpu_device_attr_remove_groups(adev, attr_list);
2202
2203         return ret;
2204 }
2205
2206 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2207                                              struct list_head *attr_list)
2208 {
2209         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2210
2211         if (list_empty(attr_list))
2212                 return ;
2213
2214         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2215                 amdgpu_device_attr_remove(adev, entry->attr);
2216                 list_del(&entry->entry);
2217                 kfree(entry);
2218         }
2219 }
2220
2221 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2222                                       struct device_attribute *attr,
2223                                       char *buf)
2224 {
2225         struct amdgpu_device *adev = dev_get_drvdata(dev);
2226         int channel = to_sensor_dev_attr(attr)->index;
2227         int r, temp = 0, size = sizeof(temp);
2228
2229         if (amdgpu_in_reset(adev))
2230                 return -EPERM;
2231         if (adev->in_suspend && !adev->in_runpm)
2232                 return -EPERM;
2233
2234         if (channel >= PP_TEMP_MAX)
2235                 return -EINVAL;
2236
2237         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2238         if (r < 0) {
2239                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2240                 return r;
2241         }
2242
2243         switch (channel) {
2244         case PP_TEMP_JUNCTION:
2245                 /* get current junction temperature */
2246                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2247                                            (void *)&temp, &size);
2248                 break;
2249         case PP_TEMP_EDGE:
2250                 /* get current edge temperature */
2251                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2252                                            (void *)&temp, &size);
2253                 break;
2254         case PP_TEMP_MEM:
2255                 /* get current memory temperature */
2256                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2257                                            (void *)&temp, &size);
2258                 break;
2259         default:
2260                 r = -EINVAL;
2261                 break;
2262         }
2263
2264         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2265         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2266
2267         if (r)
2268                 return r;
2269
2270         return sysfs_emit(buf, "%d\n", temp);
2271 }
2272
2273 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2274                                              struct device_attribute *attr,
2275                                              char *buf)
2276 {
2277         struct amdgpu_device *adev = dev_get_drvdata(dev);
2278         int hyst = to_sensor_dev_attr(attr)->index;
2279         int temp;
2280
2281         if (hyst)
2282                 temp = adev->pm.dpm.thermal.min_temp;
2283         else
2284                 temp = adev->pm.dpm.thermal.max_temp;
2285
2286         return sysfs_emit(buf, "%d\n", temp);
2287 }
2288
2289 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2290                                              struct device_attribute *attr,
2291                                              char *buf)
2292 {
2293         struct amdgpu_device *adev = dev_get_drvdata(dev);
2294         int hyst = to_sensor_dev_attr(attr)->index;
2295         int temp;
2296
2297         if (hyst)
2298                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2299         else
2300                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2301
2302         return sysfs_emit(buf, "%d\n", temp);
2303 }
2304
2305 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2306                                              struct device_attribute *attr,
2307                                              char *buf)
2308 {
2309         struct amdgpu_device *adev = dev_get_drvdata(dev);
2310         int hyst = to_sensor_dev_attr(attr)->index;
2311         int temp;
2312
2313         if (hyst)
2314                 temp = adev->pm.dpm.thermal.min_mem_temp;
2315         else
2316                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2317
2318         return sysfs_emit(buf, "%d\n", temp);
2319 }
2320
2321 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2322                                              struct device_attribute *attr,
2323                                              char *buf)
2324 {
2325         int channel = to_sensor_dev_attr(attr)->index;
2326
2327         if (channel >= PP_TEMP_MAX)
2328                 return -EINVAL;
2329
2330         return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2331 }
2332
2333 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2334                                              struct device_attribute *attr,
2335                                              char *buf)
2336 {
2337         struct amdgpu_device *adev = dev_get_drvdata(dev);
2338         int channel = to_sensor_dev_attr(attr)->index;
2339         int temp = 0;
2340
2341         if (channel >= PP_TEMP_MAX)
2342                 return -EINVAL;
2343
2344         switch (channel) {
2345         case PP_TEMP_JUNCTION:
2346                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2347                 break;
2348         case PP_TEMP_EDGE:
2349                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2350                 break;
2351         case PP_TEMP_MEM:
2352                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2353                 break;
2354         }
2355
2356         return sysfs_emit(buf, "%d\n", temp);
2357 }
2358
2359 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2360                                             struct device_attribute *attr,
2361                                             char *buf)
2362 {
2363         struct amdgpu_device *adev = dev_get_drvdata(dev);
2364         u32 pwm_mode = 0;
2365         int ret;
2366
2367         if (amdgpu_in_reset(adev))
2368                 return -EPERM;
2369         if (adev->in_suspend && !adev->in_runpm)
2370                 return -EPERM;
2371
2372         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2373         if (ret < 0) {
2374                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2375                 return ret;
2376         }
2377
2378         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2379                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2380                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2381                 return -EINVAL;
2382         }
2383
2384         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2385
2386         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2387         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2388
2389         return sysfs_emit(buf, "%u\n", pwm_mode);
2390 }
2391
2392 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2393                                             struct device_attribute *attr,
2394                                             const char *buf,
2395                                             size_t count)
2396 {
2397         struct amdgpu_device *adev = dev_get_drvdata(dev);
2398         int err, ret;
2399         int value;
2400
2401         if (amdgpu_in_reset(adev))
2402                 return -EPERM;
2403         if (adev->in_suspend && !adev->in_runpm)
2404                 return -EPERM;
2405
2406         err = kstrtoint(buf, 10, &value);
2407         if (err)
2408                 return err;
2409
2410         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2411         if (ret < 0) {
2412                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2413                 return ret;
2414         }
2415
2416         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2417                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2418                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2419                 return -EINVAL;
2420         }
2421
2422         amdgpu_dpm_set_fan_control_mode(adev, value);
2423
2424         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2425         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2426
2427         return count;
2428 }
2429
2430 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2431                                          struct device_attribute *attr,
2432                                          char *buf)
2433 {
2434         return sysfs_emit(buf, "%i\n", 0);
2435 }
2436
2437 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2438                                          struct device_attribute *attr,
2439                                          char *buf)
2440 {
2441         return sysfs_emit(buf, "%i\n", 255);
2442 }
2443
2444 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2445                                      struct device_attribute *attr,
2446                                      const char *buf, size_t count)
2447 {
2448         struct amdgpu_device *adev = dev_get_drvdata(dev);
2449         int err;
2450         u32 value;
2451         u32 pwm_mode;
2452
2453         if (amdgpu_in_reset(adev))
2454                 return -EPERM;
2455         if (adev->in_suspend && !adev->in_runpm)
2456                 return -EPERM;
2457
2458         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2459         if (err < 0) {
2460                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2461                 return err;
2462         }
2463
2464         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2465         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2466                 pr_info("manual fan speed control should be enabled first\n");
2467                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2468                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2469                 return -EINVAL;
2470         }
2471
2472         err = kstrtou32(buf, 10, &value);
2473         if (err) {
2474                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2475                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2476                 return err;
2477         }
2478
2479         if (adev->powerplay.pp_funcs->set_fan_speed_pwm)
2480                 err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2481         else
2482                 err = -EINVAL;
2483
2484         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2485         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2486
2487         if (err)
2488                 return err;
2489
2490         return count;
2491 }
2492
2493 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2494                                      struct device_attribute *attr,
2495                                      char *buf)
2496 {
2497         struct amdgpu_device *adev = dev_get_drvdata(dev);
2498         int err;
2499         u32 speed = 0;
2500
2501         if (amdgpu_in_reset(adev))
2502                 return -EPERM;
2503         if (adev->in_suspend && !adev->in_runpm)
2504                 return -EPERM;
2505
2506         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2507         if (err < 0) {
2508                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2509                 return err;
2510         }
2511
2512         if (adev->powerplay.pp_funcs->get_fan_speed_pwm)
2513                 err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2514         else
2515                 err = -EINVAL;
2516
2517         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2518         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2519
2520         if (err)
2521                 return err;
2522
2523         return sysfs_emit(buf, "%i\n", speed);
2524 }
2525
2526 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2527                                            struct device_attribute *attr,
2528                                            char *buf)
2529 {
2530         struct amdgpu_device *adev = dev_get_drvdata(dev);
2531         int err;
2532         u32 speed = 0;
2533
2534         if (amdgpu_in_reset(adev))
2535                 return -EPERM;
2536         if (adev->in_suspend && !adev->in_runpm)
2537                 return -EPERM;
2538
2539         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2540         if (err < 0) {
2541                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2542                 return err;
2543         }
2544
2545         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2546                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2547         else
2548                 err = -EINVAL;
2549
2550         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2551         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2552
2553         if (err)
2554                 return err;
2555
2556         return sysfs_emit(buf, "%i\n", speed);
2557 }
2558
2559 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2560                                          struct device_attribute *attr,
2561                                          char *buf)
2562 {
2563         struct amdgpu_device *adev = dev_get_drvdata(dev);
2564         u32 min_rpm = 0;
2565         u32 size = sizeof(min_rpm);
2566         int r;
2567
2568         if (amdgpu_in_reset(adev))
2569                 return -EPERM;
2570         if (adev->in_suspend && !adev->in_runpm)
2571                 return -EPERM;
2572
2573         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2574         if (r < 0) {
2575                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2576                 return r;
2577         }
2578
2579         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2580                                    (void *)&min_rpm, &size);
2581
2582         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2583         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2584
2585         if (r)
2586                 return r;
2587
2588         return sysfs_emit(buf, "%d\n", min_rpm);
2589 }
2590
2591 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2592                                          struct device_attribute *attr,
2593                                          char *buf)
2594 {
2595         struct amdgpu_device *adev = dev_get_drvdata(dev);
2596         u32 max_rpm = 0;
2597         u32 size = sizeof(max_rpm);
2598         int r;
2599
2600         if (amdgpu_in_reset(adev))
2601                 return -EPERM;
2602         if (adev->in_suspend && !adev->in_runpm)
2603                 return -EPERM;
2604
2605         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2606         if (r < 0) {
2607                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2608                 return r;
2609         }
2610
2611         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2612                                    (void *)&max_rpm, &size);
2613
2614         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2615         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2616
2617         if (r)
2618                 return r;
2619
2620         return sysfs_emit(buf, "%d\n", max_rpm);
2621 }
2622
2623 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2624                                            struct device_attribute *attr,
2625                                            char *buf)
2626 {
2627         struct amdgpu_device *adev = dev_get_drvdata(dev);
2628         int err;
2629         u32 rpm = 0;
2630
2631         if (amdgpu_in_reset(adev))
2632                 return -EPERM;
2633         if (adev->in_suspend && !adev->in_runpm)
2634                 return -EPERM;
2635
2636         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2637         if (err < 0) {
2638                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2639                 return err;
2640         }
2641
2642         if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2643                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2644         else
2645                 err = -EINVAL;
2646
2647         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2648         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2649
2650         if (err)
2651                 return err;
2652
2653         return sysfs_emit(buf, "%i\n", rpm);
2654 }
2655
2656 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2657                                      struct device_attribute *attr,
2658                                      const char *buf, size_t count)
2659 {
2660         struct amdgpu_device *adev = dev_get_drvdata(dev);
2661         int err;
2662         u32 value;
2663         u32 pwm_mode;
2664
2665         if (amdgpu_in_reset(adev))
2666                 return -EPERM;
2667         if (adev->in_suspend && !adev->in_runpm)
2668                 return -EPERM;
2669
2670         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2671         if (err < 0) {
2672                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2673                 return err;
2674         }
2675
2676         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2677
2678         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2679                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2680                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2681                 return -ENODATA;
2682         }
2683
2684         err = kstrtou32(buf, 10, &value);
2685         if (err) {
2686                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2687                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2688                 return err;
2689         }
2690
2691         if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2692                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2693         else
2694                 err = -EINVAL;
2695
2696         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2697         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2698
2699         if (err)
2700                 return err;
2701
2702         return count;
2703 }
2704
2705 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2706                                             struct device_attribute *attr,
2707                                             char *buf)
2708 {
2709         struct amdgpu_device *adev = dev_get_drvdata(dev);
2710         u32 pwm_mode = 0;
2711         int ret;
2712
2713         if (amdgpu_in_reset(adev))
2714                 return -EPERM;
2715         if (adev->in_suspend && !adev->in_runpm)
2716                 return -EPERM;
2717
2718         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2719         if (ret < 0) {
2720                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2721                 return ret;
2722         }
2723
2724         if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2725                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2726                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2727                 return -EINVAL;
2728         }
2729
2730         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2731
2732         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2733         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2734
2735         return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2736 }
2737
2738 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2739                                             struct device_attribute *attr,
2740                                             const char *buf,
2741                                             size_t count)
2742 {
2743         struct amdgpu_device *adev = dev_get_drvdata(dev);
2744         int err;
2745         int value;
2746         u32 pwm_mode;
2747
2748         if (amdgpu_in_reset(adev))
2749                 return -EPERM;
2750         if (adev->in_suspend && !adev->in_runpm)
2751                 return -EPERM;
2752
2753         err = kstrtoint(buf, 10, &value);
2754         if (err)
2755                 return err;
2756
2757         if (value == 0)
2758                 pwm_mode = AMD_FAN_CTRL_AUTO;
2759         else if (value == 1)
2760                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2761         else
2762                 return -EINVAL;
2763
2764         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2765         if (err < 0) {
2766                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2767                 return err;
2768         }
2769
2770         if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2771                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2772                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2773                 return -EINVAL;
2774         }
2775         amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2776
2777         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2778         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2779
2780         return count;
2781 }
2782
2783 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2784                                         struct device_attribute *attr,
2785                                         char *buf)
2786 {
2787         struct amdgpu_device *adev = dev_get_drvdata(dev);
2788         u32 vddgfx;
2789         int r, size = sizeof(vddgfx);
2790
2791         if (amdgpu_in_reset(adev))
2792                 return -EPERM;
2793         if (adev->in_suspend && !adev->in_runpm)
2794                 return -EPERM;
2795
2796         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2797         if (r < 0) {
2798                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2799                 return r;
2800         }
2801
2802         /* get the voltage */
2803         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2804                                    (void *)&vddgfx, &size);
2805
2806         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2807         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2808
2809         if (r)
2810                 return r;
2811
2812         return sysfs_emit(buf, "%d\n", vddgfx);
2813 }
2814
2815 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2816                                               struct device_attribute *attr,
2817                                               char *buf)
2818 {
2819         return sysfs_emit(buf, "vddgfx\n");
2820 }
2821
2822 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2823                                        struct device_attribute *attr,
2824                                        char *buf)
2825 {
2826         struct amdgpu_device *adev = dev_get_drvdata(dev);
2827         u32 vddnb;
2828         int r, size = sizeof(vddnb);
2829
2830         if (amdgpu_in_reset(adev))
2831                 return -EPERM;
2832         if (adev->in_suspend && !adev->in_runpm)
2833                 return -EPERM;
2834
2835         /* only APUs have vddnb */
2836         if  (!(adev->flags & AMD_IS_APU))
2837                 return -EINVAL;
2838
2839         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2840         if (r < 0) {
2841                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2842                 return r;
2843         }
2844
2845         /* get the voltage */
2846         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2847                                    (void *)&vddnb, &size);
2848
2849         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2850         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2851
2852         if (r)
2853                 return r;
2854
2855         return sysfs_emit(buf, "%d\n", vddnb);
2856 }
2857
2858 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2859                                               struct device_attribute *attr,
2860                                               char *buf)
2861 {
2862         return sysfs_emit(buf, "vddnb\n");
2863 }
2864
2865 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2866                                            struct device_attribute *attr,
2867                                            char *buf)
2868 {
2869         struct amdgpu_device *adev = dev_get_drvdata(dev);
2870         u32 query = 0;
2871         int r, size = sizeof(u32);
2872         unsigned uw;
2873
2874         if (amdgpu_in_reset(adev))
2875                 return -EPERM;
2876         if (adev->in_suspend && !adev->in_runpm)
2877                 return -EPERM;
2878
2879         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2880         if (r < 0) {
2881                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2882                 return r;
2883         }
2884
2885         /* get the voltage */
2886         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2887                                    (void *)&query, &size);
2888
2889         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2890         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2891
2892         if (r)
2893                 return r;
2894
2895         /* convert to microwatts */
2896         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2897
2898         return sysfs_emit(buf, "%u\n", uw);
2899 }
2900
2901 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2902                                          struct device_attribute *attr,
2903                                          char *buf)
2904 {
2905         return sysfs_emit(buf, "%i\n", 0);
2906 }
2907
2908
2909 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2910                                         struct device_attribute *attr,
2911                                         char *buf,
2912                                         enum pp_power_limit_level pp_limit_level)
2913 {
2914         struct amdgpu_device *adev = dev_get_drvdata(dev);
2915         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2916         enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
2917         uint32_t limit;
2918         ssize_t size;
2919         int r;
2920
2921         if (amdgpu_in_reset(adev))
2922                 return -EPERM;
2923         if (adev->in_suspend && !adev->in_runpm)
2924                 return -EPERM;
2925
2926         if ( !(pp_funcs && pp_funcs->get_power_limit))
2927                 return -ENODATA;
2928
2929         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2930         if (r < 0) {
2931                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2932                 return r;
2933         }
2934
2935         r = pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit,
2936                                       pp_limit_level, power_type);
2937
2938         if (!r)
2939                 size = sysfs_emit(buf, "%u\n", limit * 1000000);
2940         else
2941                 size = sysfs_emit(buf, "\n");
2942
2943         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2944         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2945
2946         return size;
2947 }
2948
2949
2950 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2951                                          struct device_attribute *attr,
2952                                          char *buf)
2953 {
2954         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
2955
2956 }
2957
2958 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2959                                          struct device_attribute *attr,
2960                                          char *buf)
2961 {
2962         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
2963
2964 }
2965
2966 static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
2967                                          struct device_attribute *attr,
2968                                          char *buf)
2969 {
2970         return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
2971
2972 }
2973
2974 static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
2975                                          struct device_attribute *attr,
2976                                          char *buf)
2977 {
2978         int limit_type = to_sensor_dev_attr(attr)->index;
2979
2980         return sysfs_emit(buf, "%s\n",
2981                 limit_type == SMU_FAST_PPT_LIMIT ? "fastPPT" : "slowPPT");
2982 }
2983
2984 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2985                 struct device_attribute *attr,
2986                 const char *buf,
2987                 size_t count)
2988 {
2989         struct amdgpu_device *adev = dev_get_drvdata(dev);
2990         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
2991         int limit_type = to_sensor_dev_attr(attr)->index;
2992         int err;
2993         u32 value;
2994
2995         if (amdgpu_in_reset(adev))
2996                 return -EPERM;
2997         if (adev->in_suspend && !adev->in_runpm)
2998                 return -EPERM;
2999
3000         if (amdgpu_sriov_vf(adev))
3001                 return -EINVAL;
3002
3003         err = kstrtou32(buf, 10, &value);
3004         if (err)
3005                 return err;
3006
3007         value = value / 1000000; /* convert to Watt */
3008         value |= limit_type << 24;
3009
3010         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3011         if (err < 0) {
3012                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3013                 return err;
3014         }
3015
3016         if (pp_funcs && pp_funcs->set_power_limit)
3017                 err = pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
3018         else
3019                 err = -EINVAL;
3020
3021         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3022         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3023
3024         if (err)
3025                 return err;
3026
3027         return count;
3028 }
3029
3030 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3031                                       struct device_attribute *attr,
3032                                       char *buf)
3033 {
3034         struct amdgpu_device *adev = dev_get_drvdata(dev);
3035         uint32_t sclk;
3036         int r, size = sizeof(sclk);
3037
3038         if (amdgpu_in_reset(adev))
3039                 return -EPERM;
3040         if (adev->in_suspend && !adev->in_runpm)
3041                 return -EPERM;
3042
3043         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3044         if (r < 0) {
3045                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3046                 return r;
3047         }
3048
3049         /* get the sclk */
3050         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3051                                    (void *)&sclk, &size);
3052
3053         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3054         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3055
3056         if (r)
3057                 return r;
3058
3059         return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3060 }
3061
3062 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3063                                             struct device_attribute *attr,
3064                                             char *buf)
3065 {
3066         return sysfs_emit(buf, "sclk\n");
3067 }
3068
3069 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3070                                       struct device_attribute *attr,
3071                                       char *buf)
3072 {
3073         struct amdgpu_device *adev = dev_get_drvdata(dev);
3074         uint32_t mclk;
3075         int r, size = sizeof(mclk);
3076
3077         if (amdgpu_in_reset(adev))
3078                 return -EPERM;
3079         if (adev->in_suspend && !adev->in_runpm)
3080                 return -EPERM;
3081
3082         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3083         if (r < 0) {
3084                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3085                 return r;
3086         }
3087
3088         /* get the sclk */
3089         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3090                                    (void *)&mclk, &size);
3091
3092         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3093         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3094
3095         if (r)
3096                 return r;
3097
3098         return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3099 }
3100
3101 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3102                                             struct device_attribute *attr,
3103                                             char *buf)
3104 {
3105         return sysfs_emit(buf, "mclk\n");
3106 }
3107
3108 /**
3109  * DOC: hwmon
3110  *
3111  * The amdgpu driver exposes the following sensor interfaces:
3112  *
3113  * - GPU temperature (via the on-die sensor)
3114  *
3115  * - GPU voltage
3116  *
3117  * - Northbridge voltage (APUs only)
3118  *
3119  * - GPU power
3120  *
3121  * - GPU fan
3122  *
3123  * - GPU gfx/compute engine clock
3124  *
3125  * - GPU memory clock (dGPU only)
3126  *
3127  * hwmon interfaces for GPU temperature:
3128  *
3129  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3130  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3131  *
3132  * - temp[1-3]_label: temperature channel label
3133  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3134  *
3135  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3136  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3137  *
3138  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3139  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3140  *
3141  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3142  *   - these are supported on SOC15 dGPUs only
3143  *
3144  * hwmon interfaces for GPU voltage:
3145  *
3146  * - in0_input: the voltage on the GPU in millivolts
3147  *
3148  * - in1_input: the voltage on the Northbridge in millivolts
3149  *
3150  * hwmon interfaces for GPU power:
3151  *
3152  * - power1_average: average power used by the GPU in microWatts
3153  *
3154  * - power1_cap_min: minimum cap supported in microWatts
3155  *
3156  * - power1_cap_max: maximum cap supported in microWatts
3157  *
3158  * - power1_cap: selected power cap in microWatts
3159  *
3160  * hwmon interfaces for GPU fan:
3161  *
3162  * - pwm1: pulse width modulation fan level (0-255)
3163  *
3164  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3165  *
3166  * - pwm1_min: pulse width modulation fan control minimum level (0)
3167  *
3168  * - pwm1_max: pulse width modulation fan control maximum level (255)
3169  *
3170  * - fan1_min: a minimum value Unit: revolution/min (RPM)
3171  *
3172  * - fan1_max: a maximum value Unit: revolution/max (RPM)
3173  *
3174  * - fan1_input: fan speed in RPM
3175  *
3176  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3177  *
3178  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3179  *
3180  * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3181  *       That will get the former one overridden.
3182  *
3183  * hwmon interfaces for GPU clocks:
3184  *
3185  * - freq1_input: the gfx/compute clock in hertz
3186  *
3187  * - freq2_input: the memory clock in hertz
3188  *
3189  * You can use hwmon tools like sensors to view this information on your system.
3190  *
3191  */
3192
3193 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3194 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3195 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3196 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3197 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3198 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3199 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3200 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3201 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3202 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3203 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3204 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3205 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3206 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3207 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3208 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3209 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3210 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3211 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3212 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3213 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3214 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3215 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3216 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3217 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3218 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3219 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3220 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3221 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3222 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3223 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3224 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3225 static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3226 static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3227 static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3228 static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3229 static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3230 static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3231 static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3232 static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3233 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3234 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3235 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3236 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3237
3238 static struct attribute *hwmon_attributes[] = {
3239         &sensor_dev_attr_temp1_input.dev_attr.attr,
3240         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3241         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3242         &sensor_dev_attr_temp2_input.dev_attr.attr,
3243         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3244         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3245         &sensor_dev_attr_temp3_input.dev_attr.attr,
3246         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3247         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3248         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3249         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3250         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3251         &sensor_dev_attr_temp1_label.dev_attr.attr,
3252         &sensor_dev_attr_temp2_label.dev_attr.attr,
3253         &sensor_dev_attr_temp3_label.dev_attr.attr,
3254         &sensor_dev_attr_pwm1.dev_attr.attr,
3255         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3256         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3257         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3258         &sensor_dev_attr_fan1_input.dev_attr.attr,
3259         &sensor_dev_attr_fan1_min.dev_attr.attr,
3260         &sensor_dev_attr_fan1_max.dev_attr.attr,
3261         &sensor_dev_attr_fan1_target.dev_attr.attr,
3262         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3263         &sensor_dev_attr_in0_input.dev_attr.attr,
3264         &sensor_dev_attr_in0_label.dev_attr.attr,
3265         &sensor_dev_attr_in1_input.dev_attr.attr,
3266         &sensor_dev_attr_in1_label.dev_attr.attr,
3267         &sensor_dev_attr_power1_average.dev_attr.attr,
3268         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3269         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3270         &sensor_dev_attr_power1_cap.dev_attr.attr,
3271         &sensor_dev_attr_power1_cap_default.dev_attr.attr,
3272         &sensor_dev_attr_power1_label.dev_attr.attr,
3273         &sensor_dev_attr_power2_average.dev_attr.attr,
3274         &sensor_dev_attr_power2_cap_max.dev_attr.attr,
3275         &sensor_dev_attr_power2_cap_min.dev_attr.attr,
3276         &sensor_dev_attr_power2_cap.dev_attr.attr,
3277         &sensor_dev_attr_power2_cap_default.dev_attr.attr,
3278         &sensor_dev_attr_power2_label.dev_attr.attr,
3279         &sensor_dev_attr_freq1_input.dev_attr.attr,
3280         &sensor_dev_attr_freq1_label.dev_attr.attr,
3281         &sensor_dev_attr_freq2_input.dev_attr.attr,
3282         &sensor_dev_attr_freq2_label.dev_attr.attr,
3283         NULL
3284 };
3285
3286 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3287                                         struct attribute *attr, int index)
3288 {
3289         struct device *dev = kobj_to_dev(kobj);
3290         struct amdgpu_device *adev = dev_get_drvdata(dev);
3291         umode_t effective_mode = attr->mode;
3292
3293         /* under multi-vf mode, the hwmon attributes are all not supported */
3294         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3295                 return 0;
3296
3297         /* there is no fan under pp one vf mode */
3298         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3299             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3300              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3301              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3302              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3303              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3304              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3305              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3306              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3307              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3308                 return 0;
3309
3310         /* Skip fan attributes if fan is not present */
3311         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3312             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3313             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3314             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3315             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3316             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3317             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3318             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3319             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3320                 return 0;
3321
3322         /* Skip fan attributes on APU */
3323         if ((adev->flags & AMD_IS_APU) &&
3324             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3325              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3326              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3327              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3328              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3329              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3330              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3331              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3332              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3333                 return 0;
3334
3335         /* Skip crit temp on APU */
3336         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3337             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3338              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3339                 return 0;
3340
3341         /* Skip limit attributes if DPM is not enabled */
3342         if (!adev->pm.dpm_enabled &&
3343             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3344              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3345              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3346              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3347              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3348              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3349              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3350              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3351              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3352              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3353              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3354                 return 0;
3355
3356         if (!is_support_sw_smu(adev)) {
3357                 /* mask fan attributes if we have no bindings for this asic to expose */
3358                 if ((!adev->powerplay.pp_funcs->get_fan_speed_pwm &&
3359                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3360                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3361                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3362                         effective_mode &= ~S_IRUGO;
3363
3364                 if ((!adev->powerplay.pp_funcs->set_fan_speed_pwm &&
3365                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3366                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3367                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3368                         effective_mode &= ~S_IWUSR;
3369         }
3370
3371         if (((adev->family == AMDGPU_FAMILY_SI) ||
3372                  ((adev->flags & AMD_IS_APU) &&
3373               (adev->asic_type != CHIP_VANGOGH))) &&    /* not implemented yet */
3374             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3375              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3376              attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3377              attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3378                 return 0;
3379
3380         if (((adev->family == AMDGPU_FAMILY_SI) ||
3381              ((adev->flags & AMD_IS_APU) &&
3382               (adev->asic_type < CHIP_RENOIR))) &&      /* not implemented yet */
3383             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3384                 return 0;
3385
3386         if (!is_support_sw_smu(adev)) {
3387                 /* hide max/min values if we can't both query and manage the fan */
3388                 if ((!adev->powerplay.pp_funcs->set_fan_speed_pwm &&
3389                      !adev->powerplay.pp_funcs->get_fan_speed_pwm) &&
3390                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3391                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3392                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3393                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3394                         return 0;
3395
3396                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3397                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3398                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3399                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3400                         return 0;
3401         }
3402
3403         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3404              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3405             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3406              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3407                 return 0;
3408
3409         /* only APUs have vddnb */
3410         if (!(adev->flags & AMD_IS_APU) &&
3411             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3412              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3413                 return 0;
3414
3415         /* no mclk on APUs */
3416         if ((adev->flags & AMD_IS_APU) &&
3417             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3418              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3419                 return 0;
3420
3421         /* only SOC15 dGPUs support hotspot and mem temperatures */
3422         if (((adev->flags & AMD_IS_APU) ||
3423              adev->asic_type < CHIP_VEGA10) &&
3424             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3425              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3426              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3427              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3428              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3429              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3430              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3431              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3432              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3433              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3434              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3435                 return 0;
3436
3437         /* only Vangogh has fast PPT limit and power labels */
3438         if (!(adev->asic_type == CHIP_VANGOGH) &&
3439             (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3440                  attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3441              attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3442                  attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3443                  attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3444                  attr == &sensor_dev_attr_power2_label.dev_attr.attr ||
3445                  attr == &sensor_dev_attr_power1_label.dev_attr.attr))
3446                 return 0;
3447
3448         return effective_mode;
3449 }
3450
3451 static const struct attribute_group hwmon_attrgroup = {
3452         .attrs = hwmon_attributes,
3453         .is_visible = hwmon_attributes_visible,
3454 };
3455
3456 static const struct attribute_group *hwmon_groups[] = {
3457         &hwmon_attrgroup,
3458         NULL
3459 };
3460
3461 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3462 {
3463         int ret;
3464         uint32_t mask = 0;
3465
3466         if (adev->pm.sysfs_initialized)
3467                 return 0;
3468
3469         if (adev->pm.dpm_enabled == 0)
3470                 return 0;
3471
3472         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3473
3474         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3475                                                                    DRIVER_NAME, adev,
3476                                                                    hwmon_groups);
3477         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3478                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3479                 dev_err(adev->dev,
3480                         "Unable to register hwmon device: %d\n", ret);
3481                 return ret;
3482         }
3483
3484         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3485         case SRIOV_VF_MODE_ONE_VF:
3486                 mask = ATTR_FLAG_ONEVF;
3487                 break;
3488         case SRIOV_VF_MODE_MULTI_VF:
3489                 mask = 0;
3490                 break;
3491         case SRIOV_VF_MODE_BARE_METAL:
3492         default:
3493                 mask = ATTR_FLAG_MASK_ALL;
3494                 break;
3495         }
3496
3497         ret = amdgpu_device_attr_create_groups(adev,
3498                                                amdgpu_device_attrs,
3499                                                ARRAY_SIZE(amdgpu_device_attrs),
3500                                                mask,
3501                                                &adev->pm.pm_attr_list);
3502         if (ret)
3503                 return ret;
3504
3505         adev->pm.sysfs_initialized = true;
3506
3507         return 0;
3508 }
3509
3510 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3511 {
3512         if (adev->pm.dpm_enabled == 0)
3513                 return;
3514
3515         if (adev->pm.int_hwmon_dev)
3516                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3517
3518         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3519 }
3520
3521 /*
3522  * Debugfs info
3523  */
3524 #if defined(CONFIG_DEBUG_FS)
3525
3526 static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
3527                                            struct amdgpu_device *adev) {
3528         uint16_t *p_val;
3529         uint32_t size;
3530         int i;
3531
3532         if (is_support_cclk_dpm(adev)) {
3533                 p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
3534                                 GFP_KERNEL);
3535
3536                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
3537                                             (void *)p_val, &size)) {
3538                         for (i = 0; i < adev->smu.cpu_core_num; i++)
3539                                 seq_printf(m, "\t%u MHz (CPU%d)\n",
3540                                            *(p_val + i), i);
3541                 }
3542
3543                 kfree(p_val);
3544         }
3545 }
3546
3547 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3548 {
3549         uint32_t value;
3550         uint64_t value64 = 0;
3551         uint32_t query = 0;
3552         int size;
3553
3554         /* GPU Clocks */
3555         size = sizeof(value);
3556         seq_printf(m, "GFX Clocks and Power:\n");
3557
3558         amdgpu_debugfs_prints_cpu_info(m, adev);
3559
3560         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3561                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3562         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3563                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3564         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3565                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3566         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3567                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3568         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3569                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3570         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3571                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3572         size = sizeof(uint32_t);
3573         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3574                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3575         size = sizeof(value);
3576         seq_printf(m, "\n");
3577
3578         /* GPU Temp */
3579         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3580                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3581
3582         /* GPU Load */
3583         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3584                 seq_printf(m, "GPU Load: %u %%\n", value);
3585         /* MEM Load */
3586         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3587                 seq_printf(m, "MEM Load: %u %%\n", value);
3588
3589         seq_printf(m, "\n");
3590
3591         /* SMC feature mask */
3592         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3593                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3594
3595         if (adev->asic_type > CHIP_VEGA20) {
3596                 /* VCN clocks */
3597                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3598                         if (!value) {
3599                                 seq_printf(m, "VCN: Disabled\n");
3600                         } else {
3601                                 seq_printf(m, "VCN: Enabled\n");
3602                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3603                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3604                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3605                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3606                         }
3607                 }
3608                 seq_printf(m, "\n");
3609         } else {
3610                 /* UVD clocks */
3611                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3612                         if (!value) {
3613                                 seq_printf(m, "UVD: Disabled\n");
3614                         } else {
3615                                 seq_printf(m, "UVD: Enabled\n");
3616                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3617                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3618                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3619                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3620                         }
3621                 }
3622                 seq_printf(m, "\n");
3623
3624                 /* VCE clocks */
3625                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3626                         if (!value) {
3627                                 seq_printf(m, "VCE: Disabled\n");
3628                         } else {
3629                                 seq_printf(m, "VCE: Enabled\n");
3630                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3631                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3632                         }
3633                 }
3634         }
3635
3636         return 0;
3637 }
3638
3639 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3640 {
3641         int i;
3642
3643         for (i = 0; clocks[i].flag; i++)
3644                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3645                            (flags & clocks[i].flag) ? "On" : "Off");
3646 }
3647
3648 static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
3649 {
3650         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3651         struct drm_device *dev = adev_to_drm(adev);
3652         u32 flags = 0;
3653         int r;
3654
3655         if (amdgpu_in_reset(adev))
3656                 return -EPERM;
3657         if (adev->in_suspend && !adev->in_runpm)
3658                 return -EPERM;
3659
3660         r = pm_runtime_get_sync(dev->dev);
3661         if (r < 0) {
3662                 pm_runtime_put_autosuspend(dev->dev);
3663                 return r;
3664         }
3665
3666         if (!adev->pm.dpm_enabled) {
3667                 seq_printf(m, "dpm not enabled\n");
3668                 pm_runtime_mark_last_busy(dev->dev);
3669                 pm_runtime_put_autosuspend(dev->dev);
3670                 return 0;
3671         }
3672
3673         if (!is_support_sw_smu(adev) &&
3674             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3675                 mutex_lock(&adev->pm.mutex);
3676                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3677                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3678                 else
3679                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3680                 mutex_unlock(&adev->pm.mutex);
3681                 r = 0;
3682         } else {
3683                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3684         }
3685         if (r)
3686                 goto out;
3687
3688         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3689
3690         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3691         amdgpu_parse_cg_state(m, flags);
3692         seq_printf(m, "\n");
3693
3694 out:
3695         pm_runtime_mark_last_busy(dev->dev);
3696         pm_runtime_put_autosuspend(dev->dev);
3697
3698         return r;
3699 }
3700
3701 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
3702
3703 /*
3704  * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
3705  *
3706  * Reads debug memory region allocated to PMFW
3707  */
3708 static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
3709                                          size_t size, loff_t *pos)
3710 {
3711         struct amdgpu_device *adev = file_inode(f)->i_private;
3712         const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
3713         void *pp_handle = adev->powerplay.pp_handle;
3714         size_t smu_prv_buf_size;
3715         void *smu_prv_buf;
3716
3717         if (amdgpu_in_reset(adev))
3718                 return -EPERM;
3719         if (adev->in_suspend && !adev->in_runpm)
3720                 return -EPERM;
3721
3722         if (pp_funcs && pp_funcs->get_smu_prv_buf_details)
3723                 pp_funcs->get_smu_prv_buf_details(pp_handle, &smu_prv_buf,
3724                                                   &smu_prv_buf_size);
3725         else
3726                 return -ENOSYS;
3727
3728         if (!smu_prv_buf || !smu_prv_buf_size)
3729                 return -EINVAL;
3730
3731         return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
3732                                        smu_prv_buf_size);
3733 }
3734
3735 static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
3736         .owner = THIS_MODULE,
3737         .open = simple_open,
3738         .read = amdgpu_pm_prv_buffer_read,
3739         .llseek = default_llseek,
3740 };
3741
3742 #endif
3743
3744 void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3745 {
3746 #if defined(CONFIG_DEBUG_FS)
3747         struct drm_minor *minor = adev_to_drm(adev)->primary;
3748         struct dentry *root = minor->debugfs_root;
3749
3750         debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
3751                             &amdgpu_debugfs_pm_info_fops);
3752
3753         if (adev->pm.smu_prv_buffer_size > 0)
3754                 debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
3755                                          adev,
3756                                          &amdgpu_debugfs_pm_prv_buffer_fops,
3757                                          adev->pm.smu_prv_buffer_size);
3758 #endif
3759 }