drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <[email protected]>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477, lan8804
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35 #include <linux/gpio/consumer.h>
  36
  37 /* Operation Mode Strap Override */
  38 #define MII_KSZPHY_OMSO                         0x16
  39 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  40 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  41 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  42 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  43 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  44
  45 /* general Interrupt control/status reg in vendor specific block. */
  46 #define MII_KSZPHY_INTCS                        0x1B
  47 #define KSZPHY_INTCS_JABBER                     BIT(15)
  48 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  49 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  50 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  51 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  52 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  53 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  54 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  55 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  56                                                 KSZPHY_INTCS_LINK_DOWN)
  57 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  58 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  59 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  60                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  61
  62 /* LinkMD Control/Status */
  63 #define KSZ8081_LMD                             0x1d
  64 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  65 #define KSZ8081_LMD_STAT_NORMAL                 0
  66 #define KSZ8081_LMD_STAT_OPEN                   1
  67 #define KSZ8081_LMD_STAT_SHORT                  2
  68 #define KSZ8081_LMD_STAT_FAIL                   3
  69 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  70 /* Short cable (<10 meter) has been detected by LinkMD */
  71 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  72 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  73
  74 #define KSZ9x31_LMD                             0x12
  75 #define KSZ9x31_LMD_VCT_EN                      BIT(15)
  76 #define KSZ9x31_LMD_VCT_DIS_TX                  BIT(14)
  77 #define KSZ9x31_LMD_VCT_PAIR(n)                 (((n) & 0x3) << 12)
  78 #define KSZ9x31_LMD_VCT_SEL_RESULT              0
  79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI            BIT(10)
  80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO            BIT(11)
  81 #define KSZ9x31_LMD_VCT_SEL_MASK                GENMASK(11, 10)
  82 #define KSZ9x31_LMD_VCT_ST_NORMAL               0
  83 #define KSZ9x31_LMD_VCT_ST_OPEN                 1
  84 #define KSZ9x31_LMD_VCT_ST_SHORT                2
  85 #define KSZ9x31_LMD_VCT_ST_FAIL                 3
  86 #define KSZ9x31_LMD_VCT_ST_MASK                 GENMASK(9, 8)
  87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID  BIT(7)
  88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG  BIT(6)
  89 #define KSZ9x31_LMD_VCT_DATA_MASK100            BIT(5)
  90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP            BIT(4)
  91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK      GENMASK(3, 2)
  92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK      GENMASK(1, 0)
  93 #define KSZ9x31_LMD_VCT_DATA_MASK               GENMASK(7, 0)
  94
  95 #define KSZPHY_WIRE_PAIR_MASK                   0x3
  96
  97 #define LAN8814_CABLE_DIAG                      0x12
  98 #define LAN8814_CABLE_DIAG_STAT_MASK            GENMASK(9, 8)
  99 #define LAN8814_CABLE_DIAG_VCT_DATA_MASK        GENMASK(7, 0)
 100 #define LAN8814_PAIR_BIT_SHIFT                  12
 101
 102 #define LAN8814_WIRE_PAIR_MASK                  0xF
 103
 104 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
 105 #define LAN8814_INTC                            0x18
 106 #define LAN8814_INTS                            0x1B
 107
 108 #define LAN8814_INT_LINK_DOWN                   BIT(2)
 109 #define LAN8814_INT_LINK_UP                     BIT(0)
 110 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
 111                                                  LAN8814_INT_LINK_DOWN)
 112
 113 #define LAN8814_INTR_CTRL_REG                   0x34
 114 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
 115 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
 116
 117 /* Represents 1ppm adjustment in 2^32 format with
 118  * each nsec contains 4 clock cycles.
 119  * The value is calculated as following: (1/1000000)/((2^-32)/4)
 120  */
 121 #define LAN8814_1PPM_FORMAT                     17179
 122
 123 #define PTP_RX_MOD                              0x024F
 124 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 125 #define PTP_RX_TIMESTAMP_EN                     0x024D
 126 #define PTP_TX_TIMESTAMP_EN                     0x028D
 127
 128 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
 129 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
 130 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 131 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 132
 133 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 134 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 135
 136 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 137 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 138 #define LTC_HARD_RESET                          0x023F
 139 #define LTC_HARD_RESET_                         BIT(0)
 140
 141 #define TSU_HARD_RESET                          0x02C1
 142 #define TSU_HARD_RESET_                         BIT(0)
 143
 144 #define PTP_CMD_CTL                             0x0200
 145 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 146 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 147 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 148 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 149 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 150 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 151
 152 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 153 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 154 #define PTP_CLOCK_SET_NS_HI                     0x0208
 155 #define PTP_CLOCK_SET_NS_LO                     0x0209
 156
 157 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 158 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 159 #define PTP_CLOCK_READ_NS_HI                    0x022C
 160 #define PTP_CLOCK_READ_NS_LO                    0x022D
 161
 162 #define PTP_OPERATING_MODE                      0x0241
 163 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 164
 165 #define PTP_TX_MOD                              0x028F
 166 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 167 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 168
 169 #define PTP_RX_PARSE_CONFIG                     0x0242
 170 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 171 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 172 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 173
 174 #define PTP_TX_PARSE_CONFIG                     0x0282
 175 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 176 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 177 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 178
 179 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 180 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 181 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 182
 183 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 184 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 185 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 186
 187 #define LAN8814_INTR_STS_REG                    0x0033
 188 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 189 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 190 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 191 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 192
 193 #define PTP_CAP_INFO                            0x022A
 194 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 195 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 196
 197 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 198 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 199 #define PTP_TX_EGRESS_NS_HI                     0x0294
 200 #define PTP_TX_EGRESS_NS_LO                     0x0295
 201 #define PTP_TX_MSG_HEADER2                      0x0299
 202
 203 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 204 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 205 #define PTP_RX_INGRESS_NS_HI                    0x0254
 206 #define PTP_RX_INGRESS_NS_LO                    0x0255
 207 #define PTP_RX_MSG_HEADER2                      0x0259
 208
 209 #define PTP_TSU_INT_EN                          0x0200
 210 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 211 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 212 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 213 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 214
 215 #define PTP_TSU_INT_STS                         0x0201
 216 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 217 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 218 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 219 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 220
 221 #define LAN8814_LED_CTRL_1                      0x0
 222 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_    BIT(6)
 223
 224 /* PHY Control 1 */
 225 #define MII_KSZPHY_CTRL_1                       0x1e
 226 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 227
 228 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 229 #define MII_KSZPHY_CTRL_2                       0x1f
 230 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 231 /* bitmap of PHY register to set interrupt mode */
 232 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 233 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 234 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 235 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 236 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 237 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 238 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 239
 240 /* Write/read to/from extended registers */
 241 #define MII_KSZPHY_EXTREG                       0x0b
 242 #define KSZPHY_EXTREG_WRITE                     0x8000
 243
 244 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 245 #define MII_KSZPHY_EXTREG_READ                  0x0d
 246
 247 /* Extended registers */
 248 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 249 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 250 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 251
 252 #define PS_TO_REG                               200
 253 #define FIFO_SIZE                               8
 254
 255 /* Delay used to get the second part from the LTC */
 256 #define LAN8841_GET_SEC_LTC_DELAY               (500 * NSEC_PER_MSEC)
 257
 258 struct kszphy_hw_stat {
 259         const char *string;
 260         u8 reg;
 261         u8 bits;
 262 };
 263
 264 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 265         { "phy_receive_errors", 21, 16},
 266         { "phy_idle_errors", 10, 8 },
 267 };
 268
 269 struct kszphy_type {
 270         u32 led_mode_reg;
 271         u16 interrupt_level_mask;
 272         u16 cable_diag_reg;
 273         unsigned long pair_mask;
 274         u16 disable_dll_tx_bit;
 275         u16 disable_dll_rx_bit;
 276         u16 disable_dll_mask;
 277         bool has_broadcast_disable;
 278         bool has_nand_tree_disable;
 279         bool has_rmii_ref_clk_sel;
 280 };
 281
 282 /* Shared structure between the PHYs of the same package. */
 283 struct lan8814_shared_priv {
 284         struct phy_device *phydev;
 285         struct ptp_clock *ptp_clock;
 286         struct ptp_clock_info ptp_clock_info;
 287
 288         /* Reference counter to how many ports in the package are enabling the
 289          * timestamping
 290          */
 291         u8 ref;
 292
 293         /* Lock for ptp_clock and ref */
 294         struct mutex shared_lock;
 295 };
 296
 297 struct lan8814_ptp_rx_ts {
 298         struct list_head list;
 299         u32 seconds;
 300         u32 nsec;
 301         u16 seq_id;
 302 };
 303
 304 struct kszphy_ptp_priv {
 305         struct mii_timestamper mii_ts;
 306         struct phy_device *phydev;
 307
 308         struct sk_buff_head tx_queue;
 309         struct sk_buff_head rx_queue;
 310
 311         struct list_head rx_ts_list;
 312         /* Lock for Rx ts fifo */
 313         spinlock_t rx_ts_lock;
 314
 315         int hwts_tx_type;
 316         enum hwtstamp_rx_filters rx_filter;
 317         int layer;
 318         int version;
 319
 320         struct ptp_clock *ptp_clock;
 321         struct ptp_clock_info ptp_clock_info;
 322         /* Lock for ptp_clock */
 323         struct mutex ptp_lock;
 324         struct ptp_pin_desc *pin_config;
 325
 326         s64 seconds;
 327         /* Lock for accessing seconds */
 328         spinlock_t seconds_lock;
 329 };
 330
 331 struct kszphy_priv {
 332         struct kszphy_ptp_priv ptp_priv;
 333         const struct kszphy_type *type;
 334         int led_mode;
 335         u16 vct_ctrl1000;
 336         bool rmii_ref_clk_sel;
 337         bool rmii_ref_clk_sel_val;
 338         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 339 };
 340
 341 static const struct kszphy_type lan8814_type = {
 342         .led_mode_reg           = ~LAN8814_LED_CTRL_1,
 343         .cable_diag_reg         = LAN8814_CABLE_DIAG,
 344         .pair_mask              = LAN8814_WIRE_PAIR_MASK,
 345 };
 346
 347 static const struct kszphy_type ksz886x_type = {
 348         .cable_diag_reg         = KSZ8081_LMD,
 349         .pair_mask              = KSZPHY_WIRE_PAIR_MASK,
 350 };
 351
 352 static const struct kszphy_type ksz8021_type = {
 353         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 354         .has_broadcast_disable  = true,
 355         .has_nand_tree_disable  = true,
 356         .has_rmii_ref_clk_sel   = true,
 357 };
 358
 359 static const struct kszphy_type ksz8041_type = {
 360         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 361 };
 362
 363 static const struct kszphy_type ksz8051_type = {
 364         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 365         .has_nand_tree_disable  = true,
 366 };
 367
 368 static const struct kszphy_type ksz8081_type = {
 369         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 370         .has_broadcast_disable  = true,
 371         .has_nand_tree_disable  = true,
 372         .has_rmii_ref_clk_sel   = true,
 373 };
 374
 375 static const struct kszphy_type ks8737_type = {
 376         .interrupt_level_mask   = BIT(14),
 377 };
 378
 379 static const struct kszphy_type ksz9021_type = {
 380         .interrupt_level_mask   = BIT(14),
 381 };
 382
 383 static const struct kszphy_type ksz9131_type = {
 384         .interrupt_level_mask   = BIT(14),
 385         .disable_dll_tx_bit     = BIT(12),
 386         .disable_dll_rx_bit     = BIT(12),
 387         .disable_dll_mask       = BIT_MASK(12),
 388 };
 389
 390 static const struct kszphy_type lan8841_type = {
 391         .disable_dll_tx_bit     = BIT(14),
 392         .disable_dll_rx_bit     = BIT(14),
 393         .disable_dll_mask       = BIT_MASK(14),
 394         .cable_diag_reg         = LAN8814_CABLE_DIAG,
 395         .pair_mask              = LAN8814_WIRE_PAIR_MASK,
 396 };
 397
 398 static int kszphy_extended_write(struct phy_device *phydev,
 399                                 u32 regnum, u16 val)
 400 {
 401         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 402         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 403 }
 404
 405 static int kszphy_extended_read(struct phy_device *phydev,
 406                                 u32 regnum)
 407 {
 408         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 409         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 410 }
 411
 412 static int kszphy_ack_interrupt(struct phy_device *phydev)
 413 {
 414         /* bit[7..0] int status, which is a read and clear register. */
 415         int rc;
 416
 417         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 418
 419         return (rc < 0) ? rc : 0;
 420 }
 421
 422 static int kszphy_config_intr(struct phy_device *phydev)
 423 {
 424         const struct kszphy_type *type = phydev->drv->driver_data;
 425         int temp, err;
 426         u16 mask;
 427
 428         if (type && type->interrupt_level_mask)
 429                 mask = type->interrupt_level_mask;
 430         else
 431                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 432
 433         /* set the interrupt pin active low */
 434         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 435         if (temp < 0)
 436                 return temp;
 437         temp &= ~mask;
 438         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 439
 440         /* enable / disable interrupts */
 441         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 442                 err = kszphy_ack_interrupt(phydev);
 443                 if (err)
 444                         return err;
 445
 446                 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
 447         } else {
 448                 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
 449                 if (err)
 450                         return err;
 451
 452                 err = kszphy_ack_interrupt(phydev);
 453         }
 454
 455         return err;
 456 }
 457
 458 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 459 {
 460         int irq_status;
 461
 462         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 463         if (irq_status < 0) {
 464                 phy_error(phydev);
 465                 return IRQ_NONE;
 466         }
 467
 468         if (!(irq_status & KSZPHY_INTCS_STATUS))
 469                 return IRQ_NONE;
 470
 471         phy_trigger_machine(phydev);
 472
 473         return IRQ_HANDLED;
 474 }
 475
 476 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 477 {
 478         int ctrl;
 479
 480         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 481         if (ctrl < 0)
 482                 return ctrl;
 483
 484         if (val)
 485                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 486         else
 487                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 488
 489         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 490 }
 491
 492 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 493 {
 494         int rc, temp, shift;
 495
 496         switch (reg) {
 497         case MII_KSZPHY_CTRL_1:
 498                 shift = 14;
 499                 break;
 500         case MII_KSZPHY_CTRL_2:
 501                 shift = 4;
 502                 break;
 503         default:
 504                 return -EINVAL;
 505         }
 506
 507         temp = phy_read(phydev, reg);
 508         if (temp < 0) {
 509                 rc = temp;
 510                 goto out;
 511         }
 512
 513         temp &= ~(3 << shift);
 514         temp |= val << shift;
 515         rc = phy_write(phydev, reg, temp);
 516 out:
 517         if (rc < 0)
 518                 phydev_err(phydev, "failed to set led mode\n");
 519
 520         return rc;
 521 }
 522
 523 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 524  * unique (non-broadcast) address on a shared bus.
 525  */
 526 static int kszphy_broadcast_disable(struct phy_device *phydev)
 527 {
 528         int ret;
 529
 530         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 531         if (ret < 0)
 532                 goto out;
 533
 534         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 535 out:
 536         if (ret)
 537                 phydev_err(phydev, "failed to disable broadcast address\n");
 538
 539         return ret;
 540 }
 541
 542 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 543 {
 544         int ret;
 545
 546         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 547         if (ret < 0)
 548                 goto out;
 549
 550         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 551                 return 0;
 552
 553         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 554                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 555 out:
 556         if (ret)
 557                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 558
 559         return ret;
 560 }
 561
 562 /* Some config bits need to be set again on resume, handle them here. */
 563 static int kszphy_config_reset(struct phy_device *phydev)
 564 {
 565         struct kszphy_priv *priv = phydev->priv;
 566         int ret;
 567
 568         if (priv->rmii_ref_clk_sel) {
 569                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 570                 if (ret) {
 571                         phydev_err(phydev,
 572                                    "failed to set rmii reference clock\n");
 573                         return ret;
 574                 }
 575         }
 576
 577         if (priv->type && priv->led_mode >= 0)
 578                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 579
 580         return 0;
 581 }
 582
 583 static int kszphy_config_init(struct phy_device *phydev)
 584 {
 585         struct kszphy_priv *priv = phydev->priv;
 586         const struct kszphy_type *type;
 587
 588         if (!priv)
 589                 return 0;
 590
 591         type = priv->type;
 592
 593         if (type && type->has_broadcast_disable)
 594                 kszphy_broadcast_disable(phydev);
 595
 596         if (type && type->has_nand_tree_disable)
 597                 kszphy_nand_tree_disable(phydev);
 598
 599         return kszphy_config_reset(phydev);
 600 }
 601
 602 static int ksz8041_fiber_mode(struct phy_device *phydev)
 603 {
 604         struct device_node *of_node = phydev->mdio.dev.of_node;
 605
 606         return of_property_read_bool(of_node, "micrel,fiber-mode");
 607 }
 608
 609 static int ksz8041_config_init(struct phy_device *phydev)
 610 {
 611         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 612
 613         /* Limit supported and advertised modes in fiber mode */
 614         if (ksz8041_fiber_mode(phydev)) {
 615                 phydev->dev_flags |= MICREL_PHY_FXEN;
 616                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 617                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 618
 619                 linkmode_and(phydev->supported, phydev->supported, mask);
 620                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 621                                  phydev->supported);
 622                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 623                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 624                                  phydev->advertising);
 625                 phydev->autoneg = AUTONEG_DISABLE;
 626         }
 627
 628         return kszphy_config_init(phydev);
 629 }
 630
 631 static int ksz8041_config_aneg(struct phy_device *phydev)
 632 {
 633         /* Skip auto-negotiation in fiber mode */
 634         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 635                 phydev->speed = SPEED_100;
 636                 return 0;
 637         }
 638
 639         return genphy_config_aneg(phydev);
 640 }
 641
 642 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 643                                             const bool ksz_8051)
 644 {
 645         int ret;
 646
 647         if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
 648                 return 0;
 649
 650         ret = phy_read(phydev, MII_BMSR);
 651         if (ret < 0)
 652                 return ret;
 653
 654         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 655          * exact PHY ID. However, they can be told apart by the extended
 656          * capability registers presence. The KSZ8051 PHY has them while
 657          * the switch does not.
 658          */
 659         ret &= BMSR_ERCAP;
 660         if (ksz_8051)
 661                 return ret;
 662         else
 663                 return !ret;
 664 }
 665
 666 static int ksz8051_match_phy_device(struct phy_device *phydev)
 667 {
 668         return ksz8051_ksz8795_match_phy_device(phydev, true);
 669 }
 670
 671 static int ksz8081_config_init(struct phy_device *phydev)
 672 {
 673         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 674          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 675          * pull-down is missing, the factory test mode should be cleared by
 676          * manually writing a 0.
 677          */
 678         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 679
 680         return kszphy_config_init(phydev);
 681 }
 682
 683 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 684 {
 685         u16 val;
 686
 687         switch (ctrl) {
 688         case ETH_TP_MDI:
 689                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 690                 break;
 691         case ETH_TP_MDI_X:
 692                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 693                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 694                 break;
 695         case ETH_TP_MDI_AUTO:
 696                 val = 0;
 697                 break;
 698         default:
 699                 return 0;
 700         }
 701
 702         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 703                           KSZ8081_CTRL2_HP_MDIX |
 704                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 705                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 706                           KSZ8081_CTRL2_HP_MDIX | val);
 707 }
 708
 709 static int ksz8081_config_aneg(struct phy_device *phydev)
 710 {
 711         int ret;
 712
 713         ret = genphy_config_aneg(phydev);
 714         if (ret)
 715                 return ret;
 716
 717         /* The MDI-X configuration is automatically changed by the PHY after
 718          * switching from autoneg off to on. So, take MDI-X configuration under
 719          * own control and set it after autoneg configuration was done.
 720          */
 721         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 722 }
 723
 724 static int ksz8081_mdix_update(struct phy_device *phydev)
 725 {
 726         int ret;
 727
 728         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 729         if (ret < 0)
 730                 return ret;
 731
 732         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 733                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 734                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 735                 else
 736                         phydev->mdix_ctrl = ETH_TP_MDI;
 737         } else {
 738                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 739         }
 740
 741         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 742         if (ret < 0)
 743                 return ret;
 744
 745         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 746                 phydev->mdix = ETH_TP_MDI;
 747         else
 748                 phydev->mdix = ETH_TP_MDI_X;
 749
 750         return 0;
 751 }
 752
 753 static int ksz8081_read_status(struct phy_device *phydev)
 754 {
 755         int ret;
 756
 757         ret = ksz8081_mdix_update(phydev);
 758         if (ret < 0)
 759                 return ret;
 760
 761         return genphy_read_status(phydev);
 762 }
 763
 764 static int ksz8061_config_init(struct phy_device *phydev)
 765 {
 766         int ret;
 767
 768         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 769         if (ret)
 770                 return ret;
 771
 772         return kszphy_config_init(phydev);
 773 }
 774
 775 static int ksz8795_match_phy_device(struct phy_device *phydev)
 776 {
 777         return ksz8051_ksz8795_match_phy_device(phydev, false);
 778 }
 779
 780 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 781                                        const struct device_node *of_node,
 782                                        u16 reg,
 783                                        const char *field1, const char *field2,
 784                                        const char *field3, const char *field4)
 785 {
 786         int val1 = -1;
 787         int val2 = -2;
 788         int val3 = -3;
 789         int val4 = -4;
 790         int newval;
 791         int matches = 0;
 792
 793         if (!of_property_read_u32(of_node, field1, &val1))
 794                 matches++;
 795
 796         if (!of_property_read_u32(of_node, field2, &val2))
 797                 matches++;
 798
 799         if (!of_property_read_u32(of_node, field3, &val3))
 800                 matches++;
 801
 802         if (!of_property_read_u32(of_node, field4, &val4))
 803                 matches++;
 804
 805         if (!matches)
 806                 return 0;
 807
 808         if (matches < 4)
 809                 newval = kszphy_extended_read(phydev, reg);
 810         else
 811                 newval = 0;
 812
 813         if (val1 != -1)
 814                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 815
 816         if (val2 != -2)
 817                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 818
 819         if (val3 != -3)
 820                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 821
 822         if (val4 != -4)
 823                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 824
 825         return kszphy_extended_write(phydev, reg, newval);
 826 }
 827
 828 static int ksz9021_config_init(struct phy_device *phydev)
 829 {
 830         const struct device_node *of_node;
 831         const struct device *dev_walker;
 832
 833         /* The Micrel driver has a deprecated option to place phy OF
 834          * properties in the MAC node. Walk up the tree of devices to
 835          * find a device with an OF node.
 836          */
 837         dev_walker = &phydev->mdio.dev;
 838         do {
 839                 of_node = dev_walker->of_node;
 840                 dev_walker = dev_walker->parent;
 841
 842         } while (!of_node && dev_walker);
 843
 844         if (of_node) {
 845                 ksz9021_load_values_from_of(phydev, of_node,
 846                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 847                                     "txen-skew-ps", "txc-skew-ps",
 848                                     "rxdv-skew-ps", "rxc-skew-ps");
 849                 ksz9021_load_values_from_of(phydev, of_node,
 850                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 851                                     "rxd0-skew-ps", "rxd1-skew-ps",
 852                                     "rxd2-skew-ps", "rxd3-skew-ps");
 853                 ksz9021_load_values_from_of(phydev, of_node,
 854                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 855                                     "txd0-skew-ps", "txd1-skew-ps",
 856                                     "txd2-skew-ps", "txd3-skew-ps");
 857         }
 858         return 0;
 859 }
 860
 861 #define KSZ9031_PS_TO_REG               60
 862
 863 /* Extended registers */
 864 /* MMD Address 0x0 */
 865 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 866 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 867
 868 /* MMD Address 0x2 */
 869 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 870 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 871 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 872
 873 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 874 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 875 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 876 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 877 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 878
 879 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 880 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 881 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 882 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 883 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 884
 885 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 886 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 887 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 888
 889 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 890  * provide different RGMII options we need to configure delay offset
 891  * for each pad relative to build in delay.
 892  */
 893 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 894  * 1.80ns
 895  */
 896 #define RX_ID                           0x7
 897 #define RX_CLK_ID                       0x19
 898
 899 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 900  * internal 1.2ns delay.
 901  */
 902 #define RX_ND                           0xc
 903 #define RX_CLK_ND                       0x0
 904
 905 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 906 #define TX_ID                           0x0
 907 #define TX_CLK_ID                       0x1f
 908
 909 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 910  * dealy
 911  */
 912 #define TX_ND                           0x7
 913 #define TX_CLK_ND                       0xf
 914
 915 /* MMD Address 0x1C */
 916 #define MII_KSZ9031RN_EDPD              0x23
 917 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 918
 919 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 920                                        const struct device_node *of_node,
 921                                        u16 reg, size_t field_sz,
 922                                        const char *field[], u8 numfields,
 923                                        bool *update)
 924 {
 925         int val[4] = {-1, -2, -3, -4};
 926         int matches = 0;
 927         u16 mask;
 928         u16 maxval;
 929         u16 newval;
 930         int i;
 931
 932         for (i = 0; i < numfields; i++)
 933                 if (!of_property_read_u32(of_node, field[i], val + i))
 934                         matches++;
 935
 936         if (!matches)
 937                 return 0;
 938
 939         *update |= true;
 940
 941         if (matches < numfields)
 942                 newval = phy_read_mmd(phydev, 2, reg);
 943         else
 944                 newval = 0;
 945
 946         maxval = (field_sz == 4) ? 0xf : 0x1f;
 947         for (i = 0; i < numfields; i++)
 948                 if (val[i] != -(i + 1)) {
 949                         mask = 0xffff;
 950                         mask ^= maxval << (field_sz * i);
 951                         newval = (newval & mask) |
 952                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 953                                         << (field_sz * i));
 954                 }
 955
 956         return phy_write_mmd(phydev, 2, reg, newval);
 957 }
 958
 959 /* Center KSZ9031RNX FLP timing at 16ms. */
 960 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 961 {
 962         int result;
 963
 964         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 965                                0x0006);
 966         if (result)
 967                 return result;
 968
 969         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 970                                0x1A80);
 971         if (result)
 972                 return result;
 973
 974         return genphy_restart_aneg(phydev);
 975 }
 976
 977 /* Enable energy-detect power-down mode */
 978 static int ksz9031_enable_edpd(struct phy_device *phydev)
 979 {
 980         int reg;
 981
 982         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 983         if (reg < 0)
 984                 return reg;
 985         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 986                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 987 }
 988
 989 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 990 {
 991         u16 rx, tx, rx_clk, tx_clk;
 992         int ret;
 993
 994         switch (phydev->interface) {
 995         case PHY_INTERFACE_MODE_RGMII:
 996                 tx = TX_ND;
 997                 tx_clk = TX_CLK_ND;
 998                 rx = RX_ND;
 999                 rx_clk = RX_CLK_ND;
1000                 break;
1001         case PHY_INTERFACE_MODE_RGMII_ID:
1002                 tx = TX_ID;
1003                 tx_clk = TX_CLK_ID;
1004                 rx = RX_ID;
1005                 rx_clk = RX_CLK_ID;
1006                 break;
1007         case PHY_INTERFACE_MODE_RGMII_RXID:
1008                 tx = TX_ND;
1009                 tx_clk = TX_CLK_ND;
1010                 rx = RX_ID;
1011                 rx_clk = RX_CLK_ID;
1012                 break;
1013         case PHY_INTERFACE_MODE_RGMII_TXID:
1014                 tx = TX_ID;
1015                 tx_clk = TX_CLK_ID;
1016                 rx = RX_ND;
1017                 rx_clk = RX_CLK_ND;
1018                 break;
1019         default:
1020                 return 0;
1021         }
1022
1023         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1024                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1025                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1026         if (ret < 0)
1027                 return ret;
1028
1029         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1030                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1031                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1032                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1033                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1034         if (ret < 0)
1035                 return ret;
1036
1037         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1038                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1039                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1040                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1041                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1042         if (ret < 0)
1043                 return ret;
1044
1045         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1046                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1047                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1048 }
1049
1050 static int ksz9031_config_init(struct phy_device *phydev)
1051 {
1052         const struct device_node *of_node;
1053         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1054         static const char *rx_data_skews[4] = {
1055                 "rxd0-skew-ps", "rxd1-skew-ps",
1056                 "rxd2-skew-ps", "rxd3-skew-ps"
1057         };
1058         static const char *tx_data_skews[4] = {
1059                 "txd0-skew-ps", "txd1-skew-ps",
1060                 "txd2-skew-ps", "txd3-skew-ps"
1061         };
1062         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1063         const struct device *dev_walker;
1064         int result;
1065
1066         result = ksz9031_enable_edpd(phydev);
1067         if (result < 0)
1068                 return result;
1069
1070         /* The Micrel driver has a deprecated option to place phy OF
1071          * properties in the MAC node. Walk up the tree of devices to
1072          * find a device with an OF node.
1073          */
1074         dev_walker = &phydev->mdio.dev;
1075         do {
1076                 of_node = dev_walker->of_node;
1077                 dev_walker = dev_walker->parent;
1078         } while (!of_node && dev_walker);
1079
1080         if (of_node) {
1081                 bool update = false;
1082
1083                 if (phy_interface_is_rgmii(phydev)) {
1084                         result = ksz9031_config_rgmii_delay(phydev);
1085                         if (result < 0)
1086                                 return result;
1087                 }
1088
1089                 ksz9031_of_load_skew_values(phydev, of_node,
1090                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1091                                 clk_skews, 2, &update);
1092
1093                 ksz9031_of_load_skew_values(phydev, of_node,
1094                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1095                                 control_skews, 2, &update);
1096
1097                 ksz9031_of_load_skew_values(phydev, of_node,
1098                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1099                                 rx_data_skews, 4, &update);
1100
1101                 ksz9031_of_load_skew_values(phydev, of_node,
1102                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1103                                 tx_data_skews, 4, &update);
1104
1105                 if (update && !phy_interface_is_rgmii(phydev))
1106                         phydev_warn(phydev,
1107                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1108
1109                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1110                  * When the device links in the 1000BASE-T slave mode only,
1111                  * the optional 125MHz reference output clock (CLK125_NDO)
1112                  * has wide duty cycle variation.
1113                  *
1114                  * The optional CLK125_NDO clock does not meet the RGMII
1115                  * 45/55 percent (min/max) duty cycle requirement and therefore
1116                  * cannot be used directly by the MAC side for clocking
1117                  * applications that have setup/hold time requirements on
1118                  * rising and falling clock edges.
1119                  *
1120                  * Workaround:
1121                  * Force the phy to be the master to receive a stable clock
1122                  * which meets the duty cycle requirement.
1123                  */
1124                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1125                         result = phy_read(phydev, MII_CTRL1000);
1126                         if (result < 0)
1127                                 goto err_force_master;
1128
1129                         /* enable master mode, config & prefer master */
1130                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1131                         result = phy_write(phydev, MII_CTRL1000, result);
1132                         if (result < 0)
1133                                 goto err_force_master;
1134                 }
1135         }
1136
1137         return ksz9031_center_flp_timing(phydev);
1138
1139 err_force_master:
1140         phydev_err(phydev, "failed to force the phy to master mode\n");
1141         return result;
1142 }
1143
1144 #define KSZ9131_SKEW_5BIT_MAX   2400
1145 #define KSZ9131_SKEW_4BIT_MAX   800
1146 #define KSZ9131_OFFSET          700
1147 #define KSZ9131_STEP            100
1148
1149 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1150                                        struct device_node *of_node,
1151                                        u16 reg, size_t field_sz,
1152                                        char *field[], u8 numfields)
1153 {
1154         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1155                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1156         int skewval, skewmax = 0;
1157         int matches = 0;
1158         u16 maxval;
1159         u16 newval;
1160         u16 mask;
1161         int i;
1162
1163         /* psec properties in dts should mean x pico seconds */
1164         if (field_sz == 5)
1165                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1166         else
1167                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1168
1169         for (i = 0; i < numfields; i++)
1170                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1171                         if (skewval < -KSZ9131_OFFSET)
1172                                 skewval = -KSZ9131_OFFSET;
1173                         else if (skewval > skewmax)
1174                                 skewval = skewmax;
1175
1176                         val[i] = skewval + KSZ9131_OFFSET;
1177                         matches++;
1178                 }
1179
1180         if (!matches)
1181                 return 0;
1182
1183         if (matches < numfields)
1184                 newval = phy_read_mmd(phydev, 2, reg);
1185         else
1186                 newval = 0;
1187
1188         maxval = (field_sz == 4) ? 0xf : 0x1f;
1189         for (i = 0; i < numfields; i++)
1190                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1191                         mask = 0xffff;
1192                         mask ^= maxval << (field_sz * i);
1193                         newval = (newval & mask) |
1194                                 (((val[i] / KSZ9131_STEP) & maxval)
1195                                         << (field_sz * i));
1196                 }
1197
1198         return phy_write_mmd(phydev, 2, reg, newval);
1199 }
1200
1201 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1202 #define KSZ9131RN_RXC_DLL_CTRL          76
1203 #define KSZ9131RN_TXC_DLL_CTRL          77
1204 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1205
1206 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1207 {
1208         const struct kszphy_type *type = phydev->drv->driver_data;
1209         u16 rxcdll_val, txcdll_val;
1210         int ret;
1211
1212         switch (phydev->interface) {
1213         case PHY_INTERFACE_MODE_RGMII:
1214                 rxcdll_val = type->disable_dll_rx_bit;
1215                 txcdll_val = type->disable_dll_tx_bit;
1216                 break;
1217         case PHY_INTERFACE_MODE_RGMII_ID:
1218                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1219                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1220                 break;
1221         case PHY_INTERFACE_MODE_RGMII_RXID:
1222                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1223                 txcdll_val = type->disable_dll_tx_bit;
1224                 break;
1225         case PHY_INTERFACE_MODE_RGMII_TXID:
1226                 rxcdll_val = type->disable_dll_rx_bit;
1227                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1228                 break;
1229         default:
1230                 return 0;
1231         }
1232
1233         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1234                              KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1235                              rxcdll_val);
1236         if (ret < 0)
1237                 return ret;
1238
1239         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1240                               KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1241                               txcdll_val);
1242 }
1243
1244 /* Silicon Errata DS80000693B
1245  *
1246  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1247  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1248  * according to the datasheet (off if there is no link).
1249  */
1250 static int ksz9131_led_errata(struct phy_device *phydev)
1251 {
1252         int reg;
1253
1254         reg = phy_read_mmd(phydev, 2, 0);
1255         if (reg < 0)
1256                 return reg;
1257
1258         if (!(reg & BIT(4)))
1259                 return 0;
1260
1261         return phy_set_bits(phydev, 0x1e, BIT(9));
1262 }
1263
1264 static int ksz9131_config_init(struct phy_device *phydev)
1265 {
1266         struct device_node *of_node;
1267         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1268         char *rx_data_skews[4] = {
1269                 "rxd0-skew-psec", "rxd1-skew-psec",
1270                 "rxd2-skew-psec", "rxd3-skew-psec"
1271         };
1272         char *tx_data_skews[4] = {
1273                 "txd0-skew-psec", "txd1-skew-psec",
1274                 "txd2-skew-psec", "txd3-skew-psec"
1275         };
1276         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1277         const struct device *dev_walker;
1278         int ret;
1279
1280         dev_walker = &phydev->mdio.dev;
1281         do {
1282                 of_node = dev_walker->of_node;
1283                 dev_walker = dev_walker->parent;
1284         } while (!of_node && dev_walker);
1285
1286         if (!of_node)
1287                 return 0;
1288
1289         if (phy_interface_is_rgmii(phydev)) {
1290                 ret = ksz9131_config_rgmii_delay(phydev);
1291                 if (ret < 0)
1292                         return ret;
1293         }
1294
1295         ret = ksz9131_of_load_skew_values(phydev, of_node,
1296                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1297                                           clk_skews, 2);
1298         if (ret < 0)
1299                 return ret;
1300
1301         ret = ksz9131_of_load_skew_values(phydev, of_node,
1302                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1303                                           control_skews, 2);
1304         if (ret < 0)
1305                 return ret;
1306
1307         ret = ksz9131_of_load_skew_values(phydev, of_node,
1308                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1309                                           rx_data_skews, 4);
1310         if (ret < 0)
1311                 return ret;
1312
1313         ret = ksz9131_of_load_skew_values(phydev, of_node,
1314                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1315                                           tx_data_skews, 4);
1316         if (ret < 0)
1317                 return ret;
1318
1319         ret = ksz9131_led_errata(phydev);
1320         if (ret < 0)
1321                 return ret;
1322
1323         return 0;
1324 }
1325
1326 #define MII_KSZ9131_AUTO_MDIX           0x1C
1327 #define MII_KSZ9131_AUTO_MDI_SET        BIT(7)
1328 #define MII_KSZ9131_AUTO_MDIX_SWAP_OFF  BIT(6)
1329
1330 static int ksz9131_mdix_update(struct phy_device *phydev)
1331 {
1332         int ret;
1333
1334         ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1335         if (ret < 0)
1336                 return ret;
1337
1338         if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1339                 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1340                         phydev->mdix_ctrl = ETH_TP_MDI;
1341                 else
1342                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1343         } else {
1344                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1345         }
1346
1347         if (ret & MII_KSZ9131_AUTO_MDI_SET)
1348                 phydev->mdix = ETH_TP_MDI;
1349         else
1350                 phydev->mdix = ETH_TP_MDI_X;
1351
1352         return 0;
1353 }
1354
1355 static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1356 {
1357         u16 val;
1358
1359         switch (ctrl) {
1360         case ETH_TP_MDI:
1361                 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1362                       MII_KSZ9131_AUTO_MDI_SET;
1363                 break;
1364         case ETH_TP_MDI_X:
1365                 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1366                 break;
1367         case ETH_TP_MDI_AUTO:
1368                 val = 0;
1369                 break;
1370         default:
1371                 return 0;
1372         }
1373
1374         return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1375                           MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1376                           MII_KSZ9131_AUTO_MDI_SET, val);
1377 }
1378
1379 static int ksz9131_read_status(struct phy_device *phydev)
1380 {
1381         int ret;
1382
1383         ret = ksz9131_mdix_update(phydev);
1384         if (ret < 0)
1385                 return ret;
1386
1387         return genphy_read_status(phydev);
1388 }
1389
1390 static int ksz9131_config_aneg(struct phy_device *phydev)
1391 {
1392         int ret;
1393
1394         ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1395         if (ret)
1396                 return ret;
1397
1398         return genphy_config_aneg(phydev);
1399 }
1400
1401 static int ksz9477_get_features(struct phy_device *phydev)
1402 {
1403         int ret;
1404
1405         ret = genphy_read_abilities(phydev);
1406         if (ret)
1407                 return ret;
1408
1409         /* The "EEE control and capability 1" (Register 3.20) seems to be
1410          * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1411          * on the 7.60 will affect 3.20. So, we need to construct our own list
1412          * of caps.
1413          * KSZ8563R should have 100BaseTX/Full only.
1414          */
1415         linkmode_and(phydev->supported_eee, phydev->supported,
1416                      PHY_EEE_CAP1_FEATURES);
1417
1418         return 0;
1419 }
1420
1421 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1422 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1423 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1424 static int ksz8873mll_read_status(struct phy_device *phydev)
1425 {
1426         int regval;
1427
1428         /* dummy read */
1429         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1430
1431         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1432
1433         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1434                 phydev->duplex = DUPLEX_HALF;
1435         else
1436                 phydev->duplex = DUPLEX_FULL;
1437
1438         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1439                 phydev->speed = SPEED_10;
1440         else
1441                 phydev->speed = SPEED_100;
1442
1443         phydev->link = 1;
1444         phydev->pause = phydev->asym_pause = 0;
1445
1446         return 0;
1447 }
1448
1449 static int ksz9031_get_features(struct phy_device *phydev)
1450 {
1451         int ret;
1452
1453         ret = genphy_read_abilities(phydev);
1454         if (ret < 0)
1455                 return ret;
1456
1457         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1458          * Whenever the device's Asymmetric Pause capability is set to 1,
1459          * link-up may fail after a link-up to link-down transition.
1460          *
1461          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1462          *
1463          * Workaround:
1464          * Do not enable the Asymmetric Pause capability bit.
1465          */
1466         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1467
1468         /* We force setting the Pause capability as the core will force the
1469          * Asymmetric Pause capability to 1 otherwise.
1470          */
1471         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1472
1473         return 0;
1474 }
1475
1476 static int ksz9031_read_status(struct phy_device *phydev)
1477 {
1478         int err;
1479         int regval;
1480
1481         err = genphy_read_status(phydev);
1482         if (err)
1483                 return err;
1484
1485         /* Make sure the PHY is not broken. Read idle error count,
1486          * and reset the PHY if it is maxed out.
1487          */
1488         regval = phy_read(phydev, MII_STAT1000);
1489         if ((regval & 0xFF) == 0xFF) {
1490                 phy_init_hw(phydev);
1491                 phydev->link = 0;
1492                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1493                         phydev->drv->config_intr(phydev);
1494                 return genphy_config_aneg(phydev);
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1501 {
1502         struct kszphy_priv *priv = phydev->priv;
1503         int ret;
1504
1505         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1506          * Prior to running the cable diagnostics, Auto-negotiation should
1507          * be disabled, full duplex set and the link speed set to 1000Mbps
1508          * via the Basic Control Register.
1509          */
1510         ret = phy_modify(phydev, MII_BMCR,
1511                          BMCR_SPEED1000 | BMCR_FULLDPLX |
1512                          BMCR_ANENABLE | BMCR_SPEED100,
1513                          BMCR_SPEED1000 | BMCR_FULLDPLX);
1514         if (ret)
1515                 return ret;
1516
1517         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1518          * The Master-Slave configuration should be set to Slave by writing
1519          * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1520          * Register.
1521          */
1522         ret = phy_read(phydev, MII_CTRL1000);
1523         if (ret < 0)
1524                 return ret;
1525
1526         /* Cache these bits, they need to be restored once LinkMD finishes. */
1527         priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1528         ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1529         ret |= CTL1000_ENABLE_MASTER;
1530
1531         return phy_write(phydev, MII_CTRL1000, ret);
1532 }
1533
1534 static int ksz9x31_cable_test_result_trans(u16 status)
1535 {
1536         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1537         case KSZ9x31_LMD_VCT_ST_NORMAL:
1538                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1539         case KSZ9x31_LMD_VCT_ST_OPEN:
1540                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1541         case KSZ9x31_LMD_VCT_ST_SHORT:
1542                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1543         case KSZ9x31_LMD_VCT_ST_FAIL:
1544                 fallthrough;
1545         default:
1546                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1547         }
1548 }
1549
1550 static bool ksz9x31_cable_test_failed(u16 status)
1551 {
1552         int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1553
1554         return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1555 }
1556
1557 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1558 {
1559         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1560         case KSZ9x31_LMD_VCT_ST_OPEN:
1561                 fallthrough;
1562         case KSZ9x31_LMD_VCT_ST_SHORT:
1563                 return true;
1564         }
1565         return false;
1566 }
1567
1568 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1569 {
1570         int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1571
1572         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1573          *
1574          * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1575          */
1576         if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1577                 dt = clamp(dt - 22, 0, 255);
1578
1579         return (dt * 400) / 10;
1580 }
1581
1582 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1583 {
1584         int val, ret;
1585
1586         ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1587                                     !(val & KSZ9x31_LMD_VCT_EN),
1588                                     30000, 100000, true);
1589
1590         return ret < 0 ? ret : 0;
1591 }
1592
1593 static int ksz9x31_cable_test_get_pair(int pair)
1594 {
1595         static const int ethtool_pair[] = {
1596                 ETHTOOL_A_CABLE_PAIR_A,
1597                 ETHTOOL_A_CABLE_PAIR_B,
1598                 ETHTOOL_A_CABLE_PAIR_C,
1599                 ETHTOOL_A_CABLE_PAIR_D,
1600         };
1601
1602         return ethtool_pair[pair];
1603 }
1604
1605 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1606 {
1607         int ret, val;
1608
1609         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1610          * To test each individual cable pair, set the cable pair in the Cable
1611          * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1612          * Diagnostic Register, along with setting the Cable Diagnostics Test
1613          * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1614          * will self clear when the test is concluded.
1615          */
1616         ret = phy_write(phydev, KSZ9x31_LMD,
1617                         KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1618         if (ret)
1619                 return ret;
1620
1621         ret = ksz9x31_cable_test_wait_for_completion(phydev);
1622         if (ret)
1623                 return ret;
1624
1625         val = phy_read(phydev, KSZ9x31_LMD);
1626         if (val < 0)
1627                 return val;
1628
1629         if (ksz9x31_cable_test_failed(val))
1630                 return -EAGAIN;
1631
1632         ret = ethnl_cable_test_result(phydev,
1633                                       ksz9x31_cable_test_get_pair(pair),
1634                                       ksz9x31_cable_test_result_trans(val));
1635         if (ret)
1636                 return ret;
1637
1638         if (!ksz9x31_cable_test_fault_length_valid(val))
1639                 return 0;
1640
1641         return ethnl_cable_test_fault_length(phydev,
1642                                              ksz9x31_cable_test_get_pair(pair),
1643                                              ksz9x31_cable_test_fault_length(phydev, val));
1644 }
1645
1646 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1647                                          bool *finished)
1648 {
1649         struct kszphy_priv *priv = phydev->priv;
1650         unsigned long pair_mask = 0xf;
1651         int retries = 20;
1652         int pair, ret, rv;
1653
1654         *finished = false;
1655
1656         /* Try harder if link partner is active */
1657         while (pair_mask && retries--) {
1658                 for_each_set_bit(pair, &pair_mask, 4) {
1659                         ret = ksz9x31_cable_test_one_pair(phydev, pair);
1660                         if (ret == -EAGAIN)
1661                                 continue;
1662                         if (ret < 0)
1663                                 return ret;
1664                         clear_bit(pair, &pair_mask);
1665                 }
1666                 /* If link partner is in autonegotiation mode it will send 2ms
1667                  * of FLPs with at least 6ms of silence.
1668                  * Add 2ms sleep to have better chances to hit this silence.
1669                  */
1670                 if (pair_mask)
1671                         usleep_range(2000, 3000);
1672         }
1673
1674         /* Report remaining unfinished pair result as unknown. */
1675         for_each_set_bit(pair, &pair_mask, 4) {
1676                 ret = ethnl_cable_test_result(phydev,
1677                                               ksz9x31_cable_test_get_pair(pair),
1678                                               ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1679         }
1680
1681         *finished = true;
1682
1683         /* Restore cached bits from before LinkMD got started. */
1684         rv = phy_modify(phydev, MII_CTRL1000,
1685                         CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1686                         priv->vct_ctrl1000);
1687         if (rv)
1688                 return rv;
1689
1690         return ret;
1691 }
1692
1693 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1694 {
1695         return 0;
1696 }
1697
1698 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1699 {
1700         u16 val;
1701
1702         switch (ctrl) {
1703         case ETH_TP_MDI:
1704                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1705                 break;
1706         case ETH_TP_MDI_X:
1707                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1708                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1709                  * sheet seems to be missing:
1710                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1711                  * 0 = Normal operation (transmit on TX+/TX- pins)
1712                  */
1713                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1714                 break;
1715         case ETH_TP_MDI_AUTO:
1716                 val = 0;
1717                 break;
1718         default:
1719                 return 0;
1720         }
1721
1722         return phy_modify(phydev, MII_BMCR,
1723                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1724                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1725                           KSZ886X_BMCR_HP_MDIX | val);
1726 }
1727
1728 static int ksz886x_config_aneg(struct phy_device *phydev)
1729 {
1730         int ret;
1731
1732         ret = genphy_config_aneg(phydev);
1733         if (ret)
1734                 return ret;
1735
1736         /* The MDI-X configuration is automatically changed by the PHY after
1737          * switching from autoneg off to on. So, take MDI-X configuration under
1738          * own control and set it after autoneg configuration was done.
1739          */
1740         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1741 }
1742
1743 static int ksz886x_mdix_update(struct phy_device *phydev)
1744 {
1745         int ret;
1746
1747         ret = phy_read(phydev, MII_BMCR);
1748         if (ret < 0)
1749                 return ret;
1750
1751         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1752                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1753                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1754                 else
1755                         phydev->mdix_ctrl = ETH_TP_MDI;
1756         } else {
1757                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1758         }
1759
1760         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1761         if (ret < 0)
1762                 return ret;
1763
1764         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1765         if (ret & KSZ886X_CTRL_MDIX_STAT)
1766                 phydev->mdix = ETH_TP_MDI_X;
1767         else
1768                 phydev->mdix = ETH_TP_MDI;
1769
1770         return 0;
1771 }
1772
1773 static int ksz886x_read_status(struct phy_device *phydev)
1774 {
1775         int ret;
1776
1777         ret = ksz886x_mdix_update(phydev);
1778         if (ret < 0)
1779                 return ret;
1780
1781         return genphy_read_status(phydev);
1782 }
1783
1784 struct ksz9477_errata_write {
1785         u8 dev_addr;
1786         u8 reg_addr;
1787         u16 val;
1788 };
1789
1790 static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1791          /* Register settings are needed to improve PHY receive performance */
1792         {0x01, 0x6f, 0xdd0b},
1793         {0x01, 0x8f, 0x6032},
1794         {0x01, 0x9d, 0x248c},
1795         {0x01, 0x75, 0x0060},
1796         {0x01, 0xd3, 0x7777},
1797         {0x1c, 0x06, 0x3008},
1798         {0x1c, 0x08, 0x2000},
1799
1800         /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1801         {0x1c, 0x04, 0x00d0},
1802
1803         /* Energy Efficient Ethernet (EEE) feature select must be manually disabled */
1804         {0x07, 0x3c, 0x0000},
1805
1806         /* Register settings are required to meet data sheet supply current specifications */
1807         {0x1c, 0x13, 0x6eff},
1808         {0x1c, 0x14, 0xe6ff},
1809         {0x1c, 0x15, 0x6eff},
1810         {0x1c, 0x16, 0xe6ff},
1811         {0x1c, 0x17, 0x00ff},
1812         {0x1c, 0x18, 0x43ff},
1813         {0x1c, 0x19, 0xc3ff},
1814         {0x1c, 0x1a, 0x6fff},
1815         {0x1c, 0x1b, 0x07ff},
1816         {0x1c, 0x1c, 0x0fff},
1817         {0x1c, 0x1d, 0xe7ff},
1818         {0x1c, 0x1e, 0xefff},
1819         {0x1c, 0x20, 0xeeee},
1820 };
1821
1822 static int ksz9477_config_init(struct phy_device *phydev)
1823 {
1824         int err;
1825         int i;
1826
1827         /* Apply PHY settings to address errata listed in
1828          * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1829          * Silicon Errata and Data Sheet Clarification documents.
1830          *
1831          * Document notes: Before configuring the PHY MMD registers, it is
1832          * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1833          * disabled by writing to register 0xN100-0xN101. After writing the
1834          * MMD registers, and after all errata workarounds that involve PHY
1835          * register settings, write register 0xN100-0xN101 again to enable
1836          * and restart auto-negotiation.
1837          */
1838         err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1839         if (err)
1840                 return err;
1841
1842         for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1843                 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1844
1845                 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1846                 if (err)
1847                         return err;
1848         }
1849
1850         err = genphy_restart_aneg(phydev);
1851         if (err)
1852                 return err;
1853
1854         return kszphy_config_init(phydev);
1855 }
1856
1857 static int kszphy_get_sset_count(struct phy_device *phydev)
1858 {
1859         return ARRAY_SIZE(kszphy_hw_stats);
1860 }
1861
1862 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1863 {
1864         int i;
1865
1866         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1867                 strscpy(data + i * ETH_GSTRING_LEN,
1868                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1869         }
1870 }
1871
1872 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1873 {
1874         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1875         struct kszphy_priv *priv = phydev->priv;
1876         int val;
1877         u64 ret;
1878
1879         val = phy_read(phydev, stat.reg);
1880         if (val < 0) {
1881                 ret = U64_MAX;
1882         } else {
1883                 val = val & ((1 << stat.bits) - 1);
1884                 priv->stats[i] += val;
1885                 ret = priv->stats[i];
1886         }
1887
1888         return ret;
1889 }
1890
1891 static void kszphy_get_stats(struct phy_device *phydev,
1892                              struct ethtool_stats *stats, u64 *data)
1893 {
1894         int i;
1895
1896         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1897                 data[i] = kszphy_get_stat(phydev, i);
1898 }
1899
1900 static int kszphy_suspend(struct phy_device *phydev)
1901 {
1902         /* Disable PHY Interrupts */
1903         if (phy_interrupt_is_valid(phydev)) {
1904                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1905                 if (phydev->drv->config_intr)
1906                         phydev->drv->config_intr(phydev);
1907         }
1908
1909         return genphy_suspend(phydev);
1910 }
1911
1912 static void kszphy_parse_led_mode(struct phy_device *phydev)
1913 {
1914         const struct kszphy_type *type = phydev->drv->driver_data;
1915         const struct device_node *np = phydev->mdio.dev.of_node;
1916         struct kszphy_priv *priv = phydev->priv;
1917         int ret;
1918
1919         if (type && type->led_mode_reg) {
1920                 ret = of_property_read_u32(np, "micrel,led-mode",
1921                                            &priv->led_mode);
1922
1923                 if (ret)
1924                         priv->led_mode = -1;
1925
1926                 if (priv->led_mode > 3) {
1927                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1928                                    priv->led_mode);
1929                         priv->led_mode = -1;
1930                 }
1931         } else {
1932                 priv->led_mode = -1;
1933         }
1934 }
1935
1936 static int kszphy_resume(struct phy_device *phydev)
1937 {
1938         int ret;
1939
1940         genphy_resume(phydev);
1941
1942         /* After switching from power-down to normal mode, an internal global
1943          * reset is automatically generated. Wait a minimum of 1 ms before
1944          * read/write access to the PHY registers.
1945          */
1946         usleep_range(1000, 2000);
1947
1948         ret = kszphy_config_reset(phydev);
1949         if (ret)
1950                 return ret;
1951
1952         /* Enable PHY Interrupts */
1953         if (phy_interrupt_is_valid(phydev)) {
1954                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1955                 if (phydev->drv->config_intr)
1956                         phydev->drv->config_intr(phydev);
1957         }
1958
1959         return 0;
1960 }
1961
1962 static int kszphy_probe(struct phy_device *phydev)
1963 {
1964         const struct kszphy_type *type = phydev->drv->driver_data;
1965         const struct device_node *np = phydev->mdio.dev.of_node;
1966         struct kszphy_priv *priv;
1967         struct clk *clk;
1968
1969         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1970         if (!priv)
1971                 return -ENOMEM;
1972
1973         phydev->priv = priv;
1974
1975         priv->type = type;
1976
1977         kszphy_parse_led_mode(phydev);
1978
1979         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1980         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1981         if (!IS_ERR_OR_NULL(clk)) {
1982                 unsigned long rate = clk_get_rate(clk);
1983                 bool rmii_ref_clk_sel_25_mhz;
1984
1985                 if (type)
1986                         priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1987                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1988                                 "micrel,rmii-reference-clock-select-25-mhz");
1989
1990                 if (rate > 24500000 && rate < 25500000) {
1991                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1992                 } else if (rate > 49500000 && rate < 50500000) {
1993                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1994                 } else {
1995                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1996                                    rate);
1997                         return -EINVAL;
1998                 }
1999         }
2000
2001         if (ksz8041_fiber_mode(phydev))
2002                 phydev->port = PORT_FIBRE;
2003
2004         /* Support legacy board-file configuration */
2005         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2006                 priv->rmii_ref_clk_sel = true;
2007                 priv->rmii_ref_clk_sel_val = true;
2008         }
2009
2010         return 0;
2011 }
2012
2013 static int lan8814_cable_test_start(struct phy_device *phydev)
2014 {
2015         /* If autoneg is enabled, we won't be able to test cross pair
2016          * short. In this case, the PHY will "detect" a link and
2017          * confuse the internal state machine - disable auto neg here.
2018          * Set the speed to 1000mbit and full duplex.
2019          */
2020         return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2021                           BMCR_SPEED1000 | BMCR_FULLDPLX);
2022 }
2023
2024 static int ksz886x_cable_test_start(struct phy_device *phydev)
2025 {
2026         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2027                 return -EOPNOTSUPP;
2028
2029         /* If autoneg is enabled, we won't be able to test cross pair
2030          * short. In this case, the PHY will "detect" a link and
2031          * confuse the internal state machine - disable auto neg here.
2032          * If autoneg is disabled, we should set the speed to 10mbit.
2033          */
2034         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2035 }
2036
2037 static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2038 {
2039         switch (FIELD_GET(mask, status)) {
2040         case KSZ8081_LMD_STAT_NORMAL:
2041                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2042         case KSZ8081_LMD_STAT_SHORT:
2043                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2044         case KSZ8081_LMD_STAT_OPEN:
2045                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2046         case KSZ8081_LMD_STAT_FAIL:
2047                 fallthrough;
2048         default:
2049                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2050         }
2051 }
2052
2053 static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2054 {
2055         return FIELD_GET(mask, status) ==
2056                 KSZ8081_LMD_STAT_FAIL;
2057 }
2058
2059 static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2060 {
2061         switch (FIELD_GET(mask, status)) {
2062         case KSZ8081_LMD_STAT_OPEN:
2063                 fallthrough;
2064         case KSZ8081_LMD_STAT_SHORT:
2065                 return true;
2066         }
2067         return false;
2068 }
2069
2070 static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2071                                                            u16 status, u16 data_mask)
2072 {
2073         int dt;
2074
2075         /* According to the data sheet the distance to the fault is
2076          * DELTA_TIME * 0.4 meters for ksz phys.
2077          * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2078          */
2079         dt = FIELD_GET(data_mask, status);
2080
2081         if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2082                 return ((dt - 22) * 800) / 10;
2083         else
2084                 return (dt * 400) / 10;
2085 }
2086
2087 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2088 {
2089         const struct kszphy_type *type = phydev->drv->driver_data;
2090         int val, ret;
2091
2092         ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2093                                     !(val & KSZ8081_LMD_ENABLE_TEST),
2094                                     30000, 100000, true);
2095
2096         return ret < 0 ? ret : 0;
2097 }
2098
2099 static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2100 {
2101         static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2102                                             ETHTOOL_A_CABLE_PAIR_B,
2103                                             ETHTOOL_A_CABLE_PAIR_C,
2104                                             ETHTOOL_A_CABLE_PAIR_D,
2105                                           };
2106         u32 fault_length;
2107         int ret;
2108         int val;
2109
2110         val = KSZ8081_LMD_ENABLE_TEST;
2111         val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2112
2113         ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2114         if (ret < 0)
2115                 return ret;
2116
2117         ret = ksz886x_cable_test_wait_for_completion(phydev);
2118         if (ret)
2119                 return ret;
2120
2121         val = phy_read(phydev, LAN8814_CABLE_DIAG);
2122         if (val < 0)
2123                 return val;
2124
2125         if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2126                 return -EAGAIN;
2127
2128         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2129                                       ksz886x_cable_test_result_trans(val,
2130                                                                       LAN8814_CABLE_DIAG_STAT_MASK
2131                                                                       ));
2132         if (ret)
2133                 return ret;
2134
2135         if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2136                 return 0;
2137
2138         fault_length = ksz886x_cable_test_fault_length(phydev, val,
2139                                                        LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2140
2141         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2142 }
2143
2144 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2145 {
2146         static const int ethtool_pair[] = {
2147                 ETHTOOL_A_CABLE_PAIR_A,
2148                 ETHTOOL_A_CABLE_PAIR_B,
2149         };
2150         int ret, val, mdix;
2151         u32 fault_length;
2152
2153         /* There is no way to choice the pair, like we do one ksz9031.
2154          * We can workaround this limitation by using the MDI-X functionality.
2155          */
2156         if (pair == 0)
2157                 mdix = ETH_TP_MDI;
2158         else
2159                 mdix = ETH_TP_MDI_X;
2160
2161         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2162         case PHY_ID_KSZ8081:
2163                 ret = ksz8081_config_mdix(phydev, mdix);
2164                 break;
2165         case PHY_ID_KSZ886X:
2166                 ret = ksz886x_config_mdix(phydev, mdix);
2167                 break;
2168         default:
2169                 ret = -ENODEV;
2170         }
2171
2172         if (ret)
2173                 return ret;
2174
2175         /* Now we are ready to fire. This command will send a 100ns pulse
2176          * to the pair.
2177          */
2178         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2179         if (ret)
2180                 return ret;
2181
2182         ret = ksz886x_cable_test_wait_for_completion(phydev);
2183         if (ret)
2184                 return ret;
2185
2186         val = phy_read(phydev, KSZ8081_LMD);
2187         if (val < 0)
2188                 return val;
2189
2190         if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2191                 return -EAGAIN;
2192
2193         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2194                                       ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2195         if (ret)
2196                 return ret;
2197
2198         if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2199                 return 0;
2200
2201         fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2202
2203         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2204 }
2205
2206 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2207                                          bool *finished)
2208 {
2209         const struct kszphy_type *type = phydev->drv->driver_data;
2210         unsigned long pair_mask = type->pair_mask;
2211         int retries = 20;
2212         int ret = 0;
2213         int pair;
2214
2215         *finished = false;
2216
2217         /* Try harder if link partner is active */
2218         while (pair_mask && retries--) {
2219                 for_each_set_bit(pair, &pair_mask, 4) {
2220                         if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2221                                 ret = lan8814_cable_test_one_pair(phydev, pair);
2222                         else
2223                                 ret = ksz886x_cable_test_one_pair(phydev, pair);
2224                         if (ret == -EAGAIN)
2225                                 continue;
2226                         if (ret < 0)
2227                                 return ret;
2228                         clear_bit(pair, &pair_mask);
2229                 }
2230                 /* If link partner is in autonegotiation mode it will send 2ms
2231                  * of FLPs with at least 6ms of silence.
2232                  * Add 2ms sleep to have better chances to hit this silence.
2233                  */
2234                 if (pair_mask)
2235                         msleep(2);
2236         }
2237
2238         *finished = true;
2239
2240         return ret;
2241 }
2242
2243 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
2244 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
2245 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
2246
2247 #define LAN8814_QSGMII_SOFT_RESET                       0x43
2248 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
2249 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
2250 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
2251 #define LAN8814_ALIGN_SWAP                              0x4a
2252 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
2253 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
2254
2255 #define LAN8804_ALIGN_SWAP                              0x4a
2256 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
2257 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
2258 #define LAN8814_CLOCK_MANAGEMENT                        0xd
2259 #define LAN8814_LINK_QUALITY                            0x8e
2260
2261 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2262 {
2263         int data;
2264
2265         phy_lock_mdio_bus(phydev);
2266         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2267         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2268         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2269                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2270         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2271         phy_unlock_mdio_bus(phydev);
2272
2273         return data;
2274 }
2275
2276 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2277                                  u16 val)
2278 {
2279         phy_lock_mdio_bus(phydev);
2280         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2281         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2282         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2283                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2284
2285         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2286         if (val != 0)
2287                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2288                            val);
2289         phy_unlock_mdio_bus(phydev);
2290         return val;
2291 }
2292
2293 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2294 {
2295         u16 val = 0;
2296
2297         if (enable)
2298                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2299                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2300                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2301                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2302
2303         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2304 }
2305
2306 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2307                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2308 {
2309         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2310         *seconds = (*seconds << 16) |
2311                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2312
2313         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2314         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2315                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2316
2317         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2318 }
2319
2320 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2321                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2322 {
2323         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2324         *seconds = *seconds << 16 |
2325                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2326
2327         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2328         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2329                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2330
2331         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2332 }
2333
2334 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2335 {
2336         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2337         struct phy_device *phydev = ptp_priv->phydev;
2338         struct lan8814_shared_priv *shared = phydev->shared->priv;
2339
2340         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2341                                 SOF_TIMESTAMPING_RX_HARDWARE |
2342                                 SOF_TIMESTAMPING_RAW_HARDWARE;
2343
2344         info->phc_index = ptp_clock_index(shared->ptp_clock);
2345
2346         info->tx_types =
2347                 (1 << HWTSTAMP_TX_OFF) |
2348                 (1 << HWTSTAMP_TX_ON) |
2349                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2350
2351         info->rx_filters =
2352                 (1 << HWTSTAMP_FILTER_NONE) |
2353                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2354                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2355                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2356                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2357
2358         return 0;
2359 }
2360
2361 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2362 {
2363         int i;
2364
2365         for (i = 0; i < FIFO_SIZE; ++i)
2366                 lanphy_read_page_reg(phydev, 5,
2367                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2368
2369         /* Read to clear overflow status bit */
2370         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2371 }
2372
2373 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2374 {
2375         struct kszphy_ptp_priv *ptp_priv =
2376                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2377         struct phy_device *phydev = ptp_priv->phydev;
2378         struct lan8814_shared_priv *shared = phydev->shared->priv;
2379         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2380         struct hwtstamp_config config;
2381         int txcfg = 0, rxcfg = 0;
2382         int pkt_ts_enable;
2383
2384         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2385                 return -EFAULT;
2386
2387         ptp_priv->hwts_tx_type = config.tx_type;
2388         ptp_priv->rx_filter = config.rx_filter;
2389
2390         switch (config.rx_filter) {
2391         case HWTSTAMP_FILTER_NONE:
2392                 ptp_priv->layer = 0;
2393                 ptp_priv->version = 0;
2394                 break;
2395         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2396         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2397         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2398                 ptp_priv->layer = PTP_CLASS_L4;
2399                 ptp_priv->version = PTP_CLASS_V2;
2400                 break;
2401         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2402         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2403         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2404                 ptp_priv->layer = PTP_CLASS_L2;
2405                 ptp_priv->version = PTP_CLASS_V2;
2406                 break;
2407         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2408         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2409         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2410                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2411                 ptp_priv->version = PTP_CLASS_V2;
2412                 break;
2413         default:
2414                 return -ERANGE;
2415         }
2416
2417         if (ptp_priv->layer & PTP_CLASS_L2) {
2418                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2419                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2420         } else if (ptp_priv->layer & PTP_CLASS_L4) {
2421                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2422                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2423         }
2424         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2425         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2426
2427         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2428                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2429         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2430         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2431
2432         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2433                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2434                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2435
2436         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2437                 lan8814_config_ts_intr(ptp_priv->phydev, true);
2438         else
2439                 lan8814_config_ts_intr(ptp_priv->phydev, false);
2440
2441         mutex_lock(&shared->shared_lock);
2442         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2443                 shared->ref++;
2444         else
2445                 shared->ref--;
2446
2447         if (shared->ref)
2448                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2449                                       PTP_CMD_CTL_PTP_ENABLE_);
2450         else
2451                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2452                                       PTP_CMD_CTL_PTP_DISABLE_);
2453         mutex_unlock(&shared->shared_lock);
2454
2455         /* In case of multiple starts and stops, these needs to be cleared */
2456         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2457                 list_del(&rx_ts->list);
2458                 kfree(rx_ts);
2459         }
2460         skb_queue_purge(&ptp_priv->rx_queue);
2461         skb_queue_purge(&ptp_priv->tx_queue);
2462
2463         lan8814_flush_fifo(ptp_priv->phydev, false);
2464         lan8814_flush_fifo(ptp_priv->phydev, true);
2465
2466         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2467 }
2468
2469 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2470                              struct sk_buff *skb, int type)
2471 {
2472         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2473
2474         switch (ptp_priv->hwts_tx_type) {
2475         case HWTSTAMP_TX_ONESTEP_SYNC:
2476                 if (ptp_msg_is_sync(skb, type)) {
2477                         kfree_skb(skb);
2478                         return;
2479                 }
2480                 fallthrough;
2481         case HWTSTAMP_TX_ON:
2482                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2483                 skb_queue_tail(&ptp_priv->tx_queue, skb);
2484                 break;
2485         case HWTSTAMP_TX_OFF:
2486         default:
2487                 kfree_skb(skb);
2488                 break;
2489         }
2490 }
2491
2492 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2493 {
2494         struct ptp_header *ptp_header;
2495         u32 type;
2496
2497         skb_push(skb, ETH_HLEN);
2498         type = ptp_classify_raw(skb);
2499         ptp_header = ptp_parse_header(skb, type);
2500         skb_pull_inline(skb, ETH_HLEN);
2501
2502         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2503 }
2504
2505 static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2506                                  struct sk_buff *skb)
2507 {
2508         struct skb_shared_hwtstamps *shhwtstamps;
2509         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2510         unsigned long flags;
2511         bool ret = false;
2512         u16 skb_sig;
2513
2514         lan8814_get_sig_rx(skb, &skb_sig);
2515
2516         /* Iterate over all RX timestamps and match it with the received skbs */
2517         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2518         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2519                 /* Check if we found the signature we were looking for. */
2520                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2521                         continue;
2522
2523                 shhwtstamps = skb_hwtstamps(skb);
2524                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2525                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2526                                                   rx_ts->nsec);
2527                 list_del(&rx_ts->list);
2528                 kfree(rx_ts);
2529
2530                 ret = true;
2531                 break;
2532         }
2533         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2534
2535         if (ret)
2536                 netif_rx(skb);
2537         return ret;
2538 }
2539
2540 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2541 {
2542         struct kszphy_ptp_priv *ptp_priv =
2543                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2544
2545         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2546             type == PTP_CLASS_NONE)
2547                 return false;
2548
2549         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2550                 return false;
2551
2552         /* If we failed to match then add it to the queue for when the timestamp
2553          * will come
2554          */
2555         if (!lan8814_match_rx_skb(ptp_priv, skb))
2556                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2557
2558         return true;
2559 }
2560
2561 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2562                                   u32 seconds, u32 nano_seconds)
2563 {
2564         u32 sec_low, sec_high, nsec_low, nsec_high;
2565
2566         sec_low = seconds & 0xffff;
2567         sec_high = (seconds >> 16) & 0xffff;
2568         nsec_low = nano_seconds & 0xffff;
2569         nsec_high = (nano_seconds >> 16) & 0x3fff;
2570
2571         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2572         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2573         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2574         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2575
2576         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2577 }
2578
2579 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2580                                   u32 *seconds, u32 *nano_seconds)
2581 {
2582         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2583
2584         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2585         *seconds = (*seconds << 16) |
2586                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2587
2588         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2589         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2590                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2591 }
2592
2593 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2594                                    struct timespec64 *ts)
2595 {
2596         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2597                                                           ptp_clock_info);
2598         struct phy_device *phydev = shared->phydev;
2599         u32 nano_seconds;
2600         u32 seconds;
2601
2602         mutex_lock(&shared->shared_lock);
2603         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2604         mutex_unlock(&shared->shared_lock);
2605         ts->tv_sec = seconds;
2606         ts->tv_nsec = nano_seconds;
2607
2608         return 0;
2609 }
2610
2611 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2612                                    const struct timespec64 *ts)
2613 {
2614         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2615                                                           ptp_clock_info);
2616         struct phy_device *phydev = shared->phydev;
2617
2618         mutex_lock(&shared->shared_lock);
2619         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2620         mutex_unlock(&shared->shared_lock);
2621
2622         return 0;
2623 }
2624
2625 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2626                                    s64 time_step_ns)
2627 {
2628         u32 nano_seconds_step;
2629         u64 abs_time_step_ns;
2630         u32 unsigned_seconds;
2631         u32 nano_seconds;
2632         u32 remainder;
2633         s32 seconds;
2634
2635         if (time_step_ns >  15000000000LL) {
2636                 /* convert to clock set */
2637                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2638                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2639                                                 &remainder);
2640                 nano_seconds += remainder;
2641                 if (nano_seconds >= 1000000000) {
2642                         unsigned_seconds++;
2643                         nano_seconds -= 1000000000;
2644                 }
2645                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2646                 return;
2647         } else if (time_step_ns < -15000000000LL) {
2648                 /* convert to clock set */
2649                 time_step_ns = -time_step_ns;
2650
2651                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2652                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2653                                                 &remainder);
2654                 nano_seconds_step = remainder;
2655                 if (nano_seconds < nano_seconds_step) {
2656                         unsigned_seconds--;
2657                         nano_seconds += 1000000000;
2658                 }
2659                 nano_seconds -= nano_seconds_step;
2660                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2661                                       nano_seconds);
2662                 return;
2663         }
2664
2665         /* do clock step */
2666         if (time_step_ns >= 0) {
2667                 abs_time_step_ns = (u64)time_step_ns;
2668                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2669                                            &remainder);
2670                 nano_seconds = remainder;
2671         } else {
2672                 abs_time_step_ns = (u64)(-time_step_ns);
2673                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2674                             &remainder));
2675                 nano_seconds = remainder;
2676                 if (nano_seconds > 0) {
2677                         /* subtracting nano seconds is not allowed
2678                          * convert to subtracting from seconds,
2679                          * and adding to nanoseconds
2680                          */
2681                         seconds--;
2682                         nano_seconds = (1000000000 - nano_seconds);
2683                 }
2684         }
2685
2686         if (nano_seconds > 0) {
2687                 /* add 8 ns to cover the likely normal increment */
2688                 nano_seconds += 8;
2689         }
2690
2691         if (nano_seconds >= 1000000000) {
2692                 /* carry into seconds */
2693                 seconds++;
2694                 nano_seconds -= 1000000000;
2695         }
2696
2697         while (seconds) {
2698                 if (seconds > 0) {
2699                         u32 adjustment_value = (u32)seconds;
2700                         u16 adjustment_value_lo, adjustment_value_hi;
2701
2702                         if (adjustment_value > 0xF)
2703                                 adjustment_value = 0xF;
2704
2705                         adjustment_value_lo = adjustment_value & 0xffff;
2706                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2707
2708                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2709                                               adjustment_value_lo);
2710                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2711                                               PTP_LTC_STEP_ADJ_DIR_ |
2712                                               adjustment_value_hi);
2713                         seconds -= ((s32)adjustment_value);
2714                 } else {
2715                         u32 adjustment_value = (u32)(-seconds);
2716                         u16 adjustment_value_lo, adjustment_value_hi;
2717
2718                         if (adjustment_value > 0xF)
2719                                 adjustment_value = 0xF;
2720
2721                         adjustment_value_lo = adjustment_value & 0xffff;
2722                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2723
2724                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2725                                               adjustment_value_lo);
2726                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2727                                               adjustment_value_hi);
2728                         seconds += ((s32)adjustment_value);
2729                 }
2730                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2731                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2732         }
2733         if (nano_seconds) {
2734                 u16 nano_seconds_lo;
2735                 u16 nano_seconds_hi;
2736
2737                 nano_seconds_lo = nano_seconds & 0xffff;
2738                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2739
2740                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2741                                       nano_seconds_lo);
2742                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2743                                       PTP_LTC_STEP_ADJ_DIR_ |
2744                                       nano_seconds_hi);
2745                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2746                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2747         }
2748 }
2749
2750 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2751 {
2752         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2753                                                           ptp_clock_info);
2754         struct phy_device *phydev = shared->phydev;
2755
2756         mutex_lock(&shared->shared_lock);
2757         lan8814_ptp_clock_step(phydev, delta);
2758         mutex_unlock(&shared->shared_lock);
2759
2760         return 0;
2761 }
2762
2763 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2764 {
2765         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2766                                                           ptp_clock_info);
2767         struct phy_device *phydev = shared->phydev;
2768         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2769         bool positive = true;
2770         u32 kszphy_rate_adj;
2771
2772         if (scaled_ppm < 0) {
2773                 scaled_ppm = -scaled_ppm;
2774                 positive = false;
2775         }
2776
2777         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2778         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2779
2780         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2781         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2782
2783         if (positive)
2784                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2785
2786         mutex_lock(&shared->shared_lock);
2787         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2788         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2789         mutex_unlock(&shared->shared_lock);
2790
2791         return 0;
2792 }
2793
2794 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2795 {
2796         struct ptp_header *ptp_header;
2797         u32 type;
2798
2799         type = ptp_classify_raw(skb);
2800         ptp_header = ptp_parse_header(skb, type);
2801
2802         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2803 }
2804
2805 static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2806                                  u32 seconds, u32 nsec, u16 seq_id)
2807 {
2808         struct skb_shared_hwtstamps shhwtstamps;
2809         struct sk_buff *skb, *skb_tmp;
2810         unsigned long flags;
2811         bool ret = false;
2812         u16 skb_sig;
2813
2814         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2815         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2816                 lan8814_get_sig_tx(skb, &skb_sig);
2817
2818                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2819                         continue;
2820
2821                 __skb_unlink(skb, &ptp_priv->tx_queue);
2822                 ret = true;
2823                 break;
2824         }
2825         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2826
2827         if (ret) {
2828                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2829                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2830                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2831         }
2832 }
2833
2834 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2835 {
2836         struct phy_device *phydev = ptp_priv->phydev;
2837         u32 seconds, nsec;
2838         u16 seq_id;
2839
2840         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2841         lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2842 }
2843
2844 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2845 {
2846         struct phy_device *phydev = ptp_priv->phydev;
2847         u32 reg;
2848
2849         do {
2850                 lan8814_dequeue_tx_skb(ptp_priv);
2851
2852                 /* If other timestamps are available in the FIFO,
2853                  * process them.
2854                  */
2855                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2856         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2857 }
2858
2859 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2860                               struct lan8814_ptp_rx_ts *rx_ts)
2861 {
2862         struct skb_shared_hwtstamps *shhwtstamps;
2863         struct sk_buff *skb, *skb_tmp;
2864         unsigned long flags;
2865         bool ret = false;
2866         u16 skb_sig;
2867
2868         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2869         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2870                 lan8814_get_sig_rx(skb, &skb_sig);
2871
2872                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2873                         continue;
2874
2875                 __skb_unlink(skb, &ptp_priv->rx_queue);
2876
2877                 ret = true;
2878                 break;
2879         }
2880         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2881
2882         if (ret) {
2883                 shhwtstamps = skb_hwtstamps(skb);
2884                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2885                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2886                 netif_rx(skb);
2887         }
2888
2889         return ret;
2890 }
2891
2892 static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2893                                 struct lan8814_ptp_rx_ts *rx_ts)
2894 {
2895         unsigned long flags;
2896
2897         /* If we failed to match the skb add it to the queue for when
2898          * the frame will come
2899          */
2900         if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2901                 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2902                 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2903                 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2904         } else {
2905                 kfree(rx_ts);
2906         }
2907 }
2908
2909 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2910 {
2911         struct phy_device *phydev = ptp_priv->phydev;
2912         struct lan8814_ptp_rx_ts *rx_ts;
2913         u32 reg;
2914
2915         do {
2916                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2917                 if (!rx_ts)
2918                         return;
2919
2920                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2921                                       &rx_ts->seq_id);
2922                 lan8814_match_rx_ts(ptp_priv, rx_ts);
2923
2924                 /* If other timestamps are available in the FIFO,
2925                  * process them.
2926                  */
2927                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2928         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2929 }
2930
2931 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2932 {
2933         struct kszphy_priv *priv = phydev->priv;
2934         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2935
2936         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2937                 lan8814_get_tx_ts(ptp_priv);
2938
2939         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2940                 lan8814_get_rx_ts(ptp_priv);
2941
2942         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2943                 lan8814_flush_fifo(phydev, true);
2944                 skb_queue_purge(&ptp_priv->tx_queue);
2945         }
2946
2947         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2948                 lan8814_flush_fifo(phydev, false);
2949                 skb_queue_purge(&ptp_priv->rx_queue);
2950         }
2951 }
2952
2953 static int lan8804_config_init(struct phy_device *phydev)
2954 {
2955         int val;
2956
2957         /* MDI-X setting for swap A,B transmit */
2958         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2959         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2960         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2961         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2962
2963         /* Make sure that the PHY will not stop generating the clock when the
2964          * link partner goes down
2965          */
2966         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2967         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2968
2969         return 0;
2970 }
2971
2972 static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
2973 {
2974         int status;
2975
2976         status = phy_read(phydev, LAN8814_INTS);
2977         if (status < 0) {
2978                 phy_error(phydev);
2979                 return IRQ_NONE;
2980         }
2981
2982         if (status > 0)
2983                 phy_trigger_machine(phydev);
2984
2985         return IRQ_HANDLED;
2986 }
2987
2988 #define LAN8804_OUTPUT_CONTROL                  25
2989 #define LAN8804_OUTPUT_CONTROL_INTR_BUFFER      BIT(14)
2990 #define LAN8804_CONTROL                         31
2991 #define LAN8804_CONTROL_INTR_POLARITY           BIT(14)
2992
2993 static int lan8804_config_intr(struct phy_device *phydev)
2994 {
2995         int err;
2996
2997         /* This is an internal PHY of lan966x and is not possible to change the
2998          * polarity on the GIC found in lan966x, therefore change the polarity
2999          * of the interrupt in the PHY from being active low instead of active
3000          * high.
3001          */
3002         phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3003
3004         /* By default interrupt buffer is open-drain in which case the interrupt
3005          * can be active only low. Therefore change the interrupt buffer to be
3006          * push-pull to be able to change interrupt polarity
3007          */
3008         phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3009                   LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3010
3011         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3012                 err = phy_read(phydev, LAN8814_INTS);
3013                 if (err < 0)
3014                         return err;
3015
3016                 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3017                 if (err)
3018                         return err;
3019         } else {
3020                 err = phy_write(phydev, LAN8814_INTC, 0);
3021                 if (err)
3022                         return err;
3023
3024                 err = phy_read(phydev, LAN8814_INTS);
3025                 if (err < 0)
3026                         return err;
3027         }
3028
3029         return 0;
3030 }
3031
3032 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3033 {
3034         int ret = IRQ_NONE;
3035         int irq_status;
3036
3037         irq_status = phy_read(phydev, LAN8814_INTS);
3038         if (irq_status < 0) {
3039                 phy_error(phydev);
3040                 return IRQ_NONE;
3041         }
3042
3043         if (irq_status & LAN8814_INT_LINK) {
3044                 phy_trigger_machine(phydev);
3045                 ret = IRQ_HANDLED;
3046         }
3047
3048         while (true) {
3049                 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3050                 if (!irq_status)
3051                         break;
3052
3053                 lan8814_handle_ptp_interrupt(phydev, irq_status);
3054                 ret = IRQ_HANDLED;
3055         }
3056
3057         return ret;
3058 }
3059
3060 static int lan8814_ack_interrupt(struct phy_device *phydev)
3061 {
3062         /* bit[12..0] int status, which is a read and clear register. */
3063         int rc;
3064
3065         rc = phy_read(phydev, LAN8814_INTS);
3066
3067         return (rc < 0) ? rc : 0;
3068 }
3069
3070 static int lan8814_config_intr(struct phy_device *phydev)
3071 {
3072         int err;
3073
3074         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3075                               LAN8814_INTR_CTRL_REG_POLARITY |
3076                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3077
3078         /* enable / disable interrupts */
3079         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3080                 err = lan8814_ack_interrupt(phydev);
3081                 if (err)
3082                         return err;
3083
3084                 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3085         } else {
3086                 err = phy_write(phydev, LAN8814_INTC, 0);
3087                 if (err)
3088                         return err;
3089
3090                 err = lan8814_ack_interrupt(phydev);
3091         }
3092
3093         return err;
3094 }
3095
3096 static void lan8814_ptp_init(struct phy_device *phydev)
3097 {
3098         struct kszphy_priv *priv = phydev->priv;
3099         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3100         u32 temp;
3101
3102         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3103             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3104                 return;
3105
3106         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3107
3108         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3109         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3110         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3111
3112         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3113         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3114         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3115
3116         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3117         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3118
3119         /* Removing default registers configs related to L2 and IP */
3120         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3121         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3122         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3123         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3124
3125         skb_queue_head_init(&ptp_priv->tx_queue);
3126         skb_queue_head_init(&ptp_priv->rx_queue);
3127         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3128         spin_lock_init(&ptp_priv->rx_ts_lock);
3129
3130         ptp_priv->phydev = phydev;
3131
3132         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3133         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3134         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3135         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
3136
3137         phydev->mii_ts = &ptp_priv->mii_ts;
3138 }
3139
3140 static int lan8814_ptp_probe_once(struct phy_device *phydev)
3141 {
3142         struct lan8814_shared_priv *shared = phydev->shared->priv;
3143
3144         /* Initialise shared lock for clock*/
3145         mutex_init(&shared->shared_lock);
3146
3147         shared->ptp_clock_info.owner = THIS_MODULE;
3148         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3149         shared->ptp_clock_info.max_adj = 31249999;
3150         shared->ptp_clock_info.n_alarm = 0;
3151         shared->ptp_clock_info.n_ext_ts = 0;
3152         shared->ptp_clock_info.n_pins = 0;
3153         shared->ptp_clock_info.pps = 0;
3154         shared->ptp_clock_info.pin_config = NULL;
3155         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3156         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3157         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3158         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3159         shared->ptp_clock_info.getcrosststamp = NULL;
3160
3161         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3162                                                &phydev->mdio.dev);
3163         if (IS_ERR(shared->ptp_clock)) {
3164                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3165                            PTR_ERR(shared->ptp_clock));
3166                 return -EINVAL;
3167         }
3168
3169         /* Check if PHC support is missing at the configuration level */
3170         if (!shared->ptp_clock)
3171                 return 0;
3172
3173         phydev_dbg(phydev, "successfully registered ptp clock\n");
3174
3175         shared->phydev = phydev;
3176
3177         /* The EP.4 is shared between all the PHYs in the package and also it
3178          * can be accessed by any of the PHYs
3179          */
3180         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3181         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3182                               PTP_OPERATING_MODE_STANDALONE_);
3183
3184         return 0;
3185 }
3186
3187 static void lan8814_setup_led(struct phy_device *phydev, int val)
3188 {
3189         int temp;
3190
3191         temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3192
3193         if (val)
3194                 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3195         else
3196                 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3197
3198         lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3199 }
3200
3201 static int lan8814_config_init(struct phy_device *phydev)
3202 {
3203         struct kszphy_priv *lan8814 = phydev->priv;
3204         int val;
3205
3206         /* Reset the PHY */
3207         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3208         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3209         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3210
3211         /* Disable ANEG with QSGMII PCS Host side */
3212         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3213         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3214         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3215
3216         /* MDI-X setting for swap A,B transmit */
3217         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3218         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3219         val |= LAN8814_ALIGN_TX_A_B_SWAP;
3220         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3221
3222         if (lan8814->led_mode >= 0)
3223                 lan8814_setup_led(phydev, lan8814->led_mode);
3224
3225         return 0;
3226 }
3227
3228 /* It is expected that there will not be any 'lan8814_take_coma_mode'
3229  * function called in suspend. Because the GPIO line can be shared, so if one of
3230  * the phys goes back in coma mode, then all the other PHYs will go, which is
3231  * wrong.
3232  */
3233 static int lan8814_release_coma_mode(struct phy_device *phydev)
3234 {
3235         struct gpio_desc *gpiod;
3236
3237         gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3238                                         GPIOD_OUT_HIGH_OPEN_DRAIN |
3239                                         GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3240         if (IS_ERR(gpiod))
3241                 return PTR_ERR(gpiod);
3242
3243         gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3244         gpiod_set_value_cansleep(gpiod, 0);
3245
3246         return 0;
3247 }
3248
3249 static int lan8814_probe(struct phy_device *phydev)
3250 {
3251         const struct kszphy_type *type = phydev->drv->driver_data;
3252         struct kszphy_priv *priv;
3253         u16 addr;
3254         int err;
3255
3256         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3257         if (!priv)
3258                 return -ENOMEM;
3259
3260         phydev->priv = priv;
3261
3262         priv->type = type;
3263
3264         kszphy_parse_led_mode(phydev);
3265
3266         /* Strap-in value for PHY address, below register read gives starting
3267          * phy address value
3268          */
3269         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3270         devm_phy_package_join(&phydev->mdio.dev, phydev,
3271                               addr, sizeof(struct lan8814_shared_priv));
3272
3273         if (phy_package_init_once(phydev)) {
3274                 err = lan8814_release_coma_mode(phydev);
3275                 if (err)
3276                         return err;
3277
3278                 err = lan8814_ptp_probe_once(phydev);
3279                 if (err)
3280                         return err;
3281         }
3282
3283         lan8814_ptp_init(phydev);
3284
3285         return 0;
3286 }
3287
3288 #define LAN8841_MMD_TIMER_REG                   0
3289 #define LAN8841_MMD0_REGISTER_17                17
3290 #define LAN8841_MMD0_REGISTER_17_DROP_OPT(x)    ((x) & 0x3)
3291 #define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS        BIT(3)
3292 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG   2
3293 #define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK   BIT(14)
3294 #define LAN8841_MMD_ANALOG_REG                  28
3295 #define LAN8841_ANALOG_CONTROL_1                1
3296 #define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x)    (((x) & 0x3) << 5)
3297 #define LAN8841_ANALOG_CONTROL_10               13
3298 #define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x)    ((x) & 0x3)
3299 #define LAN8841_ANALOG_CONTROL_11               14
3300 #define LAN8841_ANALOG_CONTROL_11_LDO_REF(x)    (((x) & 0x7) << 12)
3301 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3302 #define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3303 #define LAN8841_BTRX_POWER_DOWN                 70
3304 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A      BIT(0)
3305 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A       BIT(1)
3306 #define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B      BIT(2)
3307 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B       BIT(3)
3308 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C       BIT(5)
3309 #define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D       BIT(7)
3310 #define LAN8841_ADC_CHANNEL_MASK                198
3311 #define LAN8841_PTP_RX_PARSE_L2_ADDR_EN         370
3312 #define LAN8841_PTP_RX_PARSE_IP_ADDR_EN         371
3313 #define LAN8841_PTP_TX_PARSE_L2_ADDR_EN         434
3314 #define LAN8841_PTP_TX_PARSE_IP_ADDR_EN         435
3315 #define LAN8841_PTP_CMD_CTL                     256
3316 #define LAN8841_PTP_CMD_CTL_PTP_ENABLE          BIT(2)
3317 #define LAN8841_PTP_CMD_CTL_PTP_DISABLE         BIT(1)
3318 #define LAN8841_PTP_CMD_CTL_PTP_RESET           BIT(0)
3319 #define LAN8841_PTP_RX_PARSE_CONFIG             368
3320 #define LAN8841_PTP_TX_PARSE_CONFIG             432
3321 #define LAN8841_PTP_RX_MODE                     381
3322 #define LAN8841_PTP_INSERT_TS_EN                BIT(0)
3323 #define LAN8841_PTP_INSERT_TS_32BIT             BIT(1)
3324
3325 static int lan8841_config_init(struct phy_device *phydev)
3326 {
3327         int ret;
3328
3329         ret = ksz9131_config_init(phydev);
3330         if (ret)
3331                 return ret;
3332
3333         /* Initialize the HW by resetting everything */
3334         phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3335                        LAN8841_PTP_CMD_CTL,
3336                        LAN8841_PTP_CMD_CTL_PTP_RESET,
3337                        LAN8841_PTP_CMD_CTL_PTP_RESET);
3338
3339         phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3340                        LAN8841_PTP_CMD_CTL,
3341                        LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3342                        LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3343
3344         /* Don't process any frames */
3345         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3346                       LAN8841_PTP_RX_PARSE_CONFIG, 0);
3347         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3348                       LAN8841_PTP_TX_PARSE_CONFIG, 0);
3349         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3350                       LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3351         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3352                       LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3353         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3354                       LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3355         phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3356                       LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3357
3358         /* 100BT Clause 40 improvenent errata */
3359         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3360                       LAN8841_ANALOG_CONTROL_1,
3361                       LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3362         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3363                       LAN8841_ANALOG_CONTROL_10,
3364                       LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3365
3366         /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3367          * Magnetics
3368          */
3369         ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3370                            LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3371         if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3372                 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3373                               LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3374                               LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3375                 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3376                               LAN8841_BTRX_POWER_DOWN,
3377                               LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3378                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3379                               LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3380                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3381                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3382                               LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3383         }
3384
3385         /* LDO Adjustment errata */
3386         phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3387                       LAN8841_ANALOG_CONTROL_11,
3388                       LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3389
3390         /* 100BT RGMII latency tuning errata */
3391         phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3392                       LAN8841_ADC_CHANNEL_MASK, 0x0);
3393         phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3394                       LAN8841_MMD0_REGISTER_17,
3395                       LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3396                       LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3397
3398         return 0;
3399 }
3400
3401 #define LAN8841_OUTPUT_CTRL                     25
3402 #define LAN8841_OUTPUT_CTRL_INT_BUFFER          BIT(14)
3403 #define LAN8841_INT_PTP                         BIT(9)
3404
3405 static int lan8841_config_intr(struct phy_device *phydev)
3406 {
3407         int err;
3408
3409         phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3410                    LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3411
3412         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3413                 err = phy_read(phydev, LAN8814_INTS);
3414                 if (err)
3415                         return err;
3416
3417                 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3418                  * even if it PTP is not enabled. Because the underneath blocks
3419                  * will not enable the PTP so we will never get the PTP
3420                  * interrupt.
3421                  */
3422                 err = phy_write(phydev, LAN8814_INTC,
3423                                 LAN8814_INT_LINK | LAN8841_INT_PTP);
3424         } else {
3425                 err = phy_write(phydev, LAN8814_INTC, 0);
3426                 if (err)
3427                         return err;
3428
3429                 err = phy_read(phydev, LAN8814_INTS);
3430         }
3431
3432         return err;
3433 }
3434
3435 #define LAN8841_PTP_TX_EGRESS_SEC_LO                    453
3436 #define LAN8841_PTP_TX_EGRESS_SEC_HI                    452
3437 #define LAN8841_PTP_TX_EGRESS_NS_LO                     451
3438 #define LAN8841_PTP_TX_EGRESS_NS_HI                     450
3439 #define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID             BIT(15)
3440 #define LAN8841_PTP_TX_MSG_HEADER2                      455
3441
3442 static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3443                                   u32 *sec, u32 *nsec, u16 *seq)
3444 {
3445         struct phy_device *phydev = ptp_priv->phydev;
3446
3447         *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3448         if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3449                 return false;
3450
3451         *nsec = ((*nsec & 0x3fff) << 16);
3452         *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3453
3454         *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3455         *sec = *sec << 16;
3456         *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3457
3458         *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3459
3460         return true;
3461 }
3462
3463 static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3464 {
3465         u32 sec, nsec;
3466         u16 seq;
3467
3468         while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3469                 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3470 }
3471
3472 #define LAN8841_PTP_INT_STS                     259
3473 #define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3474 #define LAN8841_PTP_INT_STS_PTP_TX_TS_INT       BIT(12)
3475 #define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT    BIT(2)
3476
3477 static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3478 {
3479         struct phy_device *phydev = ptp_priv->phydev;
3480         int i;
3481
3482         for (i = 0; i < FIFO_SIZE; ++i)
3483                 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3484
3485         phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3486 }
3487
3488 #define LAN8841_PTP_GPIO_CAP_STS                        506
3489 #define LAN8841_PTP_GPIO_SEL                            327
3490 #define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio)             ((gpio) << 8)
3491 #define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP              498
3492 #define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP              499
3493 #define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP               500
3494 #define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP               501
3495 #define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP              502
3496 #define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP              503
3497 #define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP               504
3498 #define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP               505
3499
3500 static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3501 {
3502         struct phy_device *phydev = ptp_priv->phydev;
3503         struct ptp_clock_event ptp_event = {0};
3504         int pin, ret, tmp;
3505         s32 sec, nsec;
3506
3507         pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3508         if (pin == -1)
3509                 return;
3510
3511         tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3512         if (tmp < 0)
3513                 return;
3514
3515         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3516                             LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3517         if (ret)
3518                 return;
3519
3520         mutex_lock(&ptp_priv->ptp_lock);
3521         if (tmp & BIT(pin)) {
3522                 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3523                 sec <<= 16;
3524                 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3525
3526                 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3527                 nsec <<= 16;
3528                 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3529         } else {
3530                 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3531                 sec <<= 16;
3532                 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3533
3534                 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3535                 nsec <<= 16;
3536                 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3537         }
3538         mutex_unlock(&ptp_priv->ptp_lock);
3539         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3540         if (ret)
3541                 return;
3542
3543         ptp_event.index = 0;
3544         ptp_event.timestamp = ktime_set(sec, nsec);
3545         ptp_event.type = PTP_CLOCK_EXTTS;
3546         ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3547 }
3548
3549 static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3550 {
3551         struct kszphy_priv *priv = phydev->priv;
3552         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3553         u16 status;
3554
3555         do {
3556                 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3557
3558                 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3559                         lan8841_ptp_process_tx_ts(ptp_priv);
3560
3561                 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3562                         lan8841_gpio_process_cap(ptp_priv);
3563
3564                 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3565                         lan8841_ptp_flush_fifo(ptp_priv);
3566                         skb_queue_purge(&ptp_priv->tx_queue);
3567                 }
3568
3569         } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3570                            LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3571                            LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3572 }
3573
3574 #define LAN8841_INTS_PTP                BIT(9)
3575
3576 static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3577 {
3578         irqreturn_t ret = IRQ_NONE;
3579         int irq_status;
3580
3581         irq_status = phy_read(phydev, LAN8814_INTS);
3582         if (irq_status < 0) {
3583                 phy_error(phydev);
3584                 return IRQ_NONE;
3585         }
3586
3587         if (irq_status & LAN8814_INT_LINK) {
3588                 phy_trigger_machine(phydev);
3589                 ret = IRQ_HANDLED;
3590         }
3591
3592         if (irq_status & LAN8841_INTS_PTP) {
3593                 lan8841_handle_ptp_interrupt(phydev);
3594                 ret = IRQ_HANDLED;
3595         }
3596
3597         return ret;
3598 }
3599
3600 static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3601                            struct ethtool_ts_info *info)
3602 {
3603         struct kszphy_ptp_priv *ptp_priv;
3604
3605         ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3606
3607         info->phc_index = ptp_priv->ptp_clock ?
3608                                 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3609         if (info->phc_index == -1) {
3610                 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
3611                                          SOF_TIMESTAMPING_RX_SOFTWARE |
3612                                          SOF_TIMESTAMPING_SOFTWARE;
3613                 return 0;
3614         }
3615
3616         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3617                                 SOF_TIMESTAMPING_RX_HARDWARE |
3618                                 SOF_TIMESTAMPING_RAW_HARDWARE;
3619
3620         info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3621                          (1 << HWTSTAMP_TX_ON) |
3622                          (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3623
3624         info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3625                            (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3626                            (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3627                            (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3628
3629         return 0;
3630 }
3631
3632 #define LAN8841_PTP_INT_EN                      260
3633 #define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN   BIT(13)
3634 #define LAN8841_PTP_INT_EN_PTP_TX_TS_EN         BIT(12)
3635
3636 static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3637                                           bool enable)
3638 {
3639         struct phy_device *phydev = ptp_priv->phydev;
3640
3641         if (enable) {
3642                 /* Enable interrupts on the TX side */
3643                 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3644                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3645                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3646                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3647                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3648
3649                 /* Enable the modification of the frame on RX side,
3650                  * this will add the ns and 2 bits of sec in the reserved field
3651                  * of the PTP header
3652                  */
3653                 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3654                                LAN8841_PTP_RX_MODE,
3655                                LAN8841_PTP_INSERT_TS_EN |
3656                                LAN8841_PTP_INSERT_TS_32BIT,
3657                                LAN8841_PTP_INSERT_TS_EN |
3658                                LAN8841_PTP_INSERT_TS_32BIT);
3659
3660                 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3661         } else {
3662                 /* Disable interrupts on the TX side */
3663                 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3664                                LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3665                                LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3666
3667                 /* Disable modification of the RX frames */
3668                 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3669                                LAN8841_PTP_RX_MODE,
3670                                LAN8841_PTP_INSERT_TS_EN |
3671                                LAN8841_PTP_INSERT_TS_32BIT, 0);
3672
3673                 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3674         }
3675 }
3676
3677 #define LAN8841_PTP_RX_TIMESTAMP_EN             379
3678 #define LAN8841_PTP_TX_TIMESTAMP_EN             443
3679 #define LAN8841_PTP_TX_MOD                      445
3680
3681 static int lan8841_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
3682 {
3683         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3684         struct phy_device *phydev = ptp_priv->phydev;
3685         struct hwtstamp_config config;
3686         int txcfg = 0, rxcfg = 0;
3687         int pkt_ts_enable;
3688
3689         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3690                 return -EFAULT;
3691
3692         ptp_priv->hwts_tx_type = config.tx_type;
3693         ptp_priv->rx_filter = config.rx_filter;
3694
3695         switch (config.rx_filter) {
3696         case HWTSTAMP_FILTER_NONE:
3697                 ptp_priv->layer = 0;
3698                 ptp_priv->version = 0;
3699                 break;
3700         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3701         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3702         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3703                 ptp_priv->layer = PTP_CLASS_L4;
3704                 ptp_priv->version = PTP_CLASS_V2;
3705                 break;
3706         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3707         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3708         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3709                 ptp_priv->layer = PTP_CLASS_L2;
3710                 ptp_priv->version = PTP_CLASS_V2;
3711                 break;
3712         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3713         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3714         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3715                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3716                 ptp_priv->version = PTP_CLASS_V2;
3717                 break;
3718         default:
3719                 return -ERANGE;
3720         }
3721
3722         /* Setup parsing of the frames and enable the timestamping for ptp
3723          * frames
3724          */
3725         if (ptp_priv->layer & PTP_CLASS_L2) {
3726                 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3727                 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3728         } else if (ptp_priv->layer & PTP_CLASS_L4) {
3729                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3730                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3731         }
3732
3733         phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3734         phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3735
3736         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3737                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3738         phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3739         phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3740
3741         /* Enable / disable of the TX timestamp in the SYNC frames */
3742         phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3743                        PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3744                        ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3745                                 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3746
3747         /* Now enable/disable the timestamping */
3748         lan8841_ptp_enable_processing(ptp_priv,
3749                                       config.rx_filter != HWTSTAMP_FILTER_NONE);
3750
3751         skb_queue_purge(&ptp_priv->tx_queue);
3752
3753         lan8841_ptp_flush_fifo(ptp_priv);
3754
3755         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
3756 }
3757
3758 static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3759                              struct sk_buff *skb, int type)
3760 {
3761         struct kszphy_ptp_priv *ptp_priv =
3762                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3763         struct ptp_header *header = ptp_parse_header(skb, type);
3764         struct skb_shared_hwtstamps *shhwtstamps;
3765         struct timespec64 ts;
3766         unsigned long flags;
3767         u32 ts_header;
3768
3769         if (!header)
3770                 return false;
3771
3772         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3773             type == PTP_CLASS_NONE)
3774                 return false;
3775
3776         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3777                 return false;
3778
3779         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3780         ts.tv_sec = ptp_priv->seconds;
3781         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3782         ts_header = __be32_to_cpu(header->reserved2);
3783
3784         shhwtstamps = skb_hwtstamps(skb);
3785         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3786
3787         /* Check for any wrap arounds for the second part */
3788         if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3789                 ts.tv_sec -= GENMASK(1, 0) + 1;
3790         else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3791                 ts.tv_sec += 1;
3792
3793         shhwtstamps->hwtstamp =
3794                 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3795                           ts_header & GENMASK(29, 0));
3796         header->reserved2 = 0;
3797
3798         netif_rx(skb);
3799
3800         return true;
3801 }
3802
3803 #define LAN8841_EVENT_A         0
3804 #define LAN8841_EVENT_B         1
3805 #define LAN8841_PTP_LTC_TARGET_SEC_HI(event)    ((event) == LAN8841_EVENT_A ? 278 : 288)
3806 #define LAN8841_PTP_LTC_TARGET_SEC_LO(event)    ((event) == LAN8841_EVENT_A ? 279 : 289)
3807 #define LAN8841_PTP_LTC_TARGET_NS_HI(event)     ((event) == LAN8841_EVENT_A ? 280 : 290)
3808 #define LAN8841_PTP_LTC_TARGET_NS_LO(event)     ((event) == LAN8841_EVENT_A ? 281 : 291)
3809
3810 static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3811                                   s64 sec, u32 nsec)
3812 {
3813         struct phy_device *phydev = ptp_priv->phydev;
3814         int ret;
3815
3816         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3817                             upper_16_bits(sec));
3818         if (ret)
3819                 return ret;
3820
3821         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3822                             lower_16_bits(sec));
3823         if (ret)
3824                 return ret;
3825
3826         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3827                             upper_16_bits(nsec));
3828         if (ret)
3829                 return ret;
3830
3831         return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3832                             lower_16_bits(nsec));
3833 }
3834
3835 #define LAN8841_BUFFER_TIME     2
3836
3837 static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3838                                      const struct timespec64 *ts)
3839 {
3840         return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3841                                       ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3842 }
3843
3844 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event)     ((event) == LAN8841_EVENT_A ? 282 : 292)
3845 #define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event)     ((event) == LAN8841_EVENT_A ? 283 : 293)
3846 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event)      ((event) == LAN8841_EVENT_A ? 284 : 294)
3847 #define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event)      ((event) == LAN8841_EVENT_A ? 285 : 295)
3848
3849 static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3850                                   s64 sec, u32 nsec)
3851 {
3852         struct phy_device *phydev = ptp_priv->phydev;
3853         int ret;
3854
3855         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3856                             upper_16_bits(sec));
3857         if (ret)
3858                 return ret;
3859
3860         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3861                             lower_16_bits(sec));
3862         if (ret)
3863                 return ret;
3864
3865         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3866                             upper_16_bits(nsec));
3867         if (ret)
3868                 return ret;
3869
3870         return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3871                              lower_16_bits(nsec));
3872 }
3873
3874 #define LAN8841_PTP_LTC_SET_SEC_HI      262
3875 #define LAN8841_PTP_LTC_SET_SEC_MID     263
3876 #define LAN8841_PTP_LTC_SET_SEC_LO      264
3877 #define LAN8841_PTP_LTC_SET_NS_HI       265
3878 #define LAN8841_PTP_LTC_SET_NS_LO       266
3879 #define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD        BIT(4)
3880
3881 static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
3882                                  const struct timespec64 *ts)
3883 {
3884         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3885                                                         ptp_clock_info);
3886         struct phy_device *phydev = ptp_priv->phydev;
3887         unsigned long flags;
3888         int ret;
3889
3890         /* Set the value to be stored */
3891         mutex_lock(&ptp_priv->ptp_lock);
3892         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
3893         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
3894         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
3895         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
3896         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
3897
3898         /* Set the command to load the LTC */
3899         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3900                       LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
3901         ret = lan8841_ptp_update_target(ptp_priv, ts);
3902         mutex_unlock(&ptp_priv->ptp_lock);
3903
3904         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3905         ptp_priv->seconds = ts->tv_sec;
3906         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3907
3908         return ret;
3909 }
3910
3911 #define LAN8841_PTP_LTC_RD_SEC_HI       358
3912 #define LAN8841_PTP_LTC_RD_SEC_MID      359
3913 #define LAN8841_PTP_LTC_RD_SEC_LO       360
3914 #define LAN8841_PTP_LTC_RD_NS_HI        361
3915 #define LAN8841_PTP_LTC_RD_NS_LO        362
3916 #define LAN8841_PTP_CMD_CTL_PTP_LTC_READ        BIT(3)
3917
3918 static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
3919                                  struct timespec64 *ts)
3920 {
3921         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3922                                                         ptp_clock_info);
3923         struct phy_device *phydev = ptp_priv->phydev;
3924         time64_t s;
3925         s64 ns;
3926
3927         mutex_lock(&ptp_priv->ptp_lock);
3928         /* Issue the command to read the LTC */
3929         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3930                       LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3931
3932         /* Read the LTC */
3933         s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3934         s <<= 16;
3935         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3936         s <<= 16;
3937         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3938
3939         ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
3940         ns <<= 16;
3941         ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
3942         mutex_unlock(&ptp_priv->ptp_lock);
3943
3944         set_normalized_timespec64(ts, s, ns);
3945         return 0;
3946 }
3947
3948 static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
3949                                    struct timespec64 *ts)
3950 {
3951         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3952                                                         ptp_clock_info);
3953         struct phy_device *phydev = ptp_priv->phydev;
3954         time64_t s;
3955
3956         mutex_lock(&ptp_priv->ptp_lock);
3957         /* Issue the command to read the LTC */
3958         phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
3959                       LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
3960
3961         /* Read the LTC */
3962         s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
3963         s <<= 16;
3964         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
3965         s <<= 16;
3966         s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
3967         mutex_unlock(&ptp_priv->ptp_lock);
3968
3969         set_normalized_timespec64(ts, s, 0);
3970 }
3971
3972 #define LAN8841_PTP_LTC_STEP_ADJ_LO                     276
3973 #define LAN8841_PTP_LTC_STEP_ADJ_HI                     275
3974 #define LAN8841_PTP_LTC_STEP_ADJ_DIR                    BIT(15)
3975 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS        BIT(5)
3976 #define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS    BIT(6)
3977
3978 static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
3979 {
3980         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3981                                                         ptp_clock_info);
3982         struct phy_device *phydev = ptp_priv->phydev;
3983         struct timespec64 ts;
3984         bool add = true;
3985         u32 nsec;
3986         s32 sec;
3987         int ret;
3988
3989         /* The HW allows up to 15 sec to adjust the time, but here we limit to
3990          * 10 sec the adjustment. The reason is, in case the adjustment is 14
3991          * sec and 999999999 nsec, then we add 8ns to compansate the actual
3992          * increment so the value can be bigger than 15 sec. Therefore limit the
3993          * possible adjustments so we will not have these corner cases
3994          */
3995         if (delta > 10000000000LL || delta < -10000000000LL) {
3996                 /* The timeadjustment is too big, so fall back using set time */
3997                 u64 now;
3998
3999                 ptp->gettime64(ptp, &ts);
4000
4001                 now = ktime_to_ns(timespec64_to_ktime(ts));
4002                 ts = ns_to_timespec64(now + delta);
4003
4004                 ptp->settime64(ptp, &ts);
4005                 return 0;
4006         }
4007
4008         sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4009         if (delta < 0 && nsec != 0) {
4010                 /* It is not allowed to adjust low the nsec part, therefore
4011                  * subtract more from second part and add to nanosecond such
4012                  * that would roll over, so the second part will increase
4013                  */
4014                 sec--;
4015                 nsec = NSEC_PER_SEC - nsec;
4016         }
4017
4018         /* Calculate the adjustments and the direction */
4019         if (delta < 0)
4020                 add = false;
4021
4022         if (nsec > 0)
4023                 /* add 8 ns to cover the likely normal increment */
4024                 nsec += 8;
4025
4026         if (nsec >= NSEC_PER_SEC) {
4027                 /* carry into seconds */
4028                 sec++;
4029                 nsec -= NSEC_PER_SEC;
4030         }
4031
4032         mutex_lock(&ptp_priv->ptp_lock);
4033         if (sec) {
4034                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4035                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4036                               add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4037                 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4038                               LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4039         }
4040
4041         if (nsec) {
4042                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4043                               nsec & 0xffff);
4044                 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4045                               (nsec >> 16) & 0x3fff);
4046                 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4047                               LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4048         }
4049         mutex_unlock(&ptp_priv->ptp_lock);
4050
4051         /* Update the target clock */
4052         ptp->gettime64(ptp, &ts);
4053         mutex_lock(&ptp_priv->ptp_lock);
4054         ret = lan8841_ptp_update_target(ptp_priv, &ts);
4055         mutex_unlock(&ptp_priv->ptp_lock);
4056
4057         return ret;
4058 }
4059
4060 #define LAN8841_PTP_LTC_RATE_ADJ_HI             269
4061 #define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR         BIT(15)
4062 #define LAN8841_PTP_LTC_RATE_ADJ_LO             270
4063
4064 static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4065 {
4066         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4067                                                         ptp_clock_info);
4068         struct phy_device *phydev = ptp_priv->phydev;
4069         bool faster = true;
4070         u32 rate;
4071
4072         if (!scaled_ppm)
4073                 return 0;
4074
4075         if (scaled_ppm < 0) {
4076                 scaled_ppm = -scaled_ppm;
4077                 faster = false;
4078         }
4079
4080         rate = LAN8814_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4081         rate += (LAN8814_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4082
4083         mutex_lock(&ptp_priv->ptp_lock);
4084         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4085                       faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4086                              : upper_16_bits(rate) & 0x3fff);
4087         phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4088         mutex_unlock(&ptp_priv->ptp_lock);
4089
4090         return 0;
4091 }
4092
4093 static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4094                               enum ptp_pin_function func, unsigned int chan)
4095 {
4096         switch (func) {
4097         case PTP_PF_NONE:
4098         case PTP_PF_PEROUT:
4099         case PTP_PF_EXTTS:
4100                 break;
4101         default:
4102                 return -1;
4103         }
4104
4105         return 0;
4106 }
4107
4108 #define LAN8841_PTP_GPIO_NUM    10
4109 #define LAN8841_GPIO_EN         128
4110 #define LAN8841_GPIO_DIR        129
4111 #define LAN8841_GPIO_BUF        130
4112
4113 static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4114 {
4115         struct phy_device *phydev = ptp_priv->phydev;
4116         int ret;
4117
4118         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4119         if (ret)
4120                 return ret;
4121
4122         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4123         if (ret)
4124                 return ret;
4125
4126         return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4127 }
4128
4129 static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4130 {
4131         struct phy_device *phydev = ptp_priv->phydev;
4132         int ret;
4133
4134         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4135         if (ret)
4136                 return ret;
4137
4138         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4139         if (ret)
4140                 return ret;
4141
4142         return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4143 }
4144
4145 #define LAN8841_GPIO_DATA_SEL1                          131
4146 #define LAN8841_GPIO_DATA_SEL2                          132
4147 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK  GENMASK(2, 0)
4148 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A     1
4149 #define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B     2
4150 #define LAN8841_PTP_GENERAL_CONFIG                      257
4151 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A      BIT(1)
4152 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B      BIT(3)
4153 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK     GENMASK(7, 4)
4154 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK     GENMASK(11, 8)
4155 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A          4
4156 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B          7
4157
4158 static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4159                                     u8 event)
4160 {
4161         struct phy_device *phydev = ptp_priv->phydev;
4162         u16 tmp;
4163         int ret;
4164
4165         /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4166          * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4167          * depending on the pin, it requires to read a different register
4168          */
4169         if (pin < 5) {
4170                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4171                 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4172         } else {
4173                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4174                 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4175         }
4176         if (ret)
4177                 return ret;
4178
4179         /* Disable the event */
4180         if (event == LAN8841_EVENT_A)
4181                 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4182                       LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4183         else
4184                 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4185                       LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4186         return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4187 }
4188
4189 static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4190                                     u8 event, int pulse_width)
4191 {
4192         struct phy_device *phydev = ptp_priv->phydev;
4193         u16 tmp;
4194         int ret;
4195
4196         /* Enable the event */
4197         if (event == LAN8841_EVENT_A)
4198                 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4199                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4200                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4201                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4202                                      pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4203         else
4204                 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4205                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4206                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4207                                      LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4208                                      pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4209         if (ret)
4210                 return ret;
4211
4212         /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4213          * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4214          * depending on the pin, it requires to read a different register
4215          */
4216         if (event == LAN8841_EVENT_A)
4217                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4218         else
4219                 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4220
4221         if (pin < 5)
4222                 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4223                                        tmp << (3 * pin));
4224         else
4225                 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4226                                        tmp << (3 * (pin - 5)));
4227
4228         return ret;
4229 }
4230
4231 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS      13
4232 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS      12
4233 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS       11
4234 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS       10
4235 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS        9
4236 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS        8
4237 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US      7
4238 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US      6
4239 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US       5
4240 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US       4
4241 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US        3
4242 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US        2
4243 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS      1
4244 #define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS      0
4245
4246 static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4247                               struct ptp_clock_request *rq, int on)
4248 {
4249         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4250                                                         ptp_clock_info);
4251         struct phy_device *phydev = ptp_priv->phydev;
4252         struct timespec64 ts_on, ts_period;
4253         s64 on_nsec, period_nsec;
4254         int pulse_width;
4255         int pin;
4256         int ret;
4257
4258         if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4259                 return -EOPNOTSUPP;
4260
4261         pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4262         if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4263                 return -EINVAL;
4264
4265         if (!on) {
4266                 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4267                 if (ret)
4268                         return ret;
4269
4270                 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4271         }
4272
4273         ts_on.tv_sec = rq->perout.on.sec;
4274         ts_on.tv_nsec = rq->perout.on.nsec;
4275         on_nsec = timespec64_to_ns(&ts_on);
4276
4277         ts_period.tv_sec = rq->perout.period.sec;
4278         ts_period.tv_nsec = rq->perout.period.nsec;
4279         period_nsec = timespec64_to_ns(&ts_period);
4280
4281         if (period_nsec < 200) {
4282                 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4283                                     phydev_name(phydev));
4284                 return -EOPNOTSUPP;
4285         }
4286
4287         if (on_nsec >= period_nsec) {
4288                 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4289                                     phydev_name(phydev));
4290                 return -EINVAL;
4291         }
4292
4293         switch (on_nsec) {
4294         case 200000000:
4295                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4296                 break;
4297         case 100000000:
4298                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4299                 break;
4300         case 50000000:
4301                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4302                 break;
4303         case 10000000:
4304                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4305                 break;
4306         case 5000000:
4307                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4308                 break;
4309         case 1000000:
4310                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4311                 break;
4312         case 500000:
4313                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4314                 break;
4315         case 100000:
4316                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4317                 break;
4318         case 50000:
4319                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4320                 break;
4321         case 10000:
4322                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4323                 break;
4324         case 5000:
4325                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4326                 break;
4327         case 1000:
4328                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4329                 break;
4330         case 500:
4331                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4332                 break;
4333         case 100:
4334                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4335                 break;
4336         default:
4337                 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4338                                     phydev_name(phydev));
4339                 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4340                 break;
4341         }
4342
4343         mutex_lock(&ptp_priv->ptp_lock);
4344         ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4345                                      rq->perout.start.nsec);
4346         mutex_unlock(&ptp_priv->ptp_lock);
4347         if (ret)
4348                 return ret;
4349
4350         ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4351                                      rq->perout.period.nsec);
4352         if (ret)
4353                 return ret;
4354
4355         ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4356                                        pulse_width);
4357         if (ret)
4358                 return ret;
4359
4360         ret = lan8841_ptp_perout_on(ptp_priv, pin);
4361         if (ret)
4362                 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4363
4364         return ret;
4365 }
4366
4367 #define LAN8841_PTP_GPIO_CAP_EN                 496
4368 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio)    (BIT(gpio))
4369 #define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio)    (BIT(gpio) << 8)
4370 #define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN      BIT(2)
4371
4372 static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4373                                 u32 flags)
4374 {
4375         struct phy_device *phydev = ptp_priv->phydev;
4376         u16 tmp = 0;
4377         int ret;
4378
4379         /* Set GPIO to be intput */
4380         ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4381         if (ret)
4382                 return ret;
4383
4384         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4385         if (ret)
4386                 return ret;
4387
4388         /* Enable capture on the edges of the pin */
4389         if (flags & PTP_RISING_EDGE)
4390                 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4391         if (flags & PTP_FALLING_EDGE)
4392                 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4393         ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4394         if (ret)
4395                 return ret;
4396
4397         /* Enable interrupt */
4398         return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4399                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4400                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4401 }
4402
4403 static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4404 {
4405         struct phy_device *phydev = ptp_priv->phydev;
4406         int ret;
4407
4408         /* Set GPIO to be output */
4409         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4410         if (ret)
4411                 return ret;
4412
4413         ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4414         if (ret)
4415                 return ret;
4416
4417         /* Disable capture on both of the edges */
4418         ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4419                              LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4420                              LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4421                              0);
4422         if (ret)
4423                 return ret;
4424
4425         /* Disable interrupt */
4426         return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4427                               LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4428                               0);
4429 }
4430
4431 static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4432                              struct ptp_clock_request *rq, int on)
4433 {
4434         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4435                                                         ptp_clock_info);
4436         int pin;
4437         int ret;
4438
4439         /* Reject requests with unsupported flags */
4440         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4441                                 PTP_EXTTS_EDGES |
4442                                 PTP_STRICT_FLAGS))
4443                 return -EOPNOTSUPP;
4444
4445         pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4446         if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4447                 return -EINVAL;
4448
4449         mutex_lock(&ptp_priv->ptp_lock);
4450         if (on)
4451                 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4452         else
4453                 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4454         mutex_unlock(&ptp_priv->ptp_lock);
4455
4456         return ret;
4457 }
4458
4459 static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4460                               struct ptp_clock_request *rq, int on)
4461 {
4462         switch (rq->type) {
4463         case PTP_CLK_REQ_EXTTS:
4464                 return lan8841_ptp_extts(ptp, rq, on);
4465         case PTP_CLK_REQ_PEROUT:
4466                 return lan8841_ptp_perout(ptp, rq, on);
4467         default:
4468                 return -EOPNOTSUPP;
4469         }
4470
4471         return 0;
4472 }
4473
4474 static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4475 {
4476         struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4477                                                         ptp_clock_info);
4478         struct timespec64 ts;
4479         unsigned long flags;
4480
4481         lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4482
4483         spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4484         ptp_priv->seconds = ts.tv_sec;
4485         spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4486
4487         return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4488 }
4489
4490 static struct ptp_clock_info lan8841_ptp_clock_info = {
4491         .owner          = THIS_MODULE,
4492         .name           = "lan8841 ptp",
4493         .max_adj        = 31249999,
4494         .gettime64      = lan8841_ptp_gettime64,
4495         .settime64      = lan8841_ptp_settime64,
4496         .adjtime        = lan8841_ptp_adjtime,
4497         .adjfine        = lan8841_ptp_adjfine,
4498         .verify         = lan8841_ptp_verify,
4499         .enable         = lan8841_ptp_enable,
4500         .do_aux_work    = lan8841_ptp_do_aux_work,
4501         .n_per_out      = LAN8841_PTP_GPIO_NUM,
4502         .n_ext_ts       = LAN8841_PTP_GPIO_NUM,
4503         .n_pins         = LAN8841_PTP_GPIO_NUM,
4504 };
4505
4506 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4507 #define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4508
4509 static int lan8841_probe(struct phy_device *phydev)
4510 {
4511         struct kszphy_ptp_priv *ptp_priv;
4512         struct kszphy_priv *priv;
4513         int err;
4514
4515         err = kszphy_probe(phydev);
4516         if (err)
4517                 return err;
4518
4519         if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4520                          LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4521             LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4522                 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4523
4524         /* Register the clock */
4525         if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4526                 return 0;
4527
4528         priv = phydev->priv;
4529         ptp_priv = &priv->ptp_priv;
4530
4531         ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4532                                             LAN8841_PTP_GPIO_NUM,
4533                                             sizeof(*ptp_priv->pin_config),
4534                                             GFP_KERNEL);
4535         if (!ptp_priv->pin_config)
4536                 return -ENOMEM;
4537
4538         for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4539                 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4540
4541                 snprintf(p->name, sizeof(p->name), "pin%d", i);
4542                 p->index = i;
4543                 p->func = PTP_PF_NONE;
4544         }
4545
4546         ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4547         ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4548         ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4549                                                  &phydev->mdio.dev);
4550         if (IS_ERR(ptp_priv->ptp_clock)) {
4551                 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4552                            PTR_ERR(ptp_priv->ptp_clock));
4553                 return -EINVAL;
4554         }
4555
4556         if (!ptp_priv->ptp_clock)
4557                 return 0;
4558
4559         /* Initialize the SW */
4560         skb_queue_head_init(&ptp_priv->tx_queue);
4561         ptp_priv->phydev = phydev;
4562         mutex_init(&ptp_priv->ptp_lock);
4563         spin_lock_init(&ptp_priv->seconds_lock);
4564
4565         ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4566         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4567         ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4568         ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4569
4570         phydev->mii_ts = &ptp_priv->mii_ts;
4571
4572         return 0;
4573 }
4574
4575 static int lan8841_suspend(struct phy_device *phydev)
4576 {
4577         struct kszphy_priv *priv = phydev->priv;
4578         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4579
4580         ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4581
4582         return genphy_suspend(phydev);
4583 }
4584
4585 static struct phy_driver ksphy_driver[] = {
4586 {
4587         .phy_id         = PHY_ID_KS8737,
4588         .phy_id_mask    = MICREL_PHY_ID_MASK,
4589         .name           = "Micrel KS8737",
4590         /* PHY_BASIC_FEATURES */
4591         .driver_data    = &ks8737_type,
4592         .probe          = kszphy_probe,
4593         .config_init    = kszphy_config_init,
4594         .config_intr    = kszphy_config_intr,
4595         .handle_interrupt = kszphy_handle_interrupt,
4596         .suspend        = kszphy_suspend,
4597         .resume         = kszphy_resume,
4598 }, {
4599         .phy_id         = PHY_ID_KSZ8021,
4600         .phy_id_mask    = 0x00ffffff,
4601         .name           = "Micrel KSZ8021 or KSZ8031",
4602         /* PHY_BASIC_FEATURES */
4603         .driver_data    = &ksz8021_type,
4604         .probe          = kszphy_probe,
4605         .config_init    = kszphy_config_init,
4606         .config_intr    = kszphy_config_intr,
4607         .handle_interrupt = kszphy_handle_interrupt,
4608         .get_sset_count = kszphy_get_sset_count,
4609         .get_strings    = kszphy_get_strings,
4610         .get_stats      = kszphy_get_stats,
4611         .suspend        = kszphy_suspend,
4612         .resume         = kszphy_resume,
4613 }, {
4614         .phy_id         = PHY_ID_KSZ8031,
4615         .phy_id_mask    = 0x00ffffff,
4616         .name           = "Micrel KSZ8031",
4617         /* PHY_BASIC_FEATURES */
4618         .driver_data    = &ksz8021_type,
4619         .probe          = kszphy_probe,
4620         .config_init    = kszphy_config_init,
4621         .config_intr    = kszphy_config_intr,
4622         .handle_interrupt = kszphy_handle_interrupt,
4623         .get_sset_count = kszphy_get_sset_count,
4624         .get_strings    = kszphy_get_strings,
4625         .get_stats      = kszphy_get_stats,
4626         .suspend        = kszphy_suspend,
4627         .resume         = kszphy_resume,
4628 }, {
4629         .phy_id         = PHY_ID_KSZ8041,
4630         .phy_id_mask    = MICREL_PHY_ID_MASK,
4631         .name           = "Micrel KSZ8041",
4632         /* PHY_BASIC_FEATURES */
4633         .driver_data    = &ksz8041_type,
4634         .probe          = kszphy_probe,
4635         .config_init    = ksz8041_config_init,
4636         .config_aneg    = ksz8041_config_aneg,
4637         .config_intr    = kszphy_config_intr,
4638         .handle_interrupt = kszphy_handle_interrupt,
4639         .get_sset_count = kszphy_get_sset_count,
4640         .get_strings    = kszphy_get_strings,
4641         .get_stats      = kszphy_get_stats,
4642         /* No suspend/resume callbacks because of errata DS80000700A,
4643          * receiver error following software power down.
4644          */
4645 }, {
4646         .phy_id         = PHY_ID_KSZ8041RNLI,
4647         .phy_id_mask    = MICREL_PHY_ID_MASK,
4648         .name           = "Micrel KSZ8041RNLI",
4649         /* PHY_BASIC_FEATURES */
4650         .driver_data    = &ksz8041_type,
4651         .probe          = kszphy_probe,
4652         .config_init    = kszphy_config_init,
4653         .config_intr    = kszphy_config_intr,
4654         .handle_interrupt = kszphy_handle_interrupt,
4655         .get_sset_count = kszphy_get_sset_count,
4656         .get_strings    = kszphy_get_strings,
4657         .get_stats      = kszphy_get_stats,
4658         .suspend        = kszphy_suspend,
4659         .resume         = kszphy_resume,
4660 }, {
4661         .name           = "Micrel KSZ8051",
4662         /* PHY_BASIC_FEATURES */
4663         .driver_data    = &ksz8051_type,
4664         .probe          = kszphy_probe,
4665         .config_init    = kszphy_config_init,
4666         .config_intr    = kszphy_config_intr,
4667         .handle_interrupt = kszphy_handle_interrupt,
4668         .get_sset_count = kszphy_get_sset_count,
4669         .get_strings    = kszphy_get_strings,
4670         .get_stats      = kszphy_get_stats,
4671         .match_phy_device = ksz8051_match_phy_device,
4672         .suspend        = kszphy_suspend,
4673         .resume         = kszphy_resume,
4674 }, {
4675         .phy_id         = PHY_ID_KSZ8001,
4676         .name           = "Micrel KSZ8001 or KS8721",
4677         .phy_id_mask    = 0x00fffffc,
4678         /* PHY_BASIC_FEATURES */
4679         .driver_data    = &ksz8041_type,
4680         .probe          = kszphy_probe,
4681         .config_init    = kszphy_config_init,
4682         .config_intr    = kszphy_config_intr,
4683         .handle_interrupt = kszphy_handle_interrupt,
4684         .get_sset_count = kszphy_get_sset_count,
4685         .get_strings    = kszphy_get_strings,
4686         .get_stats      = kszphy_get_stats,
4687         .suspend        = kszphy_suspend,
4688         .resume         = kszphy_resume,
4689 }, {
4690         .phy_id         = PHY_ID_KSZ8081,
4691         .name           = "Micrel KSZ8081 or KSZ8091",
4692         .phy_id_mask    = MICREL_PHY_ID_MASK,
4693         .flags          = PHY_POLL_CABLE_TEST,
4694         /* PHY_BASIC_FEATURES */
4695         .driver_data    = &ksz8081_type,
4696         .probe          = kszphy_probe,
4697         .config_init    = ksz8081_config_init,
4698         .soft_reset     = genphy_soft_reset,
4699         .config_aneg    = ksz8081_config_aneg,
4700         .read_status    = ksz8081_read_status,
4701         .config_intr    = kszphy_config_intr,
4702         .handle_interrupt = kszphy_handle_interrupt,
4703         .get_sset_count = kszphy_get_sset_count,
4704         .get_strings    = kszphy_get_strings,
4705         .get_stats      = kszphy_get_stats,
4706         .suspend        = kszphy_suspend,
4707         .resume         = kszphy_resume,
4708         .cable_test_start       = ksz886x_cable_test_start,
4709         .cable_test_get_status  = ksz886x_cable_test_get_status,
4710 }, {
4711         .phy_id         = PHY_ID_KSZ8061,
4712         .name           = "Micrel KSZ8061",
4713         .phy_id_mask    = MICREL_PHY_ID_MASK,
4714         /* PHY_BASIC_FEATURES */
4715         .probe          = kszphy_probe,
4716         .config_init    = ksz8061_config_init,
4717         .config_intr    = kszphy_config_intr,
4718         .handle_interrupt = kszphy_handle_interrupt,
4719         .suspend        = kszphy_suspend,
4720         .resume         = kszphy_resume,
4721 }, {
4722         .phy_id         = PHY_ID_KSZ9021,
4723         .phy_id_mask    = 0x000ffffe,
4724         .name           = "Micrel KSZ9021 Gigabit PHY",
4725         /* PHY_GBIT_FEATURES */
4726         .driver_data    = &ksz9021_type,
4727         .probe          = kszphy_probe,
4728         .get_features   = ksz9031_get_features,
4729         .config_init    = ksz9021_config_init,
4730         .config_intr    = kszphy_config_intr,
4731         .handle_interrupt = kszphy_handle_interrupt,
4732         .get_sset_count = kszphy_get_sset_count,
4733         .get_strings    = kszphy_get_strings,
4734         .get_stats      = kszphy_get_stats,
4735         .suspend        = kszphy_suspend,
4736         .resume         = kszphy_resume,
4737         .read_mmd       = genphy_read_mmd_unsupported,
4738         .write_mmd      = genphy_write_mmd_unsupported,
4739 }, {
4740         .phy_id         = PHY_ID_KSZ9031,
4741         .phy_id_mask    = MICREL_PHY_ID_MASK,
4742         .name           = "Micrel KSZ9031 Gigabit PHY",
4743         .flags          = PHY_POLL_CABLE_TEST,
4744         .driver_data    = &ksz9021_type,
4745         .probe          = kszphy_probe,
4746         .get_features   = ksz9031_get_features,
4747         .config_init    = ksz9031_config_init,
4748         .soft_reset     = genphy_soft_reset,
4749         .read_status    = ksz9031_read_status,
4750         .config_intr    = kszphy_config_intr,
4751         .handle_interrupt = kszphy_handle_interrupt,
4752         .get_sset_count = kszphy_get_sset_count,
4753         .get_strings    = kszphy_get_strings,
4754         .get_stats      = kszphy_get_stats,
4755         .suspend        = kszphy_suspend,
4756         .resume         = kszphy_resume,
4757         .cable_test_start       = ksz9x31_cable_test_start,
4758         .cable_test_get_status  = ksz9x31_cable_test_get_status,
4759 }, {
4760         .phy_id         = PHY_ID_LAN8814,
4761         .phy_id_mask    = MICREL_PHY_ID_MASK,
4762         .name           = "Microchip INDY Gigabit Quad PHY",
4763         .flags          = PHY_POLL_CABLE_TEST,
4764         .config_init    = lan8814_config_init,
4765         .driver_data    = &lan8814_type,
4766         .probe          = lan8814_probe,
4767         .soft_reset     = genphy_soft_reset,
4768         .read_status    = ksz9031_read_status,
4769         .get_sset_count = kszphy_get_sset_count,
4770         .get_strings    = kszphy_get_strings,
4771         .get_stats      = kszphy_get_stats,
4772         .suspend        = genphy_suspend,
4773         .resume         = kszphy_resume,
4774         .config_intr    = lan8814_config_intr,
4775         .handle_interrupt = lan8814_handle_interrupt,
4776         .cable_test_start       = lan8814_cable_test_start,
4777         .cable_test_get_status  = ksz886x_cable_test_get_status,
4778 }, {
4779         .phy_id         = PHY_ID_LAN8804,
4780         .phy_id_mask    = MICREL_PHY_ID_MASK,
4781         .name           = "Microchip LAN966X Gigabit PHY",
4782         .config_init    = lan8804_config_init,
4783         .driver_data    = &ksz9021_type,
4784         .probe          = kszphy_probe,
4785         .soft_reset     = genphy_soft_reset,
4786         .read_status    = ksz9031_read_status,
4787         .get_sset_count = kszphy_get_sset_count,
4788         .get_strings    = kszphy_get_strings,
4789         .get_stats      = kszphy_get_stats,
4790         .suspend        = genphy_suspend,
4791         .resume         = kszphy_resume,
4792         .config_intr    = lan8804_config_intr,
4793         .handle_interrupt = lan8804_handle_interrupt,
4794 }, {
4795         .phy_id         = PHY_ID_LAN8841,
4796         .phy_id_mask    = MICREL_PHY_ID_MASK,
4797         .name           = "Microchip LAN8841 Gigabit PHY",
4798         .flags          = PHY_POLL_CABLE_TEST,
4799         .driver_data    = &lan8841_type,
4800         .config_init    = lan8841_config_init,
4801         .probe          = lan8841_probe,
4802         .soft_reset     = genphy_soft_reset,
4803         .config_intr    = lan8841_config_intr,
4804         .handle_interrupt = lan8841_handle_interrupt,
4805         .get_sset_count = kszphy_get_sset_count,
4806         .get_strings    = kszphy_get_strings,
4807         .get_stats      = kszphy_get_stats,
4808         .suspend        = lan8841_suspend,
4809         .resume         = genphy_resume,
4810         .cable_test_start       = lan8814_cable_test_start,
4811         .cable_test_get_status  = ksz886x_cable_test_get_status,
4812 }, {
4813         .phy_id         = PHY_ID_KSZ9131,
4814         .phy_id_mask    = MICREL_PHY_ID_MASK,
4815         .name           = "Microchip KSZ9131 Gigabit PHY",
4816         /* PHY_GBIT_FEATURES */
4817         .flags          = PHY_POLL_CABLE_TEST,
4818         .driver_data    = &ksz9131_type,
4819         .probe          = kszphy_probe,
4820         .config_init    = ksz9131_config_init,
4821         .config_intr    = kszphy_config_intr,
4822         .config_aneg    = ksz9131_config_aneg,
4823         .read_status    = ksz9131_read_status,
4824         .handle_interrupt = kszphy_handle_interrupt,
4825         .get_sset_count = kszphy_get_sset_count,
4826         .get_strings    = kszphy_get_strings,
4827         .get_stats      = kszphy_get_stats,
4828         .suspend        = kszphy_suspend,
4829         .resume         = kszphy_resume,
4830         .cable_test_start       = ksz9x31_cable_test_start,
4831         .cable_test_get_status  = ksz9x31_cable_test_get_status,
4832         .get_features   = ksz9477_get_features,
4833 }, {
4834         .phy_id         = PHY_ID_KSZ8873MLL,
4835         .phy_id_mask    = MICREL_PHY_ID_MASK,
4836         .name           = "Micrel KSZ8873MLL Switch",
4837         /* PHY_BASIC_FEATURES */
4838         .config_init    = kszphy_config_init,
4839         .config_aneg    = ksz8873mll_config_aneg,
4840         .read_status    = ksz8873mll_read_status,
4841         .suspend        = genphy_suspend,
4842         .resume         = genphy_resume,
4843 }, {
4844         .phy_id         = PHY_ID_KSZ886X,
4845         .phy_id_mask    = MICREL_PHY_ID_MASK,
4846         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4847         .driver_data    = &ksz886x_type,
4848         /* PHY_BASIC_FEATURES */
4849         .flags          = PHY_POLL_CABLE_TEST,
4850         .config_init    = kszphy_config_init,
4851         .config_aneg    = ksz886x_config_aneg,
4852         .read_status    = ksz886x_read_status,
4853         .suspend        = genphy_suspend,
4854         .resume         = genphy_resume,
4855         .cable_test_start       = ksz886x_cable_test_start,
4856         .cable_test_get_status  = ksz886x_cable_test_get_status,
4857 }, {
4858         .name           = "Micrel KSZ87XX Switch",
4859         /* PHY_BASIC_FEATURES */
4860         .config_init    = kszphy_config_init,
4861         .match_phy_device = ksz8795_match_phy_device,
4862         .suspend        = genphy_suspend,
4863         .resume         = genphy_resume,
4864 }, {
4865         .phy_id         = PHY_ID_KSZ9477,
4866         .phy_id_mask    = MICREL_PHY_ID_MASK,
4867         .name           = "Microchip KSZ9477",
4868         /* PHY_GBIT_FEATURES */
4869         .config_init    = ksz9477_config_init,
4870         .config_intr    = kszphy_config_intr,
4871         .handle_interrupt = kszphy_handle_interrupt,
4872         .suspend        = genphy_suspend,
4873         .resume         = genphy_resume,
4874         .get_features   = ksz9477_get_features,
4875 } };
4876
4877 module_phy_driver(ksphy_driver);
4878
4879 MODULE_DESCRIPTION("Micrel PHY driver");
4880 MODULE_AUTHOR("David J. Choi");
4881 MODULE_LICENSE("GPL");
4882
4883 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
4884         { PHY_ID_KSZ9021, 0x000ffffe },
4885         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
4886         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
4887         { PHY_ID_KSZ8001, 0x00fffffc },
4888         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
4889         { PHY_ID_KSZ8021, 0x00ffffff },
4890         { PHY_ID_KSZ8031, 0x00ffffff },
4891         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
4892         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
4893         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
4894         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
4895         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
4896         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
4897         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
4898         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
4899         { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
4900         { }
4901 };
4902
4903 MODULE_DEVICE_TABLE(mdio, micrel_tbl);