1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/slab.h>
26 #include <linux/list.h>
27 #include "kfd_device_queue_manager.h"
29 #include "kfd_kernel_queue.h"
30 #include "amdgpu_amdkfd.h"
31 #include "amdgpu_reset.h"
33 static inline struct process_queue_node *get_queue_by_qid(
34 struct process_queue_manager *pqm, unsigned int qid)
36 struct process_queue_node *pqn;
38 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
39 if ((pqn->q && pqn->q->properties.queue_id == qid) ||
40 (pqn->kq && pqn->kq->queue->properties.queue_id == qid))
47 static int assign_queue_slot_by_qid(struct process_queue_manager *pqm,
50 if (qid >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS)
53 if (__test_and_set_bit(qid, pqm->queue_slot_bitmap)) {
54 pr_err("Cannot create new queue because requested qid(%u) is in use\n", qid);
61 static int find_available_queue_slot(struct process_queue_manager *pqm,
66 found = find_first_zero_bit(pqm->queue_slot_bitmap,
67 KFD_MAX_NUM_OF_QUEUES_PER_PROCESS);
69 pr_debug("The new slot id %lu\n", found);
71 if (found >= KFD_MAX_NUM_OF_QUEUES_PER_PROCESS) {
72 pr_info("Cannot open more queues for process with pasid 0x%x\n",
77 set_bit(found, pqm->queue_slot_bitmap);
83 void kfd_process_dequeue_from_device(struct kfd_process_device *pdd)
85 struct kfd_node *dev = pdd->dev;
87 if (pdd->already_dequeued)
90 dev->dqm->ops.process_termination(dev->dqm, &pdd->qpd);
91 if (dev->kfd->shared_resources.enable_mes &&
92 down_read_trylock(&dev->adev->reset_domain->sem)) {
93 amdgpu_mes_flush_shader_debugger(dev->adev,
94 pdd->proc_ctx_gpu_addr);
95 up_read(&dev->adev->reset_domain->sem);
97 pdd->already_dequeued = true;
100 int pqm_set_gws(struct process_queue_manager *pqm, unsigned int qid,
103 struct mqd_update_info minfo = {0};
104 struct kfd_node *dev = NULL;
105 struct process_queue_node *pqn;
106 struct kfd_process_device *pdd;
107 struct kgd_mem *mem = NULL;
110 pqn = get_queue_by_qid(pqm, qid);
112 pr_err("Queue id does not match any known queue\n");
117 dev = pqn->q->device;
121 pdd = kfd_get_process_device_data(dev, pqm->process);
123 pr_err("Process device data doesn't exist\n");
127 /* Only allow one queue per process can have GWS assigned */
128 if (gws && pdd->qpd.num_gws)
131 if (!gws && pdd->qpd.num_gws == 0)
134 if (KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 3) &&
135 KFD_GC_VERSION(dev) != IP_VERSION(9, 4, 4) &&
136 !dev->kfd->shared_resources.enable_mes) {
138 ret = amdgpu_amdkfd_add_gws_to_process(pdd->process->kgd_process_info,
141 ret = amdgpu_amdkfd_remove_gws_from_process(pdd->process->kgd_process_info,
148 * Intentionally set GWS to a non-NULL value
149 * for devices that do not use GWS for global wave
150 * synchronization but require the formality
151 * of setting GWS for cooperative groups.
153 pqn->q->gws = gws ? ERR_PTR(-ENOMEM) : NULL;
156 pdd->qpd.num_gws = gws ? dev->adev->gds.gws_size : 0;
157 minfo.update_flag = gws ? UPDATE_FLAG_IS_GWS : 0;
159 return pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
163 void kfd_process_dequeue_from_all_devices(struct kfd_process *p)
167 for (i = 0; i < p->n_pdds; i++)
168 kfd_process_dequeue_from_device(p->pdds[i]);
171 int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p)
173 INIT_LIST_HEAD(&pqm->queues);
174 pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS,
176 if (!pqm->queue_slot_bitmap)
183 static void pqm_clean_queue_resource(struct process_queue_manager *pqm,
184 struct process_queue_node *pqn)
186 struct kfd_node *dev;
187 struct kfd_process_device *pdd;
189 dev = pqn->q->device;
191 pdd = kfd_get_process_device_data(dev, pqm->process);
193 pr_err("Process device data doesn't exist\n");
198 if (KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 3) &&
199 KFD_GC_VERSION(pqn->q->device) != IP_VERSION(9, 4, 4) &&
200 !dev->kfd->shared_resources.enable_mes)
201 amdgpu_amdkfd_remove_gws_from_process(
202 pqm->process->kgd_process_info, pqn->q->gws);
203 pdd->qpd.num_gws = 0;
206 if (dev->kfd->shared_resources.enable_mes) {
207 amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->gang_ctx_bo);
209 amdgpu_amdkfd_free_gtt_mem(dev->adev, pqn->q->wptr_bo);
213 void pqm_uninit(struct process_queue_manager *pqm)
215 struct process_queue_node *pqn, *next;
217 list_for_each_entry_safe(pqn, next, &pqm->queues, process_queue_list) {
219 pqm_clean_queue_resource(pqm, pqn);
221 kfd_procfs_del_queue(pqn->q);
222 uninit_queue(pqn->q);
223 list_del(&pqn->process_queue_list);
227 bitmap_free(pqm->queue_slot_bitmap);
228 pqm->queue_slot_bitmap = NULL;
231 static int init_user_queue(struct process_queue_manager *pqm,
232 struct kfd_node *dev, struct queue **q,
233 struct queue_properties *q_properties,
234 struct file *f, struct amdgpu_bo *wptr_bo,
239 /* Doorbell initialized in user space*/
240 q_properties->doorbell_ptr = NULL;
241 q_properties->exception_status = KFD_EC_MASK(EC_QUEUE_NEW);
243 /* let DQM handle it*/
244 q_properties->vmid = 0;
245 q_properties->queue_id = qid;
247 retval = init_queue(q, q_properties);
252 (*q)->process = pqm->process;
254 if (dev->kfd->shared_resources.enable_mes) {
255 retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev,
256 AMDGPU_MES_GANG_CTX_SIZE,
258 &(*q)->gang_ctx_gpu_addr,
259 &(*q)->gang_ctx_cpu_ptr,
262 pr_err("failed to allocate gang context bo\n");
265 memset((*q)->gang_ctx_cpu_ptr, 0, AMDGPU_MES_GANG_CTX_SIZE);
266 (*q)->wptr_bo = wptr_bo;
269 pr_debug("PQM After init queue");
278 int pqm_create_queue(struct process_queue_manager *pqm,
279 struct kfd_node *dev,
281 struct queue_properties *properties,
283 struct amdgpu_bo *wptr_bo,
284 const struct kfd_criu_queue_priv_data *q_data,
285 const void *restore_mqd,
286 const void *restore_ctl_stack,
287 uint32_t *p_doorbell_offset_in_process)
290 struct kfd_process_device *pdd;
292 struct process_queue_node *pqn;
293 struct kernel_queue *kq;
294 enum kfd_queue_type type = properties->type;
295 unsigned int max_queues = 127; /* HWS limit */
298 * On GFX 9.4.3, increase the number of queues that
299 * can be created to 255. No HWS limit on GFX 9.4.3.
301 if (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3) ||
302 KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4))
308 pdd = kfd_get_process_device_data(dev, pqm->process);
310 pr_err("Process device data doesn't exist\n");
315 * for debug process, verify that it is within the static queues limit
316 * currently limit is set to half of the total avail HQD slots
317 * If we are just about to create DIQ, the is_debug flag is not set yet
318 * Hence we also check the type as well
320 if ((pdd->qpd.is_debug) || (type == KFD_QUEUE_TYPE_DIQ))
321 max_queues = dev->kfd->device_info.max_no_of_hqd/2;
323 if (pdd->qpd.queue_count >= max_queues)
327 retval = assign_queue_slot_by_qid(pqm, q_data->q_id);
330 retval = find_available_queue_slot(pqm, qid);
335 if (list_empty(&pdd->qpd.queues_list) &&
336 list_empty(&pdd->qpd.priv_queue_list))
337 dev->dqm->ops.register_process(dev->dqm, &pdd->qpd);
339 pqn = kzalloc(sizeof(*pqn), GFP_KERNEL);
342 goto err_allocate_pqn;
346 case KFD_QUEUE_TYPE_SDMA:
347 case KFD_QUEUE_TYPE_SDMA_XGMI:
348 /* SDMA queues are always allocated statically no matter
349 * which scheduler mode is used. We also do not need to
350 * check whether a SDMA queue can be allocated here, because
351 * allocate_sdma_queue() in create_queue() has the
352 * corresponding check logic.
354 retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid);
356 goto err_create_queue;
359 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
360 restore_mqd, restore_ctl_stack);
364 case KFD_QUEUE_TYPE_COMPUTE:
365 /* check if there is over subscription */
366 if ((dev->dqm->sched_policy ==
367 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION) &&
368 ((dev->dqm->processes_count >= dev->vm_info.vmid_num_kfd) ||
369 (dev->dqm->active_queue_count >= get_cp_queues_num(dev->dqm)))) {
370 pr_debug("Over-subscription is not allowed when amdkfd.sched_policy == 1\n");
372 goto err_create_queue;
375 retval = init_user_queue(pqm, dev, &q, properties, f, wptr_bo, *qid);
377 goto err_create_queue;
380 retval = dev->dqm->ops.create_queue(dev->dqm, q, &pdd->qpd, q_data,
381 restore_mqd, restore_ctl_stack);
384 case KFD_QUEUE_TYPE_DIQ:
385 kq = kernel_queue_init(dev, KFD_QUEUE_TYPE_DIQ);
388 goto err_create_queue;
390 kq->queue->properties.queue_id = *qid;
393 retval = kfd_process_drain_interrupts(pdd);
397 retval = dev->dqm->ops.create_kernel_queue(dev->dqm,
401 WARN(1, "Invalid queue type %d", type);
406 pr_err("Pasid 0x%x DQM create queue type %d failed. ret %d\n",
407 pqm->process->pasid, type, retval);
408 goto err_create_queue;
411 if (q && p_doorbell_offset_in_process) {
412 /* Return the doorbell offset within the doorbell page
413 * to the caller so it can be passed up to user mode
415 * relative doorbell index = Absolute doorbell index -
416 * absolute index of first doorbell in the page.
418 uint32_t first_db_index = amdgpu_doorbell_index_on_bar(pdd->dev->adev,
419 pdd->qpd.proc_doorbells,
421 pdd->dev->kfd->device_info.doorbell_size);
423 *p_doorbell_offset_in_process = (q->properties.doorbell_off
424 - first_db_index) * sizeof(uint32_t);
427 pr_debug("PQM After DQM create queue\n");
429 list_add(&pqn->process_queue_list, &pqm->queues);
432 pr_debug("PQM done creating queue\n");
433 kfd_procfs_add_queue(q);
434 print_queue_properties(&q->properties);
442 kernel_queue_uninit(kq);
445 /* check if queues list is empty unregister process from device */
446 clear_bit(*qid, pqm->queue_slot_bitmap);
447 if (list_empty(&pdd->qpd.queues_list) &&
448 list_empty(&pdd->qpd.priv_queue_list))
449 dev->dqm->ops.unregister_process(dev->dqm, &pdd->qpd);
453 int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid)
455 struct process_queue_node *pqn;
456 struct kfd_process_device *pdd;
457 struct device_queue_manager *dqm;
458 struct kfd_node *dev;
465 pqn = get_queue_by_qid(pqm, qid);
467 pr_err("Queue id does not match any known queue\n");
475 dev = pqn->q->device;
479 pdd = kfd_get_process_device_data(dev, pqm->process);
481 pr_err("Process device data doesn't exist\n");
486 /* destroy kernel queue (DIQ) */
487 dqm = pqn->kq->dev->dqm;
488 dqm->ops.destroy_kernel_queue(dqm, pqn->kq, &pdd->qpd);
489 kernel_queue_uninit(pqn->kq);
493 kfd_procfs_del_queue(pqn->q);
494 dqm = pqn->q->device->dqm;
495 retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q);
497 pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n",
499 pqn->q->properties.queue_id, retval);
500 if (retval != -ETIME)
501 goto err_destroy_queue;
504 pqm_clean_queue_resource(pqm, pqn);
505 uninit_queue(pqn->q);
508 list_del(&pqn->process_queue_list);
510 clear_bit(qid, pqm->queue_slot_bitmap);
512 if (list_empty(&pdd->qpd.queues_list) &&
513 list_empty(&pdd->qpd.priv_queue_list))
514 dqm->ops.unregister_process(dqm, &pdd->qpd);
520 int pqm_update_queue_properties(struct process_queue_manager *pqm,
521 unsigned int qid, struct queue_properties *p)
524 struct process_queue_node *pqn;
526 pqn = get_queue_by_qid(pqm, qid);
528 pr_debug("No queue %d exists for update operation\n", qid);
532 pqn->q->properties.queue_address = p->queue_address;
533 pqn->q->properties.queue_size = p->queue_size;
534 pqn->q->properties.queue_percent = p->queue_percent;
535 pqn->q->properties.priority = p->priority;
536 pqn->q->properties.pm4_target_xcc = p->pm4_target_xcc;
538 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
546 int pqm_update_mqd(struct process_queue_manager *pqm,
547 unsigned int qid, struct mqd_update_info *minfo)
550 struct process_queue_node *pqn;
552 pqn = get_queue_by_qid(pqm, qid);
554 pr_debug("No queue %d exists for update operation\n", qid);
558 /* CUs are masked for debugger requirements so deny user mask */
559 if (pqn->q->properties.is_dbg_wa && minfo && minfo->cu_mask.ptr)
562 /* ASICs that have WGPs must enforce pairwise enabled mask checks. */
563 if (minfo && minfo->cu_mask.ptr &&
564 KFD_GC_VERSION(pqn->q->device) >= IP_VERSION(10, 0, 0)) {
567 for (i = 0; i < minfo->cu_mask.count; i += 2) {
568 uint32_t cu_pair = (minfo->cu_mask.ptr[i / 32] >> (i % 32)) & 0x3;
570 if (cu_pair && cu_pair != 0x3) {
571 pr_debug("CUs must be adjacent pairwise enabled.\n");
577 retval = pqn->q->device->dqm->ops.update_queue(pqn->q->device->dqm,
582 if (minfo && minfo->cu_mask.ptr)
583 pqn->q->properties.is_user_cu_masked = true;
588 struct kernel_queue *pqm_get_kernel_queue(
589 struct process_queue_manager *pqm,
592 struct process_queue_node *pqn;
594 pqn = get_queue_by_qid(pqm, qid);
601 struct queue *pqm_get_user_queue(struct process_queue_manager *pqm,
604 struct process_queue_node *pqn;
606 pqn = get_queue_by_qid(pqm, qid);
607 return pqn ? pqn->q : NULL;
610 int pqm_get_wave_state(struct process_queue_manager *pqm,
612 void __user *ctl_stack,
613 u32 *ctl_stack_used_size,
614 u32 *save_area_used_size)
616 struct process_queue_node *pqn;
618 pqn = get_queue_by_qid(pqm, qid);
620 pr_debug("amdkfd: No queue %d exists for operation\n",
625 return pqn->q->device->dqm->ops.get_wave_state(pqn->q->device->dqm,
629 save_area_used_size);
632 int pqm_get_queue_snapshot(struct process_queue_manager *pqm,
633 uint64_t exception_clear_mask,
635 int *num_qss_entries,
636 uint32_t *entry_size)
638 struct process_queue_node *pqn;
639 struct kfd_queue_snapshot_entry src;
640 uint32_t tmp_entry_size = *entry_size, tmp_qss_entries = *num_qss_entries;
643 *num_qss_entries = 0;
647 *entry_size = min_t(size_t, *entry_size, sizeof(struct kfd_queue_snapshot_entry));
648 mutex_lock(&pqm->process->event_mutex);
650 memset(&src, 0, sizeof(src));
652 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
656 if (*num_qss_entries < tmp_qss_entries) {
657 set_queue_snapshot_entry(pqn->q, exception_clear_mask, &src);
659 if (copy_to_user(buf, &src, *entry_size)) {
663 buf += tmp_entry_size;
665 *num_qss_entries += 1;
668 mutex_unlock(&pqm->process->event_mutex);
672 static int get_queue_data_sizes(struct kfd_process_device *pdd,
675 uint32_t *ctl_stack_size)
679 ret = pqm_get_queue_checkpoint_info(&pdd->process->pqm,
680 q->properties.queue_id,
684 pr_err("Failed to get queue dump info (%d)\n", ret);
689 int kfd_process_get_queue_info(struct kfd_process *p,
690 uint32_t *num_queues,
691 uint64_t *priv_data_sizes)
693 uint32_t extra_data_sizes = 0;
700 /* Run over all PDDs of the process */
701 for (i = 0; i < p->n_pdds; i++) {
702 struct kfd_process_device *pdd = p->pdds[i];
704 list_for_each_entry(q, &pdd->qpd.queues_list, list) {
705 if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
706 q->properties.type == KFD_QUEUE_TYPE_SDMA ||
707 q->properties.type == KFD_QUEUE_TYPE_SDMA_XGMI) {
708 uint32_t mqd_size, ctl_stack_size;
710 *num_queues = *num_queues + 1;
712 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
716 extra_data_sizes += mqd_size + ctl_stack_size;
718 pr_err("Unsupported queue type (%d)\n", q->properties.type);
723 *priv_data_sizes = extra_data_sizes +
724 (*num_queues * sizeof(struct kfd_criu_queue_priv_data));
729 static int pqm_checkpoint_mqd(struct process_queue_manager *pqm,
734 struct process_queue_node *pqn;
736 pqn = get_queue_by_qid(pqm, qid);
738 pr_debug("amdkfd: No queue %d exists for operation\n", qid);
742 if (!pqn->q->device->dqm->ops.checkpoint_mqd) {
743 pr_err("amdkfd: queue dumping not supported on this device\n");
747 return pqn->q->device->dqm->ops.checkpoint_mqd(pqn->q->device->dqm,
748 pqn->q, mqd, ctl_stack);
751 static int criu_checkpoint_queue(struct kfd_process_device *pdd,
753 struct kfd_criu_queue_priv_data *q_data)
755 uint8_t *mqd, *ctl_stack;
758 mqd = (void *)(q_data + 1);
759 ctl_stack = mqd + q_data->mqd_size;
761 q_data->gpu_id = pdd->user_gpu_id;
762 q_data->type = q->properties.type;
763 q_data->format = q->properties.format;
764 q_data->q_id = q->properties.queue_id;
765 q_data->q_address = q->properties.queue_address;
766 q_data->q_size = q->properties.queue_size;
767 q_data->priority = q->properties.priority;
768 q_data->q_percent = q->properties.queue_percent;
769 q_data->read_ptr_addr = (uint64_t)q->properties.read_ptr;
770 q_data->write_ptr_addr = (uint64_t)q->properties.write_ptr;
771 q_data->doorbell_id = q->doorbell_id;
773 q_data->sdma_id = q->sdma_id;
775 q_data->eop_ring_buffer_address =
776 q->properties.eop_ring_buffer_address;
778 q_data->eop_ring_buffer_size = q->properties.eop_ring_buffer_size;
780 q_data->ctx_save_restore_area_address =
781 q->properties.ctx_save_restore_area_address;
783 q_data->ctx_save_restore_area_size =
784 q->properties.ctx_save_restore_area_size;
786 q_data->gws = !!q->gws;
788 ret = pqm_checkpoint_mqd(&pdd->process->pqm, q->properties.queue_id, mqd, ctl_stack);
790 pr_err("Failed checkpoint queue_mqd (%d)\n", ret);
794 pr_debug("Dumping Queue: gpu_id:%x queue_id:%u\n", q_data->gpu_id, q_data->q_id);
798 static int criu_checkpoint_queues_device(struct kfd_process_device *pdd,
799 uint8_t __user *user_priv,
800 unsigned int *q_index,
801 uint64_t *queues_priv_data_offset)
803 unsigned int q_private_data_size = 0;
804 uint8_t *q_private_data = NULL; /* Local buffer to store individual queue private data */
808 list_for_each_entry(q, &pdd->qpd.queues_list, list) {
809 struct kfd_criu_queue_priv_data *q_data;
810 uint64_t q_data_size;
812 uint32_t ctl_stack_size;
814 if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE &&
815 q->properties.type != KFD_QUEUE_TYPE_SDMA &&
816 q->properties.type != KFD_QUEUE_TYPE_SDMA_XGMI) {
818 pr_err("Unsupported queue type (%d)\n", q->properties.type);
823 ret = get_queue_data_sizes(pdd, q, &mqd_size, &ctl_stack_size);
827 q_data_size = sizeof(*q_data) + mqd_size + ctl_stack_size;
829 /* Increase local buffer space if needed */
830 if (q_private_data_size < q_data_size) {
831 kfree(q_private_data);
833 q_private_data = kzalloc(q_data_size, GFP_KERNEL);
834 if (!q_private_data) {
838 q_private_data_size = q_data_size;
841 q_data = (struct kfd_criu_queue_priv_data *)q_private_data;
843 /* data stored in this order: priv_data, mqd, ctl_stack */
844 q_data->mqd_size = mqd_size;
845 q_data->ctl_stack_size = ctl_stack_size;
847 ret = criu_checkpoint_queue(pdd, q, q_data);
851 q_data->object_type = KFD_CRIU_OBJECT_TYPE_QUEUE;
853 ret = copy_to_user(user_priv + *queues_priv_data_offset,
854 q_data, q_data_size);
859 *queues_priv_data_offset += q_data_size;
860 *q_index = *q_index + 1;
863 kfree(q_private_data);
868 int kfd_criu_checkpoint_queues(struct kfd_process *p,
869 uint8_t __user *user_priv_data,
870 uint64_t *priv_data_offset)
872 int ret = 0, pdd_index, q_index = 0;
874 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
875 struct kfd_process_device *pdd = p->pdds[pdd_index];
878 * criu_checkpoint_queues_device will copy data to user and update q_index and
879 * queues_priv_data_offset
881 ret = criu_checkpoint_queues_device(pdd, user_priv_data, &q_index,
891 static void set_queue_properties_from_criu(struct queue_properties *qp,
892 struct kfd_criu_queue_priv_data *q_data)
894 qp->is_interop = false;
895 qp->queue_percent = q_data->q_percent;
896 qp->priority = q_data->priority;
897 qp->queue_address = q_data->q_address;
898 qp->queue_size = q_data->q_size;
899 qp->read_ptr = (uint32_t *) q_data->read_ptr_addr;
900 qp->write_ptr = (uint32_t *) q_data->write_ptr_addr;
901 qp->eop_ring_buffer_address = q_data->eop_ring_buffer_address;
902 qp->eop_ring_buffer_size = q_data->eop_ring_buffer_size;
903 qp->ctx_save_restore_area_address = q_data->ctx_save_restore_area_address;
904 qp->ctx_save_restore_area_size = q_data->ctx_save_restore_area_size;
905 qp->ctl_stack_size = q_data->ctl_stack_size;
906 qp->type = q_data->type;
907 qp->format = q_data->format;
910 int kfd_criu_restore_queue(struct kfd_process *p,
911 uint8_t __user *user_priv_ptr,
912 uint64_t *priv_data_offset,
913 uint64_t max_priv_data_size)
915 uint8_t *mqd, *ctl_stack, *q_extra_data = NULL;
916 struct kfd_criu_queue_priv_data *q_data;
917 struct kfd_process_device *pdd;
918 uint64_t q_extra_data_size;
919 struct queue_properties qp;
920 unsigned int queue_id;
923 if (*priv_data_offset + sizeof(*q_data) > max_priv_data_size)
926 q_data = kmalloc(sizeof(*q_data), GFP_KERNEL);
930 ret = copy_from_user(q_data, user_priv_ptr + *priv_data_offset, sizeof(*q_data));
936 *priv_data_offset += sizeof(*q_data);
937 q_extra_data_size = (uint64_t)q_data->ctl_stack_size + q_data->mqd_size;
939 if (*priv_data_offset + q_extra_data_size > max_priv_data_size) {
944 q_extra_data = kmalloc(q_extra_data_size, GFP_KERNEL);
950 ret = copy_from_user(q_extra_data, user_priv_ptr + *priv_data_offset, q_extra_data_size);
956 *priv_data_offset += q_extra_data_size;
958 pdd = kfd_process_device_data_by_id(p, q_data->gpu_id);
960 pr_err("Failed to get pdd\n");
965 /* data stored in this order: mqd, ctl_stack */
967 ctl_stack = mqd + q_data->mqd_size;
969 memset(&qp, 0, sizeof(qp));
970 set_queue_properties_from_criu(&qp, q_data);
972 print_queue_properties(&qp);
974 ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, NULL, q_data, mqd, ctl_stack,
977 pr_err("Failed to create new queue err:%d\n", ret);
982 ret = pqm_set_gws(&p->pqm, q_data->q_id, pdd->dev->gws);
986 pr_err("Failed to restore queue (%d)\n", ret);
988 pr_debug("Queue id %d was restored successfully\n", queue_id);
995 int pqm_get_queue_checkpoint_info(struct process_queue_manager *pqm,
998 uint32_t *ctl_stack_size)
1000 struct process_queue_node *pqn;
1002 pqn = get_queue_by_qid(pqm, qid);
1004 pr_debug("amdkfd: No queue %d exists for operation\n", qid);
1008 if (!pqn->q->device->dqm->ops.get_queue_checkpoint_info) {
1009 pr_err("amdkfd: queue dumping not supported on this device\n");
1013 pqn->q->device->dqm->ops.get_queue_checkpoint_info(pqn->q->device->dqm,
1019 #if defined(CONFIG_DEBUG_FS)
1021 int pqm_debugfs_mqds(struct seq_file *m, void *data)
1023 struct process_queue_manager *pqm = data;
1024 struct process_queue_node *pqn;
1026 enum KFD_MQD_TYPE mqd_type;
1027 struct mqd_manager *mqd_mgr;
1028 int r = 0, xcc, num_xccs = 1;
1032 list_for_each_entry(pqn, &pqm->queues, process_queue_list) {
1035 switch (q->properties.type) {
1036 case KFD_QUEUE_TYPE_SDMA:
1037 case KFD_QUEUE_TYPE_SDMA_XGMI:
1038 seq_printf(m, " SDMA queue on device %x\n",
1040 mqd_type = KFD_MQD_TYPE_SDMA;
1042 case KFD_QUEUE_TYPE_COMPUTE:
1043 seq_printf(m, " Compute queue on device %x\n",
1045 mqd_type = KFD_MQD_TYPE_CP;
1046 num_xccs = NUM_XCC(q->device->xcc_mask);
1050 " Bad user queue type %d on device %x\n",
1051 q->properties.type, q->device->id);
1054 mqd_mgr = q->device->dqm->mqd_mgrs[mqd_type];
1055 size = mqd_mgr->mqd_stride(mqd_mgr,
1057 } else if (pqn->kq) {
1059 mqd_mgr = pqn->kq->mqd_mgr;
1060 switch (q->properties.type) {
1061 case KFD_QUEUE_TYPE_DIQ:
1062 seq_printf(m, " DIQ on device %x\n",
1067 " Bad kernel queue type %d on device %x\n",
1074 " Weird: Queue node with neither kernel nor user queue\n");
1078 for (xcc = 0; xcc < num_xccs; xcc++) {
1079 mqd = q->mqd + size * xcc;
1080 r = mqd_mgr->debugfs_show_mqd(m, mqd);