drivers/gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "intel_guc_ads.h"
  27 #include "intel_guc_submission.h"
  28 #include "i915_drv.h"
  29
  30 static void gen8_guc_raise_irq(struct intel_guc *guc)
  31 {
  32         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  33
  34         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  35 }
  36
  37 static void gen11_guc_raise_irq(struct intel_guc *guc)
  38 {
  39         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  40
  41         I915_WRITE(GEN11_GUC_HOST_INTERRUPT, 0);
  42 }
  43
  44 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  45 {
  46         GEM_BUG_ON(!guc->send_regs.base);
  47         GEM_BUG_ON(!guc->send_regs.count);
  48         GEM_BUG_ON(i >= guc->send_regs.count);
  49
  50         return _MMIO(guc->send_regs.base + 4 * i);
  51 }
  52
  53 void intel_guc_init_send_regs(struct intel_guc *guc)
  54 {
  55         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  56         enum forcewake_domains fw_domains = 0;
  57         unsigned int i;
  58
  59         if (INTEL_GEN(dev_priv) >= 11) {
  60                 guc->send_regs.base =
  61                                 i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
  62                 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
  63         } else {
  64                 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  65                 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
  66                 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
  67         }
  68
  69         for (i = 0; i < guc->send_regs.count; i++) {
  70                 fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
  71                                         guc_send_reg(guc, i),
  72                                         FW_REG_READ | FW_REG_WRITE);
  73         }
  74         guc->send_regs.fw_domains = fw_domains;
  75 }
  76
  77 void intel_guc_init_early(struct intel_guc *guc)
  78 {
  79         struct drm_i915_private *i915 = guc_to_i915(guc);
  80
  81         intel_guc_fw_init_early(guc);
  82         intel_guc_ct_init_early(&guc->ct);
  83         intel_guc_log_init_early(&guc->log);
  84
  85         mutex_init(&guc->send_mutex);
  86         spin_lock_init(&guc->irq_lock);
  87         guc->send = intel_guc_send_nop;
  88         guc->handler = intel_guc_to_host_event_handler_nop;
  89         if (INTEL_GEN(i915) >= 11) {
  90                 guc->notify = gen11_guc_raise_irq;
  91                 guc->interrupts.reset = gen11_reset_guc_interrupts;
  92                 guc->interrupts.enable = gen11_enable_guc_interrupts;
  93                 guc->interrupts.disable = gen11_disable_guc_interrupts;
  94         } else {
  95                 guc->notify = gen8_guc_raise_irq;
  96                 guc->interrupts.reset = gen9_reset_guc_interrupts;
  97                 guc->interrupts.enable = gen9_enable_guc_interrupts;
  98                 guc->interrupts.disable = gen9_disable_guc_interrupts;
  99         }
 100 }
 101
 102 static int guc_init_wq(struct intel_guc *guc)
 103 {
 104         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 105
 106         /*
 107          * GuC log buffer flush work item has to do register access to
 108          * send the ack to GuC and this work item, if not synced before
 109          * suspend, can potentially get executed after the GFX device is
 110          * suspended.
 111          * By marking the WQ as freezable, we don't have to bother about
 112          * flushing of this work item from the suspend hooks, the pending
 113          * work item if any will be either executed before the suspend
 114          * or scheduled later on resume. This way the handling of work
 115          * item can be kept same between system suspend & rpm suspend.
 116          */
 117         guc->log.relay.flush_wq =
 118                 alloc_ordered_workqueue("i915-guc_log",
 119                                         WQ_HIGHPRI | WQ_FREEZABLE);
 120         if (!guc->log.relay.flush_wq) {
 121                 DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
 122                 return -ENOMEM;
 123         }
 124
 125         /*
 126          * Even though both sending GuC action, and adding a new workitem to
 127          * GuC workqueue are serialized (each with its own locking), since
 128          * we're using mutliple engines, it's possible that we're going to
 129          * issue a preempt request with two (or more - each for different
 130          * engine) workitems in GuC queue. In this situation, GuC may submit
 131          * all of them, which will make us very confused.
 132          * Our preemption contexts may even already be complete - before we
 133          * even had the chance to sent the preempt action to GuC!. Rather
 134          * than introducing yet another lock, we can just use ordered workqueue
 135          * to make sure we're always sending a single preemption request with a
 136          * single workitem.
 137          */
 138         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 139             USES_GUC_SUBMISSION(dev_priv)) {
 140                 guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
 141                                                           WQ_HIGHPRI);
 142                 if (!guc->preempt_wq) {
 143                         destroy_workqueue(guc->log.relay.flush_wq);
 144                         DRM_ERROR("Couldn't allocate workqueue for GuC "
 145                                   "preemption\n");
 146                         return -ENOMEM;
 147                 }
 148         }
 149
 150         return 0;
 151 }
 152
 153 static void guc_fini_wq(struct intel_guc *guc)
 154 {
 155         struct workqueue_struct *wq;
 156
 157         wq = fetch_and_zero(&guc->preempt_wq);
 158         if (wq)
 159                 destroy_workqueue(wq);
 160
 161         wq = fetch_and_zero(&guc->log.relay.flush_wq);
 162         if (wq)
 163                 destroy_workqueue(wq);
 164 }
 165
 166 int intel_guc_init_misc(struct intel_guc *guc)
 167 {
 168         struct drm_i915_private *i915 = guc_to_i915(guc);
 169         int ret;
 170
 171         ret = guc_init_wq(guc);
 172         if (ret)
 173                 return ret;
 174
 175         intel_uc_fw_fetch(i915, &guc->fw);
 176
 177         return 0;
 178 }
 179
 180 void intel_guc_fini_misc(struct intel_guc *guc)
 181 {
 182         intel_uc_fw_cleanup_fetch(&guc->fw);
 183         guc_fini_wq(guc);
 184 }
 185
 186 static int guc_shared_data_create(struct intel_guc *guc)
 187 {
 188         struct i915_vma *vma;
 189         void *vaddr;
 190
 191         vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
 192         if (IS_ERR(vma))
 193                 return PTR_ERR(vma);
 194
 195         vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
 196         if (IS_ERR(vaddr)) {
 197                 i915_vma_unpin_and_release(&vma, 0);
 198                 return PTR_ERR(vaddr);
 199         }
 200
 201         guc->shared_data = vma;
 202         guc->shared_data_vaddr = vaddr;
 203
 204         return 0;
 205 }
 206
 207 static void guc_shared_data_destroy(struct intel_guc *guc)
 208 {
 209         i915_vma_unpin_and_release(&guc->shared_data, I915_VMA_RELEASE_MAP);
 210 }
 211
 212 int intel_guc_init(struct intel_guc *guc)
 213 {
 214         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 215         int ret;
 216
 217         ret = intel_uc_fw_init(&guc->fw);
 218         if (ret)
 219                 goto err_fetch;
 220
 221         ret = guc_shared_data_create(guc);
 222         if (ret)
 223                 goto err_fw;
 224         GEM_BUG_ON(!guc->shared_data);
 225
 226         ret = intel_guc_log_create(&guc->log);
 227         if (ret)
 228                 goto err_shared;
 229
 230         ret = intel_guc_ads_create(guc);
 231         if (ret)
 232                 goto err_log;
 233         GEM_BUG_ON(!guc->ads_vma);
 234
 235         ret = intel_guc_ct_init(&guc->ct);
 236         if (ret)
 237                 goto err_ads;
 238
 239         /* We need to notify the guc whenever we change the GGTT */
 240         i915_ggtt_enable_guc(dev_priv);
 241
 242         return 0;
 243
 244 err_ads:
 245         intel_guc_ads_destroy(guc);
 246 err_log:
 247         intel_guc_log_destroy(&guc->log);
 248 err_shared:
 249         guc_shared_data_destroy(guc);
 250 err_fw:
 251         intel_uc_fw_fini(&guc->fw);
 252 err_fetch:
 253         intel_uc_fw_cleanup_fetch(&guc->fw);
 254         return ret;
 255 }
 256
 257 void intel_guc_fini(struct intel_guc *guc)
 258 {
 259         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 260
 261         i915_ggtt_disable_guc(dev_priv);
 262
 263         intel_guc_ct_fini(&guc->ct);
 264
 265         intel_guc_ads_destroy(guc);
 266         intel_guc_log_destroy(&guc->log);
 267         guc_shared_data_destroy(guc);
 268         intel_uc_fw_fini(&guc->fw);
 269         intel_uc_fw_cleanup_fetch(&guc->fw);
 270 }
 271
 272 static u32 guc_ctl_debug_flags(struct intel_guc *guc)
 273 {
 274         u32 level = intel_guc_log_get_level(&guc->log);
 275         u32 flags = 0;
 276
 277         if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 278                 flags |= GUC_LOG_DISABLED;
 279         else
 280                 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
 281                          GUC_LOG_VERBOSITY_SHIFT;
 282
 283         return flags;
 284 }
 285
 286 static u32 guc_ctl_feature_flags(struct intel_guc *guc)
 287 {
 288         u32 flags = 0;
 289
 290         if (!USES_GUC_SUBMISSION(guc_to_i915(guc)))
 291                 flags |= GUC_CTL_DISABLE_SCHEDULER;
 292
 293         return flags;
 294 }
 295
 296 static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
 297 {
 298         u32 flags = 0;
 299
 300         if (USES_GUC_SUBMISSION(guc_to_i915(guc))) {
 301                 u32 ctxnum, base;
 302
 303                 base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
 304                 ctxnum = GUC_MAX_STAGE_DESCRIPTORS / 16;
 305
 306                 base >>= PAGE_SHIFT;
 307                 flags |= (base << GUC_CTL_BASE_ADDR_SHIFT) |
 308                         (ctxnum << GUC_CTL_CTXNUM_IN16_SHIFT);
 309         }
 310         return flags;
 311 }
 312
 313 static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
 314 {
 315         u32 offset = intel_guc_ggtt_offset(guc, guc->log.vma) >> PAGE_SHIFT;
 316         u32 flags;
 317
 318         #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0)
 319         #define UNIT SZ_1M
 320         #define FLAG GUC_LOG_ALLOC_IN_MEGABYTE
 321         #else
 322         #define UNIT SZ_4K
 323         #define FLAG 0
 324         #endif
 325
 326         BUILD_BUG_ON(!CRASH_BUFFER_SIZE);
 327         BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, UNIT));
 328         BUILD_BUG_ON(!DPC_BUFFER_SIZE);
 329         BUILD_BUG_ON(!IS_ALIGNED(DPC_BUFFER_SIZE, UNIT));
 330         BUILD_BUG_ON(!ISR_BUFFER_SIZE);
 331         BUILD_BUG_ON(!IS_ALIGNED(ISR_BUFFER_SIZE, UNIT));
 332
 333         BUILD_BUG_ON((CRASH_BUFFER_SIZE / UNIT - 1) >
 334                         (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
 335         BUILD_BUG_ON((DPC_BUFFER_SIZE / UNIT - 1) >
 336                         (GUC_LOG_DPC_MASK >> GUC_LOG_DPC_SHIFT));
 337         BUILD_BUG_ON((ISR_BUFFER_SIZE / UNIT - 1) >
 338                         (GUC_LOG_ISR_MASK >> GUC_LOG_ISR_SHIFT));
 339
 340         flags = GUC_LOG_VALID |
 341                 GUC_LOG_NOTIFY_ON_HALF_FULL |
 342                 FLAG |
 343                 ((CRASH_BUFFER_SIZE / UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
 344                 ((DPC_BUFFER_SIZE / UNIT - 1) << GUC_LOG_DPC_SHIFT) |
 345                 ((ISR_BUFFER_SIZE / UNIT - 1) << GUC_LOG_ISR_SHIFT) |
 346                 (offset << GUC_LOG_BUF_ADDR_SHIFT);
 347
 348         #undef UNIT
 349         #undef FLAG
 350
 351         return flags;
 352 }
 353
 354 static u32 guc_ctl_ads_flags(struct intel_guc *guc)
 355 {
 356         u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
 357         u32 flags = ads << GUC_ADS_ADDR_SHIFT;
 358
 359         return flags;
 360 }
 361
 362 /*
 363  * Initialise the GuC parameter block before starting the firmware
 364  * transfer. These parameters are read by the firmware on startup
 365  * and cannot be changed thereafter.
 366  */
 367 void intel_guc_init_params(struct intel_guc *guc)
 368 {
 369         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 370         u32 params[GUC_CTL_MAX_DWORDS];
 371         int i;
 372
 373         memset(params, 0, sizeof(params));
 374
 375         params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
 376         params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
 377         params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
 378         params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
 379         params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
 380
 381         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 382                 DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
 383
 384         /*
 385          * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
 386          * they are power context saved so it's ok to release forcewake
 387          * when we are done here and take it again at xfer time.
 388          */
 389         intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_BLITTER);
 390
 391         I915_WRITE(SOFT_SCRATCH(0), 0);
 392
 393         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 394                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 395
 396         intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_BLITTER);
 397 }
 398
 399 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
 400                        u32 *response_buf, u32 response_buf_size)
 401 {
 402         WARN(1, "Unexpected send: action=%#x\n", *action);
 403         return -ENODEV;
 404 }
 405
 406 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
 407 {
 408         WARN(1, "Unexpected event: no suitable handler\n");
 409 }
 410
 411 /*
 412  * This function implements the MMIO based host to GuC interface.
 413  */
 414 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 415                         u32 *response_buf, u32 response_buf_size)
 416 {
 417         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 418         struct intel_uncore *uncore = &dev_priv->uncore;
 419         u32 status;
 420         int i;
 421         int ret;
 422
 423         GEM_BUG_ON(!len);
 424         GEM_BUG_ON(len > guc->send_regs.count);
 425
 426         /* We expect only action code */
 427         GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
 428
 429         /* If CT is available, we expect to use MMIO only during init/fini */
 430         GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 431                    *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 432
 433         mutex_lock(&guc->send_mutex);
 434         intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
 435
 436         for (i = 0; i < len; i++)
 437                 intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]);
 438
 439         intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
 440
 441         intel_guc_notify(guc);
 442
 443         /*
 444          * No GuC command should ever take longer than 10ms.
 445          * Fast commands should still complete in 10us.
 446          */
 447         ret = __intel_wait_for_register_fw(uncore,
 448                                            guc_send_reg(guc, 0),
 449                                            INTEL_GUC_MSG_TYPE_MASK,
 450                                            INTEL_GUC_MSG_TYPE_RESPONSE <<
 451                                            INTEL_GUC_MSG_TYPE_SHIFT,
 452                                            10, 10, &status);
 453         /* If GuC explicitly returned an error, convert it to -EIO */
 454         if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
 455                 ret = -EIO;
 456
 457         if (ret) {
 458                 DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
 459                           action[0], ret, status);
 460                 goto out;
 461         }
 462
 463         if (response_buf) {
 464                 int count = min(response_buf_size, guc->send_regs.count - 1);
 465
 466                 for (i = 0; i < count; i++)
 467                         response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
 468         }
 469
 470         /* Use data from the GuC response as our return value */
 471         ret = INTEL_GUC_MSG_TO_DATA(status);
 472
 473 out:
 474         intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
 475         mutex_unlock(&guc->send_mutex);
 476
 477         return ret;
 478 }
 479
 480 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
 481                                        const u32 *payload, u32 len)
 482 {
 483         u32 msg;
 484
 485         if (unlikely(!len))
 486                 return -EPROTO;
 487
 488         /* Make sure to handle only enabled messages */
 489         msg = payload[0] & guc->msg_enabled_mask;
 490
 491         if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
 492                    INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
 493                 intel_guc_log_handle_flush_event(&guc->log);
 494
 495         return 0;
 496 }
 497
 498 int intel_guc_sample_forcewake(struct intel_guc *guc)
 499 {
 500         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 501         u32 action[2];
 502
 503         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 504         /* WaRsDisableCoarsePowerGating:skl,cnl */
 505         if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 506                 action[1] = 0;
 507         else
 508                 /* bit 0 and 1 are for Render and Media domain separately */
 509                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 510
 511         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 512 }
 513
 514 /**
 515  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 516  * @guc: intel_guc structure
 517  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 518  *
 519  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 520  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 521  * intel_huc_auth().
 522  *
 523  * Return:      non-zero code on error
 524  */
 525 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 526 {
 527         u32 action[] = {
 528                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 529                 rsa_offset
 530         };
 531
 532         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 533 }
 534
 535 /**
 536  * intel_guc_suspend() - notify GuC entering suspend state
 537  * @guc:        the guc
 538  */
 539 int intel_guc_suspend(struct intel_guc *guc)
 540 {
 541         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 542         int ret;
 543         u32 status;
 544         u32 action[] = {
 545                 INTEL_GUC_ACTION_ENTER_S_STATE,
 546                 GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
 547         };
 548
 549         /*
 550          * The ENTER_S_STATE action queues the save/restore operation in GuC FW
 551          * and then returns, so waiting on the H2G is not enough to guarantee
 552          * GuC is done. When all the processing is done, GuC writes
 553          * INTEL_GUC_SLEEP_STATE_SUCCESS to scratch register 14, so we can poll
 554          * on that. Note that GuC does not ensure that the value in the register
 555          * is different from INTEL_GUC_SLEEP_STATE_SUCCESS while the action is
 556          * in progress so we need to take care of that ourselves as well.
 557          */
 558
 559         I915_WRITE(SOFT_SCRATCH(14), INTEL_GUC_SLEEP_STATE_INVALID_MASK);
 560
 561         ret = intel_guc_send(guc, action, ARRAY_SIZE(action));
 562         if (ret)
 563                 return ret;
 564
 565         ret = __intel_wait_for_register(&dev_priv->uncore, SOFT_SCRATCH(14),
 566                                         INTEL_GUC_SLEEP_STATE_INVALID_MASK,
 567                                         0, 0, 10, &status);
 568         if (ret)
 569                 return ret;
 570
 571         if (status != INTEL_GUC_SLEEP_STATE_SUCCESS) {
 572                 DRM_ERROR("GuC failed to change sleep state. "
 573                           "action=0x%x, err=%u\n",
 574                           action[0], status);
 575                 return -EIO;
 576         }
 577
 578         return 0;
 579 }
 580
 581 /**
 582  * intel_guc_reset_engine() - ask GuC to reset an engine
 583  * @guc:        intel_guc structure
 584  * @engine:     engine to be reset
 585  */
 586 int intel_guc_reset_engine(struct intel_guc *guc,
 587                            struct intel_engine_cs *engine)
 588 {
 589         u32 data[7];
 590
 591         GEM_BUG_ON(!guc->execbuf_client);
 592
 593         data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
 594         data[1] = engine->guc_id;
 595         data[2] = 0;
 596         data[3] = 0;
 597         data[4] = 0;
 598         data[5] = guc->execbuf_client->stage_id;
 599         data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 600
 601         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 602 }
 603
 604 /**
 605  * intel_guc_resume() - notify GuC resuming from suspend state
 606  * @guc:        the guc
 607  */
 608 int intel_guc_resume(struct intel_guc *guc)
 609 {
 610         u32 action[] = {
 611                 INTEL_GUC_ACTION_EXIT_S_STATE,
 612                 GUC_POWER_D0,
 613         };
 614
 615         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 616 }
 617
 618 /**
 619  * DOC: GuC Address Space
 620  *
 621  * The layout of GuC address space is shown below:
 622  *
 623  * ::
 624  *
 625  *     +===========> +====================+ <== FFFF_FFFF
 626  *     ^             |      Reserved      |
 627  *     |             +====================+ <== GUC_GGTT_TOP
 628  *     |             |                    |
 629  *     |             |        DRAM        |
 630  *    GuC            |                    |
 631  *  Address    +===> +====================+ <== GuC ggtt_pin_bias
 632  *   Space     ^     |                    |
 633  *     |       |     |                    |
 634  *     |      GuC    |        GuC         |
 635  *     |     WOPCM   |       WOPCM        |
 636  *     |      Size   |                    |
 637  *     |       |     |                    |
 638  *     v       v     |                    |
 639  *     +=======+===> +====================+ <== 0000_0000
 640  *
 641  * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
 642  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
 643  * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
 644  */
 645
 646 /**
 647  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 648  * @guc:        the guc
 649  * @size:       size of area to allocate (both virtual space and memory)
 650  *
 651  * This is a wrapper to create an object for use with the GuC. In order to
 652  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 653  * both some backing storage and a range inside the Global GTT. We must pin
 654  * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
 655  * range is reserved inside GuC.
 656  *
 657  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 658  */
 659 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 660 {
 661         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 662         struct drm_i915_gem_object *obj;
 663         struct i915_vma *vma;
 664         u64 flags;
 665         int ret;
 666
 667         obj = i915_gem_object_create_shmem(dev_priv, size);
 668         if (IS_ERR(obj))
 669                 return ERR_CAST(obj);
 670
 671         vma = i915_vma_instance(obj, &dev_priv->ggtt.vm, NULL);
 672         if (IS_ERR(vma))
 673                 goto err;
 674
 675         flags = PIN_GLOBAL | PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
 676         ret = i915_vma_pin(vma, 0, 0, flags);
 677         if (ret) {
 678                 vma = ERR_PTR(ret);
 679                 goto err;
 680         }
 681
 682         return vma;
 683
 684 err:
 685         i915_gem_object_put(obj);
 686         return vma;
 687 }