drivers/gpu/drm/i915/intel_device_info.h

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #ifndef _INTEL_DEVICE_INFO_H_
  26 #define _INTEL_DEVICE_INFO_H_
  27
  28 #include <uapi/drm/i915_drm.h>
  29
  30 #include "display/intel_display.h"
  31
  32 #include "gt/intel_engine_types.h"
  33 #include "gt/intel_context_types.h"
  34 #include "gt/intel_sseu.h"
  35
  36 struct drm_printer;
  37 struct drm_i915_private;
  38
  39 /* Keep in gen based order, and chronological order within a gen */
  40 enum intel_platform {
  41         INTEL_PLATFORM_UNINITIALIZED = 0,
  42         /* gen2 */
  43         INTEL_I830,
  44         INTEL_I845G,
  45         INTEL_I85X,
  46         INTEL_I865G,
  47         /* gen3 */
  48         INTEL_I915G,
  49         INTEL_I915GM,
  50         INTEL_I945G,
  51         INTEL_I945GM,
  52         INTEL_G33,
  53         INTEL_PINEVIEW,
  54         /* gen4 */
  55         INTEL_I965G,
  56         INTEL_I965GM,
  57         INTEL_G45,
  58         INTEL_GM45,
  59         /* gen5 */
  60         INTEL_IRONLAKE,
  61         /* gen6 */
  62         INTEL_SANDYBRIDGE,
  63         /* gen7 */
  64         INTEL_IVYBRIDGE,
  65         INTEL_VALLEYVIEW,
  66         INTEL_HASWELL,
  67         /* gen8 */
  68         INTEL_BROADWELL,
  69         INTEL_CHERRYVIEW,
  70         /* gen9 */
  71         INTEL_SKYLAKE,
  72         INTEL_BROXTON,
  73         INTEL_KABYLAKE,
  74         INTEL_GEMINILAKE,
  75         INTEL_COFFEELAKE,
  76         /* gen10 */
  77         INTEL_CANNONLAKE,
  78         /* gen11 */
  79         INTEL_ICELAKE,
  80         INTEL_ELKHARTLAKE,
  81         INTEL_MAX_PLATFORMS
  82 };
  83
  84 /*
  85  * Subplatform bits share the same namespace per parent platform. In other words
  86  * it is fine for the same bit to be used on multiple parent platforms.
  87  */
  88
  89 #define INTEL_SUBPLATFORM_BITS (3)
  90
  91 /* HSW/BDW/SKL/KBL/CFL */
  92 #define INTEL_SUBPLATFORM_ULT   (0)
  93 #define INTEL_SUBPLATFORM_ULX   (1)
  94
  95 /* CNL/ICL */
  96 #define INTEL_SUBPLATFORM_PORTF (0)
  97
  98 enum intel_ppgtt_type {
  99         INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
 100         INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
 101         INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
 102 };
 103
 104 #define DEV_INFO_FOR_EACH_FLAG(func) \
 105         func(is_mobile); \
 106         func(is_lp); \
 107         func(require_force_probe); \
 108         /* Keep has_* in alphabetical order */ \
 109         func(has_64bit_reloc); \
 110         func(gpu_reset_clobbers_display); \
 111         func(has_reset_engine); \
 112         func(has_fpga_dbg); \
 113         func(has_guc); \
 114         func(has_l3_dpf); \
 115         func(has_llc); \
 116         func(has_logical_ring_contexts); \
 117         func(has_logical_ring_elsq); \
 118         func(has_logical_ring_preemption); \
 119         func(has_pooled_eu); \
 120         func(has_rc6); \
 121         func(has_rc6p); \
 122         func(has_rps); \
 123         func(has_runtime_pm); \
 124         func(has_snoop); \
 125         func(has_coherent_ggtt); \
 126         func(unfenced_needs_alignment); \
 127         func(hws_needs_physical);
 128
 129 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 130         /* Keep in alphabetical order */ \
 131         func(cursor_needs_physical); \
 132         func(has_csr); \
 133         func(has_ddi); \
 134         func(has_dp_mst); \
 135         func(has_fbc); \
 136         func(has_gmch); \
 137         func(has_hotplug); \
 138         func(has_ipc); \
 139         func(has_overlay); \
 140         func(has_psr); \
 141         func(overlay_needs_physical); \
 142         func(supports_tv);
 143
 144 struct intel_device_info {
 145         u16 gen_mask;
 146
 147         u8 gen;
 148         u8 gt; /* GT number, 0 if undefined */
 149         intel_engine_mask_t engine_mask; /* Engines supported by the HW */
 150
 151         enum intel_platform platform;
 152
 153         enum intel_ppgtt_type ppgtt_type;
 154         unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
 155
 156         unsigned int page_sizes; /* page sizes supported by the HW */
 157
 158         u32 display_mmio_offset;
 159
 160         u8 num_pipes;
 161
 162 #define DEFINE_FLAG(name) u8 name:1
 163         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 164 #undef DEFINE_FLAG
 165
 166         struct {
 167 #define DEFINE_FLAG(name) u8 name:1
 168                 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 169 #undef DEFINE_FLAG
 170         } display;
 171
 172         u16 ddb_size; /* in blocks */
 173
 174         /* Register offsets for the various display pipes and transcoders */
 175         int pipe_offsets[I915_MAX_TRANSCODERS];
 176         int trans_offsets[I915_MAX_TRANSCODERS];
 177         int cursor_offsets[I915_MAX_PIPES];
 178
 179         struct color_luts {
 180                 u32 degamma_lut_size;
 181                 u32 gamma_lut_size;
 182                 u32 degamma_lut_tests;
 183                 u32 gamma_lut_tests;
 184         } color;
 185 };
 186
 187 struct intel_runtime_info {
 188         /*
 189          * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
 190          * into single runtime conditionals, and also to provide groundwork
 191          * for future per platform, or per SKU build optimizations.
 192          *
 193          * Array can be extended when necessary if the corresponding
 194          * BUILD_BUG_ON is hit.
 195          */
 196         u32 platform_mask[2];
 197
 198         u16 device_id;
 199
 200         u8 num_sprites[I915_MAX_PIPES];
 201         u8 num_scalers[I915_MAX_PIPES];
 202
 203         u8 num_engines;
 204
 205         /* Slice/subslice/EU info */
 206         struct sseu_dev_info sseu;
 207
 208         u32 cs_timestamp_frequency_khz;
 209
 210         /* Media engine access to SFC per instance */
 211         u8 vdbox_sfc_access;
 212 };
 213
 214 struct intel_driver_caps {
 215         unsigned int scheduler;
 216         bool has_logical_contexts:1;
 217 };
 218
 219 const char *intel_platform_name(enum intel_platform platform);
 220
 221 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
 222 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
 223 void intel_device_info_dump_flags(const struct intel_device_info *info,
 224                                   struct drm_printer *p);
 225 void intel_device_info_dump_runtime(const struct intel_runtime_info *info,
 226                                     struct drm_printer *p);
 227 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu,
 228                                      struct drm_printer *p);
 229
 230 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
 231
 232 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 233                              struct drm_printer *p);
 234
 235 #endif