drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27
  28 #include <linux/file.h>
  29 #include <linux/pagemap.h>
  30 #include <linux/sync_file.h>
  31 #include <linux/dma-buf.h>
  32
  33 #include <drm/amdgpu_drm.h>
  34 #include <drm/drm_syncobj.h>
  35 #include "amdgpu_cs.h"
  36 #include "amdgpu.h"
  37 #include "amdgpu_trace.h"
  38 #include "amdgpu_gmc.h"
  39 #include "amdgpu_gem.h"
  40 #include "amdgpu_ras.h"
  41
  42 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
  43                                       struct drm_amdgpu_cs_chunk_fence *data,
  44                                       uint32_t *offset)
  45 {
  46         struct drm_gem_object *gobj;
  47         struct amdgpu_bo *bo;
  48         unsigned long size;
  49         int r;
  50
  51         gobj = drm_gem_object_lookup(p->filp, data->handle);
  52         if (gobj == NULL)
  53                 return -EINVAL;
  54
  55         bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
  56         p->uf_entry.priority = 0;
  57         p->uf_entry.tv.bo = &bo->tbo;
  58         /* One for TTM and two for the CS job */
  59         p->uf_entry.tv.num_shared = 3;
  60
  61         drm_gem_object_put(gobj);
  62
  63         size = amdgpu_bo_size(bo);
  64         if (size != PAGE_SIZE || (data->offset + 8) > size) {
  65                 r = -EINVAL;
  66                 goto error_unref;
  67         }
  68
  69         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
  70                 r = -EINVAL;
  71                 goto error_unref;
  72         }
  73
  74         *offset = data->offset;
  75
  76         return 0;
  77
  78 error_unref:
  79         amdgpu_bo_unref(&bo);
  80         return r;
  81 }
  82
  83 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
  84                                       struct drm_amdgpu_bo_list_in *data)
  85 {
  86         int r;
  87         struct drm_amdgpu_bo_list_entry *info = NULL;
  88
  89         r = amdgpu_bo_create_list_entry_array(data, &info);
  90         if (r)
  91                 return r;
  92
  93         r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
  94                                   &p->bo_list);
  95         if (r)
  96                 goto error_free;
  97
  98         kvfree(info);
  99         return 0;
 100
 101 error_free:
 102         kvfree(info);
 103
 104         return r;
 105 }
 106
 107 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
 108 {
 109         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 110         struct amdgpu_vm *vm = &fpriv->vm;
 111         uint64_t *chunk_array_user;
 112         uint64_t *chunk_array;
 113         unsigned size, num_ibs = 0;
 114         uint32_t uf_offset = 0;
 115         int i;
 116         int ret;
 117
 118         if (cs->in.num_chunks == 0)
 119                 return 0;
 120
 121         chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 122         if (!chunk_array)
 123                 return -ENOMEM;
 124
 125         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 126         if (!p->ctx) {
 127                 ret = -EINVAL;
 128                 goto free_chunk;
 129         }
 130
 131         /* skip guilty context job */
 132         if (atomic_read(&p->ctx->guilty) == 1) {
 133                 ret = -ECANCELED;
 134                 goto free_chunk;
 135         }
 136
 137         /* get chunks */
 138         chunk_array_user = u64_to_user_ptr(cs->in.chunks);
 139         if (copy_from_user(chunk_array, chunk_array_user,
 140                            sizeof(uint64_t)*cs->in.num_chunks)) {
 141                 ret = -EFAULT;
 142                 goto free_chunk;
 143         }
 144
 145         p->nchunks = cs->in.num_chunks;
 146         p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 147                             GFP_KERNEL);
 148         if (!p->chunks) {
 149                 ret = -ENOMEM;
 150                 goto free_chunk;
 151         }
 152
 153         for (i = 0; i < p->nchunks; i++) {
 154                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 155                 struct drm_amdgpu_cs_chunk user_chunk;
 156                 uint32_t __user *cdata;
 157
 158                 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
 159                 if (copy_from_user(&user_chunk, chunk_ptr,
 160                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 161                         ret = -EFAULT;
 162                         i--;
 163                         goto free_partial_kdata;
 164                 }
 165                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 166                 p->chunks[i].length_dw = user_chunk.length_dw;
 167
 168                 size = p->chunks[i].length_dw;
 169                 cdata = u64_to_user_ptr(user_chunk.chunk_data);
 170
 171                 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
 172                 if (p->chunks[i].kdata == NULL) {
 173                         ret = -ENOMEM;
 174                         i--;
 175                         goto free_partial_kdata;
 176                 }
 177                 size *= sizeof(uint32_t);
 178                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 179                         ret = -EFAULT;
 180                         goto free_partial_kdata;
 181                 }
 182
 183                 switch (p->chunks[i].chunk_id) {
 184                 case AMDGPU_CHUNK_ID_IB:
 185                         ++num_ibs;
 186                         break;
 187
 188                 case AMDGPU_CHUNK_ID_FENCE:
 189                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 190                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 191                                 ret = -EINVAL;
 192                                 goto free_partial_kdata;
 193                         }
 194
 195                         ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
 196                                                          &uf_offset);
 197                         if (ret)
 198                                 goto free_partial_kdata;
 199
 200                         break;
 201
 202                 case AMDGPU_CHUNK_ID_BO_HANDLES:
 203                         size = sizeof(struct drm_amdgpu_bo_list_in);
 204                         if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
 205                                 ret = -EINVAL;
 206                                 goto free_partial_kdata;
 207                         }
 208
 209                         ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
 210                         if (ret)
 211                                 goto free_partial_kdata;
 212
 213                         break;
 214
 215                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 216                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
 217                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
 218                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
 219                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
 220                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
 221                         break;
 222
 223                 default:
 224                         ret = -EINVAL;
 225                         goto free_partial_kdata;
 226                 }
 227         }
 228
 229         ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
 230         if (ret)
 231                 goto free_all_kdata;
 232
 233         if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
 234                 ret = -ECANCELED;
 235                 goto free_all_kdata;
 236         }
 237
 238         if (p->uf_entry.tv.bo)
 239                 p->job->uf_addr = uf_offset;
 240         kvfree(chunk_array);
 241
 242         /* Use this opportunity to fill in task info for the vm */
 243         amdgpu_vm_set_task_info(vm);
 244
 245         return 0;
 246
 247 free_all_kdata:
 248         i = p->nchunks - 1;
 249 free_partial_kdata:
 250         for (; i >= 0; i--)
 251                 kvfree(p->chunks[i].kdata);
 252         kvfree(p->chunks);
 253         p->chunks = NULL;
 254         p->nchunks = 0;
 255 free_chunk:
 256         kvfree(chunk_array);
 257
 258         return ret;
 259 }
 260
 261 /* Convert microseconds to bytes. */
 262 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
 263 {
 264         if (us <= 0 || !adev->mm_stats.log2_max_MBps)
 265                 return 0;
 266
 267         /* Since accum_us is incremented by a million per second, just
 268          * multiply it by the number of MB/s to get the number of bytes.
 269          */
 270         return us << adev->mm_stats.log2_max_MBps;
 271 }
 272
 273 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
 274 {
 275         if (!adev->mm_stats.log2_max_MBps)
 276                 return 0;
 277
 278         return bytes >> adev->mm_stats.log2_max_MBps;
 279 }
 280
 281 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
 282  * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
 283  * which means it can go over the threshold once. If that happens, the driver
 284  * will be in debt and no other buffer migrations can be done until that debt
 285  * is repaid.
 286  *
 287  * This approach allows moving a buffer of any size (it's important to allow
 288  * that).
 289  *
 290  * The currency is simply time in microseconds and it increases as the clock
 291  * ticks. The accumulated microseconds (us) are converted to bytes and
 292  * returned.
 293  */
 294 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
 295                                               u64 *max_bytes,
 296                                               u64 *max_vis_bytes)
 297 {
 298         s64 time_us, increment_us;
 299         u64 free_vram, total_vram, used_vram;
 300         /* Allow a maximum of 200 accumulated ms. This is basically per-IB
 301          * throttling.
 302          *
 303          * It means that in order to get full max MBps, at least 5 IBs per
 304          * second must be submitted and not more than 200ms apart from each
 305          * other.
 306          */
 307         const s64 us_upper_bound = 200000;
 308
 309         if (!adev->mm_stats.log2_max_MBps) {
 310                 *max_bytes = 0;
 311                 *max_vis_bytes = 0;
 312                 return;
 313         }
 314
 315         total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
 316         used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
 317         free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
 318
 319         spin_lock(&adev->mm_stats.lock);
 320
 321         /* Increase the amount of accumulated us. */
 322         time_us = ktime_to_us(ktime_get());
 323         increment_us = time_us - adev->mm_stats.last_update_us;
 324         adev->mm_stats.last_update_us = time_us;
 325         adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
 326                                       us_upper_bound);
 327
 328         /* This prevents the short period of low performance when the VRAM
 329          * usage is low and the driver is in debt or doesn't have enough
 330          * accumulated us to fill VRAM quickly.
 331          *
 332          * The situation can occur in these cases:
 333          * - a lot of VRAM is freed by userspace
 334          * - the presence of a big buffer causes a lot of evictions
 335          *   (solution: split buffers into smaller ones)
 336          *
 337          * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
 338          * accum_us to a positive number.
 339          */
 340         if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
 341                 s64 min_us;
 342
 343                 /* Be more aggressive on dGPUs. Try to fill a portion of free
 344                  * VRAM now.
 345                  */
 346                 if (!(adev->flags & AMD_IS_APU))
 347                         min_us = bytes_to_us(adev, free_vram / 4);
 348                 else
 349                         min_us = 0; /* Reset accum_us on APUs. */
 350
 351                 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
 352         }
 353
 354         /* This is set to 0 if the driver is in debt to disallow (optional)
 355          * buffer moves.
 356          */
 357         *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
 358
 359         /* Do the same for visible VRAM if half of it is free */
 360         if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
 361                 u64 total_vis_vram = adev->gmc.visible_vram_size;
 362                 u64 used_vis_vram =
 363                   amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
 364
 365                 if (used_vis_vram < total_vis_vram) {
 366                         u64 free_vis_vram = total_vis_vram - used_vis_vram;
 367                         adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
 368                                                           increment_us, us_upper_bound);
 369
 370                         if (free_vis_vram >= total_vis_vram / 2)
 371                                 adev->mm_stats.accum_us_vis =
 372                                         max(bytes_to_us(adev, free_vis_vram / 2),
 373                                             adev->mm_stats.accum_us_vis);
 374                 }
 375
 376                 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
 377         } else {
 378                 *max_vis_bytes = 0;
 379         }
 380
 381         spin_unlock(&adev->mm_stats.lock);
 382 }
 383
 384 /* Report how many bytes have really been moved for the last command
 385  * submission. This can result in a debt that can stop buffer migrations
 386  * temporarily.
 387  */
 388 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
 389                                   u64 num_vis_bytes)
 390 {
 391         spin_lock(&adev->mm_stats.lock);
 392         adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
 393         adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
 394         spin_unlock(&adev->mm_stats.lock);
 395 }
 396
 397 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
 398 {
 399         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 400         struct amdgpu_cs_parser *p = param;
 401         struct ttm_operation_ctx ctx = {
 402                 .interruptible = true,
 403                 .no_wait_gpu = false,
 404                 .resv = bo->tbo.base.resv
 405         };
 406         uint32_t domain;
 407         int r;
 408
 409         if (bo->tbo.pin_count)
 410                 return 0;
 411
 412         /* Don't move this buffer if we have depleted our allowance
 413          * to move it. Don't move anything if the threshold is zero.
 414          */
 415         if (p->bytes_moved < p->bytes_moved_threshold &&
 416             (!bo->tbo.base.dma_buf ||
 417             list_empty(&bo->tbo.base.dma_buf->attachments))) {
 418                 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 419                     (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
 420                         /* And don't move a CPU_ACCESS_REQUIRED BO to limited
 421                          * visible VRAM if we've depleted our allowance to do
 422                          * that.
 423                          */
 424                         if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
 425                                 domain = bo->preferred_domains;
 426                         else
 427                                 domain = bo->allowed_domains;
 428                 } else {
 429                         domain = bo->preferred_domains;
 430                 }
 431         } else {
 432                 domain = bo->allowed_domains;
 433         }
 434
 435 retry:
 436         amdgpu_bo_placement_from_domain(bo, domain);
 437         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 438
 439         p->bytes_moved += ctx.bytes_moved;
 440         if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 441             amdgpu_bo_in_cpu_visible_vram(bo))
 442                 p->bytes_moved_vis += ctx.bytes_moved;
 443
 444         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 445                 domain = bo->allowed_domains;
 446                 goto retry;
 447         }
 448
 449         return r;
 450 }
 451
 452 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
 453                             struct list_head *validated)
 454 {
 455         struct ttm_operation_ctx ctx = { true, false };
 456         struct amdgpu_bo_list_entry *lobj;
 457         int r;
 458
 459         list_for_each_entry(lobj, validated, tv.head) {
 460                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
 461                 struct mm_struct *usermm;
 462
 463                 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
 464                 if (usermm && usermm != current->mm)
 465                         return -EPERM;
 466
 467                 if (amdgpu_ttm_tt_is_userptr(bo->tbo.ttm) &&
 468                     lobj->user_invalidated && lobj->user_pages) {
 469                         amdgpu_bo_placement_from_domain(bo,
 470                                                         AMDGPU_GEM_DOMAIN_CPU);
 471                         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 472                         if (r)
 473                                 return r;
 474
 475                         amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 476                                                      lobj->user_pages);
 477                 }
 478
 479                 r = amdgpu_cs_bo_validate(p, bo);
 480                 if (r)
 481                         return r;
 482
 483                 kvfree(lobj->user_pages);
 484                 lobj->user_pages = NULL;
 485         }
 486         return 0;
 487 }
 488
 489 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
 490                                 union drm_amdgpu_cs *cs)
 491 {
 492         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 493         struct amdgpu_vm *vm = &fpriv->vm;
 494         struct amdgpu_bo_list_entry *e;
 495         struct list_head duplicates;
 496         struct amdgpu_bo *gds;
 497         struct amdgpu_bo *gws;
 498         struct amdgpu_bo *oa;
 499         int r;
 500
 501         INIT_LIST_HEAD(&p->validated);
 502
 503         /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
 504         if (cs->in.bo_list_handle) {
 505                 if (p->bo_list)
 506                         return -EINVAL;
 507
 508                 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
 509                                        &p->bo_list);
 510                 if (r)
 511                         return r;
 512         } else if (!p->bo_list) {
 513                 /* Create a empty bo_list when no handle is provided */
 514                 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
 515                                           &p->bo_list);
 516                 if (r)
 517                         return r;
 518         }
 519
 520         /* One for TTM and one for the CS job */
 521         amdgpu_bo_list_for_each_entry(e, p->bo_list)
 522                 e->tv.num_shared = 2;
 523
 524         amdgpu_bo_list_get_list(p->bo_list, &p->validated);
 525
 526         INIT_LIST_HEAD(&duplicates);
 527         amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
 528
 529         if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
 530                 list_add(&p->uf_entry.tv.head, &p->validated);
 531
 532         /* Get userptr backing pages. If pages are updated after registered
 533          * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
 534          * amdgpu_ttm_backend_bind() to flush and invalidate new pages
 535          */
 536         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
 537                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 538                 bool userpage_invalidated = false;
 539                 int i;
 540
 541                 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
 542                                         sizeof(struct page *),
 543                                         GFP_KERNEL | __GFP_ZERO);
 544                 if (!e->user_pages) {
 545                         DRM_ERROR("kvmalloc_array failure\n");
 546                         return -ENOMEM;
 547                 }
 548
 549                 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages);
 550                 if (r) {
 551                         kvfree(e->user_pages);
 552                         e->user_pages = NULL;
 553                         return r;
 554                 }
 555
 556                 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
 557                         if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
 558                                 userpage_invalidated = true;
 559                                 break;
 560                         }
 561                 }
 562                 e->user_invalidated = userpage_invalidated;
 563         }
 564
 565         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
 566                                    &duplicates);
 567         if (unlikely(r != 0)) {
 568                 if (r != -ERESTARTSYS)
 569                         DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
 570                 goto out;
 571         }
 572
 573         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 574                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 575
 576                 e->bo_va = amdgpu_vm_bo_find(vm, bo);
 577         }
 578
 579         /* Move fence waiting after getting reservation lock of
 580          * PD root. Then there is no need on a ctx mutex lock.
 581          */
 582         r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entity);
 583         if (unlikely(r != 0)) {
 584                 if (r != -ERESTARTSYS)
 585                         DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
 586                 goto error_validate;
 587         }
 588
 589         amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
 590                                           &p->bytes_moved_vis_threshold);
 591         p->bytes_moved = 0;
 592         p->bytes_moved_vis = 0;
 593
 594         r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
 595                                       amdgpu_cs_bo_validate, p);
 596         if (r) {
 597                 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
 598                 goto error_validate;
 599         }
 600
 601         r = amdgpu_cs_list_validate(p, &duplicates);
 602         if (r)
 603                 goto error_validate;
 604
 605         r = amdgpu_cs_list_validate(p, &p->validated);
 606         if (r)
 607                 goto error_validate;
 608
 609         amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
 610                                      p->bytes_moved_vis);
 611
 612         gds = p->bo_list->gds_obj;
 613         gws = p->bo_list->gws_obj;
 614         oa = p->bo_list->oa_obj;
 615
 616         if (gds) {
 617                 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
 618                 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
 619         }
 620         if (gws) {
 621                 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
 622                 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
 623         }
 624         if (oa) {
 625                 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
 626                 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
 627         }
 628
 629         if (!r && p->uf_entry.tv.bo) {
 630                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
 631
 632                 r = amdgpu_ttm_alloc_gart(&uf->tbo);
 633                 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
 634         }
 635
 636 error_validate:
 637         if (r)
 638                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 639 out:
 640         return r;
 641 }
 642
 643 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 644 {
 645         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 646         struct amdgpu_bo_list_entry *e;
 647         int r;
 648
 649         list_for_each_entry(e, &p->validated, tv.head) {
 650                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 651                 struct dma_resv *resv = bo->tbo.base.resv;
 652                 enum amdgpu_sync_mode sync_mode;
 653
 654                 sync_mode = amdgpu_bo_explicit_sync(bo) ?
 655                         AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
 656                 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode,
 657                                      &fpriv->vm);
 658                 if (r)
 659                         return r;
 660         }
 661         return 0;
 662 }
 663
 664 /**
 665  * amdgpu_cs_parser_fini() - clean parser states
 666  * @parser:     parser structure holding parsing context.
 667  * @error:      error number
 668  * @backoff:    indicator to backoff the reservation
 669  *
 670  * If error is set then unvalidate buffer, otherwise just free memory
 671  * used by parsing context.
 672  **/
 673 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 674                                   bool backoff)
 675 {
 676         unsigned i;
 677
 678         if (error && backoff)
 679                 ttm_eu_backoff_reservation(&parser->ticket,
 680                                            &parser->validated);
 681
 682         for (i = 0; i < parser->num_post_deps; i++) {
 683                 drm_syncobj_put(parser->post_deps[i].syncobj);
 684                 kfree(parser->post_deps[i].chain);
 685         }
 686         kfree(parser->post_deps);
 687
 688         dma_fence_put(parser->fence);
 689
 690         if (parser->ctx) {
 691                 amdgpu_ctx_put(parser->ctx);
 692         }
 693         if (parser->bo_list)
 694                 amdgpu_bo_list_put(parser->bo_list);
 695
 696         for (i = 0; i < parser->nchunks; i++)
 697                 kvfree(parser->chunks[i].kdata);
 698         kvfree(parser->chunks);
 699         if (parser->job)
 700                 amdgpu_job_free(parser->job);
 701         if (parser->uf_entry.tv.bo) {
 702                 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
 703
 704                 amdgpu_bo_unref(&uf);
 705         }
 706 }
 707
 708 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 709 {
 710         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 711         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 712         struct amdgpu_device *adev = p->adev;
 713         struct amdgpu_vm *vm = &fpriv->vm;
 714         struct amdgpu_bo_list_entry *e;
 715         struct amdgpu_bo_va *bo_va;
 716         struct amdgpu_bo *bo;
 717         int r;
 718
 719         /* Only for UVD/VCE VM emulation */
 720         if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
 721                 unsigned i, j;
 722
 723                 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
 724                         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 725                         struct amdgpu_bo_va_mapping *m;
 726                         struct amdgpu_bo *aobj = NULL;
 727                         struct amdgpu_cs_chunk *chunk;
 728                         uint64_t offset, va_start;
 729                         struct amdgpu_ib *ib;
 730                         uint8_t *kptr;
 731
 732                         chunk = &p->chunks[i];
 733                         ib = &p->job->ibs[j];
 734                         chunk_ib = chunk->kdata;
 735
 736                         if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 737                                 continue;
 738
 739                         va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 740                         r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 741                         if (r) {
 742                                 DRM_ERROR("IB va_start is invalid\n");
 743                                 return r;
 744                         }
 745
 746                         if ((va_start + chunk_ib->ib_bytes) >
 747                             (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 748                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 749                                 return -EINVAL;
 750                         }
 751
 752                         /* the IB should be reserved at this point */
 753                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 754                         if (r) {
 755                                 return r;
 756                         }
 757
 758                         offset = m->start * AMDGPU_GPU_PAGE_SIZE;
 759                         kptr += va_start - offset;
 760
 761                         if (ring->funcs->parse_cs) {
 762                                 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 763                                 amdgpu_bo_kunmap(aobj);
 764
 765                                 r = amdgpu_ring_parse_cs(ring, p, p->job, ib);
 766                                 if (r)
 767                                         return r;
 768                         } else {
 769                                 ib->ptr = (uint32_t *)kptr;
 770                                 r = amdgpu_ring_patch_cs_in_place(ring, p, p->job, ib);
 771                                 amdgpu_bo_kunmap(aobj);
 772                                 if (r)
 773                                         return r;
 774                         }
 775
 776                         j++;
 777                 }
 778         }
 779
 780         if (!p->job->vm)
 781                 return amdgpu_cs_sync_rings(p);
 782
 783
 784         r = amdgpu_vm_clear_freed(adev, vm, NULL);
 785         if (r)
 786                 return r;
 787
 788         r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
 789         if (r)
 790                 return r;
 791
 792         r = amdgpu_sync_fence(&p->job->sync, fpriv->prt_va->last_pt_update);
 793         if (r)
 794                 return r;
 795
 796         if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
 797                 bo_va = fpriv->csa_va;
 798                 BUG_ON(!bo_va);
 799                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 800                 if (r)
 801                         return r;
 802
 803                 r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);
 804                 if (r)
 805                         return r;
 806         }
 807
 808         amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 809                 /* ignore duplicates */
 810                 bo = ttm_to_amdgpu_bo(e->tv.bo);
 811                 if (!bo)
 812                         continue;
 813
 814                 bo_va = e->bo_va;
 815                 if (bo_va == NULL)
 816                         continue;
 817
 818                 r = amdgpu_vm_bo_update(adev, bo_va, false);
 819                 if (r)
 820                         return r;
 821
 822                 r = amdgpu_sync_fence(&p->job->sync, bo_va->last_pt_update);
 823                 if (r)
 824                         return r;
 825         }
 826
 827         r = amdgpu_vm_handle_moved(adev, vm);
 828         if (r)
 829                 return r;
 830
 831         r = amdgpu_vm_update_pdes(adev, vm, false);
 832         if (r)
 833                 return r;
 834
 835         r = amdgpu_sync_fence(&p->job->sync, vm->last_update);
 836         if (r)
 837                 return r;
 838
 839         p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
 840
 841         if (amdgpu_vm_debug) {
 842                 /* Invalidate all BOs to test for userspace bugs */
 843                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
 844                         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
 845
 846                         /* ignore duplicates */
 847                         if (!bo)
 848                                 continue;
 849
 850                         amdgpu_vm_bo_invalidate(adev, bo, false);
 851                 }
 852         }
 853
 854         return amdgpu_cs_sync_rings(p);
 855 }
 856
 857 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 858                              struct amdgpu_cs_parser *parser)
 859 {
 860         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 861         struct amdgpu_vm *vm = &fpriv->vm;
 862         int r, ce_preempt = 0, de_preempt = 0;
 863         struct amdgpu_ring *ring;
 864         int i, j;
 865
 866         for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
 867                 struct amdgpu_cs_chunk *chunk;
 868                 struct amdgpu_ib *ib;
 869                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 870                 struct drm_sched_entity *entity;
 871
 872                 chunk = &parser->chunks[i];
 873                 ib = &parser->job->ibs[j];
 874                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 875
 876                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 877                         continue;
 878
 879                 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
 880                     (amdgpu_mcbp || amdgpu_sriov_vf(adev))) {
 881                         if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
 882                                 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
 883                                         ce_preempt++;
 884                                 else
 885                                         de_preempt++;
 886                         }
 887
 888                         /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
 889                         if (ce_preempt > 1 || de_preempt > 1)
 890                                 return -EINVAL;
 891                 }
 892
 893                 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
 894                                           chunk_ib->ip_instance, chunk_ib->ring,
 895                                           &entity);
 896                 if (r)
 897                         return r;
 898
 899                 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
 900                         parser->job->preamble_status |=
 901                                 AMDGPU_PREAMBLE_IB_PRESENT;
 902
 903                 if (parser->entity && parser->entity != entity)
 904                         return -EINVAL;
 905
 906                 /* Return if there is no run queue associated with this entity.
 907                  * Possibly because of disabled HW IP*/
 908                 if (entity->rq == NULL)
 909                         return -EINVAL;
 910
 911                 parser->entity = entity;
 912
 913                 ring = to_amdgpu_ring(entity->rq->sched);
 914                 r =  amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
 915                                    chunk_ib->ib_bytes : 0,
 916                                    AMDGPU_IB_POOL_DELAYED, ib);
 917                 if (r) {
 918                         DRM_ERROR("Failed to get ib !\n");
 919                         return r;
 920                 }
 921
 922                 ib->gpu_addr = chunk_ib->va_start;
 923                 ib->length_dw = chunk_ib->ib_bytes / 4;
 924                 ib->flags = chunk_ib->flags;
 925
 926                 j++;
 927         }
 928
 929         /* MM engine doesn't support user fences */
 930         ring = to_amdgpu_ring(parser->entity->rq->sched);
 931         if (parser->job->uf_addr && ring->funcs->no_user_fence)
 932                 return -EINVAL;
 933
 934         return 0;
 935 }
 936
 937 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
 938                                        struct amdgpu_cs_chunk *chunk)
 939 {
 940         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 941         unsigned num_deps;
 942         int i, r;
 943         struct drm_amdgpu_cs_chunk_dep *deps;
 944
 945         deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 946         num_deps = chunk->length_dw * 4 /
 947                 sizeof(struct drm_amdgpu_cs_chunk_dep);
 948
 949         for (i = 0; i < num_deps; ++i) {
 950                 struct amdgpu_ctx *ctx;
 951                 struct drm_sched_entity *entity;
 952                 struct dma_fence *fence;
 953
 954                 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
 955                 if (ctx == NULL)
 956                         return -EINVAL;
 957
 958                 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
 959                                           deps[i].ip_instance,
 960                                           deps[i].ring, &entity);
 961                 if (r) {
 962                         amdgpu_ctx_put(ctx);
 963                         return r;
 964                 }
 965
 966                 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
 967                 amdgpu_ctx_put(ctx);
 968
 969                 if (IS_ERR(fence))
 970                         return PTR_ERR(fence);
 971                 else if (!fence)
 972                         continue;
 973
 974                 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
 975                         struct drm_sched_fence *s_fence;
 976                         struct dma_fence *old = fence;
 977
 978                         s_fence = to_drm_sched_fence(fence);
 979                         fence = dma_fence_get(&s_fence->scheduled);
 980                         dma_fence_put(old);
 981                 }
 982
 983                 r = amdgpu_sync_fence(&p->job->sync, fence);
 984                 dma_fence_put(fence);
 985                 if (r)
 986                         return r;
 987         }
 988         return 0;
 989 }
 990
 991 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
 992                                                  uint32_t handle, u64 point,
 993                                                  u64 flags)
 994 {
 995         struct dma_fence *fence;
 996         int r;
 997
 998         r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
 999         if (r) {
1000                 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
1001                           handle, point, r);
1002                 return r;
1003         }
1004
1005         r = amdgpu_sync_fence(&p->job->sync, fence);
1006         dma_fence_put(fence);
1007
1008         return r;
1009 }
1010
1011 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1012                                             struct amdgpu_cs_chunk *chunk)
1013 {
1014         struct drm_amdgpu_cs_chunk_sem *deps;
1015         unsigned num_deps;
1016         int i, r;
1017
1018         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1019         num_deps = chunk->length_dw * 4 /
1020                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1021         for (i = 0; i < num_deps; ++i) {
1022                 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle,
1023                                                           0, 0);
1024                 if (r)
1025                         return r;
1026         }
1027
1028         return 0;
1029 }
1030
1031
1032 static int amdgpu_cs_process_syncobj_timeline_in_dep(struct amdgpu_cs_parser *p,
1033                                                      struct amdgpu_cs_chunk *chunk)
1034 {
1035         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1036         unsigned num_deps;
1037         int i, r;
1038
1039         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1040         num_deps = chunk->length_dw * 4 /
1041                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1042         for (i = 0; i < num_deps; ++i) {
1043                 r = amdgpu_syncobj_lookup_and_add_to_sync(p,
1044                                                           syncobj_deps[i].handle,
1045                                                           syncobj_deps[i].point,
1046                                                           syncobj_deps[i].flags);
1047                 if (r)
1048                         return r;
1049         }
1050
1051         return 0;
1052 }
1053
1054 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1055                                              struct amdgpu_cs_chunk *chunk)
1056 {
1057         struct drm_amdgpu_cs_chunk_sem *deps;
1058         unsigned num_deps;
1059         int i;
1060
1061         deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1062         num_deps = chunk->length_dw * 4 /
1063                 sizeof(struct drm_amdgpu_cs_chunk_sem);
1064
1065         if (p->post_deps)
1066                 return -EINVAL;
1067
1068         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1069                                      GFP_KERNEL);
1070         p->num_post_deps = 0;
1071
1072         if (!p->post_deps)
1073                 return -ENOMEM;
1074
1075
1076         for (i = 0; i < num_deps; ++i) {
1077                 p->post_deps[i].syncobj =
1078                         drm_syncobj_find(p->filp, deps[i].handle);
1079                 if (!p->post_deps[i].syncobj)
1080                         return -EINVAL;
1081                 p->post_deps[i].chain = NULL;
1082                 p->post_deps[i].point = 0;
1083                 p->num_post_deps++;
1084         }
1085
1086         return 0;
1087 }
1088
1089
1090 static int amdgpu_cs_process_syncobj_timeline_out_dep(struct amdgpu_cs_parser *p,
1091                                                       struct amdgpu_cs_chunk *chunk)
1092 {
1093         struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps;
1094         unsigned num_deps;
1095         int i;
1096
1097         syncobj_deps = (struct drm_amdgpu_cs_chunk_syncobj *)chunk->kdata;
1098         num_deps = chunk->length_dw * 4 /
1099                 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
1100
1101         if (p->post_deps)
1102                 return -EINVAL;
1103
1104         p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
1105                                      GFP_KERNEL);
1106         p->num_post_deps = 0;
1107
1108         if (!p->post_deps)
1109                 return -ENOMEM;
1110
1111         for (i = 0; i < num_deps; ++i) {
1112                 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
1113
1114                 dep->chain = NULL;
1115                 if (syncobj_deps[i].point) {
1116                         dep->chain = dma_fence_chain_alloc();
1117                         if (!dep->chain)
1118                                 return -ENOMEM;
1119                 }
1120
1121                 dep->syncobj = drm_syncobj_find(p->filp,
1122                                                 syncobj_deps[i].handle);
1123                 if (!dep->syncobj) {
1124                         dma_fence_chain_free(dep->chain);
1125                         return -EINVAL;
1126                 }
1127                 dep->point = syncobj_deps[i].point;
1128                 p->num_post_deps++;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1135                                   struct amdgpu_cs_parser *p)
1136 {
1137         int i, r;
1138
1139         for (i = 0; i < p->nchunks; ++i) {
1140                 struct amdgpu_cs_chunk *chunk;
1141
1142                 chunk = &p->chunks[i];
1143
1144                 switch (chunk->chunk_id) {
1145                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
1146                 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
1147                         r = amdgpu_cs_process_fence_dep(p, chunk);
1148                         if (r)
1149                                 return r;
1150                         break;
1151                 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
1152                         r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1153                         if (r)
1154                                 return r;
1155                         break;
1156                 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
1157                         r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1158                         if (r)
1159                                 return r;
1160                         break;
1161                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
1162                         r = amdgpu_cs_process_syncobj_timeline_in_dep(p, chunk);
1163                         if (r)
1164                                 return r;
1165                         break;
1166                 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
1167                         r = amdgpu_cs_process_syncobj_timeline_out_dep(p, chunk);
1168                         if (r)
1169                                 return r;
1170                         break;
1171                 }
1172         }
1173
1174         return 0;
1175 }
1176
1177 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1178 {
1179         int i;
1180
1181         for (i = 0; i < p->num_post_deps; ++i) {
1182                 if (p->post_deps[i].chain && p->post_deps[i].point) {
1183                         drm_syncobj_add_point(p->post_deps[i].syncobj,
1184                                               p->post_deps[i].chain,
1185                                               p->fence, p->post_deps[i].point);
1186                         p->post_deps[i].chain = NULL;
1187                 } else {
1188                         drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1189                                                   p->fence);
1190                 }
1191         }
1192 }
1193
1194 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1195                             union drm_amdgpu_cs *cs)
1196 {
1197         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1198         struct drm_sched_entity *entity = p->entity;
1199         struct amdgpu_bo_list_entry *e;
1200         struct amdgpu_job *job;
1201         uint64_t seq;
1202         int r;
1203
1204         job = p->job;
1205         p->job = NULL;
1206
1207         r = drm_sched_job_init(&job->base, entity, &fpriv->vm);
1208         if (r)
1209                 goto error_unlock;
1210
1211         drm_sched_job_arm(&job->base);
1212
1213         /* No memory allocation is allowed while holding the notifier lock.
1214          * The lock is held until amdgpu_cs_submit is finished and fence is
1215          * added to BOs.
1216          */
1217         mutex_lock(&p->adev->notifier_lock);
1218
1219         /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1220          * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1221          */
1222         amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1223                 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1224
1225                 r |= !amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
1226         }
1227         if (r) {
1228                 r = -EAGAIN;
1229                 goto error_abort;
1230         }
1231
1232         p->fence = dma_fence_get(&job->base.s_fence->finished);
1233
1234         amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1235         amdgpu_cs_post_dependencies(p);
1236
1237         if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1238             !p->ctx->preamble_presented) {
1239                 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1240                 p->ctx->preamble_presented = true;
1241         }
1242
1243         cs->out.handle = seq;
1244         job->uf_sequence = seq;
1245
1246         amdgpu_job_free_resources(job);
1247
1248         trace_amdgpu_cs_ioctl(job);
1249         amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1250         drm_sched_entity_push_job(&job->base);
1251
1252         amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1253
1254         /* Make sure all BOs are remembered as writers */
1255         amdgpu_bo_list_for_each_entry(e, p->bo_list)
1256                 e->tv.num_shared = 0;
1257
1258         ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1259         mutex_unlock(&p->adev->notifier_lock);
1260
1261         return 0;
1262
1263 error_abort:
1264         drm_sched_job_cleanup(&job->base);
1265         mutex_unlock(&p->adev->notifier_lock);
1266
1267 error_unlock:
1268         amdgpu_job_free(job);
1269         return r;
1270 }
1271
1272 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *parser)
1273 {
1274         int i;
1275
1276         if (!trace_amdgpu_cs_enabled())
1277                 return;
1278
1279         for (i = 0; i < parser->job->num_ibs; i++)
1280                 trace_amdgpu_cs(parser, i);
1281 }
1282
1283 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1284 {
1285         struct amdgpu_device *adev = drm_to_adev(dev);
1286         union drm_amdgpu_cs *cs = data;
1287         struct amdgpu_cs_parser parser = {};
1288         bool reserved_buffers = false;
1289         int r;
1290
1291         if (amdgpu_ras_intr_triggered())
1292                 return -EHWPOISON;
1293
1294         if (!adev->accel_working)
1295                 return -EBUSY;
1296
1297         parser.adev = adev;
1298         parser.filp = filp;
1299
1300         r = amdgpu_cs_parser_init(&parser, data);
1301         if (r) {
1302                 if (printk_ratelimit())
1303                         DRM_ERROR("Failed to initialize parser %d!\n", r);
1304                 goto out;
1305         }
1306
1307         r = amdgpu_cs_ib_fill(adev, &parser);
1308         if (r)
1309                 goto out;
1310
1311         r = amdgpu_cs_dependencies(adev, &parser);
1312         if (r) {
1313                 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1314                 goto out;
1315         }
1316
1317         r = amdgpu_cs_parser_bos(&parser, data);
1318         if (r) {
1319                 if (r == -ENOMEM)
1320                         DRM_ERROR("Not enough memory for command submission!\n");
1321                 else if (r != -ERESTARTSYS && r != -EAGAIN)
1322                         DRM_ERROR("Failed to process the buffer list %d!\n", r);
1323                 goto out;
1324         }
1325
1326         reserved_buffers = true;
1327
1328         trace_amdgpu_cs_ibs(&parser);
1329
1330         r = amdgpu_cs_vm_handling(&parser);
1331         if (r)
1332                 goto out;
1333
1334         r = amdgpu_cs_submit(&parser, cs);
1335 out:
1336         amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1337
1338         return r;
1339 }
1340
1341 /**
1342  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1343  *
1344  * @dev: drm device
1345  * @data: data from userspace
1346  * @filp: file private
1347  *
1348  * Wait for the command submission identified by handle to finish.
1349  */
1350 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1351                          struct drm_file *filp)
1352 {
1353         union drm_amdgpu_wait_cs *wait = data;
1354         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1355         struct drm_sched_entity *entity;
1356         struct amdgpu_ctx *ctx;
1357         struct dma_fence *fence;
1358         long r;
1359
1360         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1361         if (ctx == NULL)
1362                 return -EINVAL;
1363
1364         r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1365                                   wait->in.ring, &entity);
1366         if (r) {
1367                 amdgpu_ctx_put(ctx);
1368                 return r;
1369         }
1370
1371         fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1372         if (IS_ERR(fence))
1373                 r = PTR_ERR(fence);
1374         else if (fence) {
1375                 r = dma_fence_wait_timeout(fence, true, timeout);
1376                 if (r > 0 && fence->error)
1377                         r = fence->error;
1378                 dma_fence_put(fence);
1379         } else
1380                 r = 1;
1381
1382         amdgpu_ctx_put(ctx);
1383         if (r < 0)
1384                 return r;
1385
1386         memset(wait, 0, sizeof(*wait));
1387         wait->out.status = (r == 0);
1388
1389         return 0;
1390 }
1391
1392 /**
1393  * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1394  *
1395  * @adev: amdgpu device
1396  * @filp: file private
1397  * @user: drm_amdgpu_fence copied from user space
1398  */
1399 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1400                                              struct drm_file *filp,
1401                                              struct drm_amdgpu_fence *user)
1402 {
1403         struct drm_sched_entity *entity;
1404         struct amdgpu_ctx *ctx;
1405         struct dma_fence *fence;
1406         int r;
1407
1408         ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1409         if (ctx == NULL)
1410                 return ERR_PTR(-EINVAL);
1411
1412         r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1413                                   user->ring, &entity);
1414         if (r) {
1415                 amdgpu_ctx_put(ctx);
1416                 return ERR_PTR(r);
1417         }
1418
1419         fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1420         amdgpu_ctx_put(ctx);
1421
1422         return fence;
1423 }
1424
1425 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1426                                     struct drm_file *filp)
1427 {
1428         struct amdgpu_device *adev = drm_to_adev(dev);
1429         union drm_amdgpu_fence_to_handle *info = data;
1430         struct dma_fence *fence;
1431         struct drm_syncobj *syncobj;
1432         struct sync_file *sync_file;
1433         int fd, r;
1434
1435         fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1436         if (IS_ERR(fence))
1437                 return PTR_ERR(fence);
1438
1439         if (!fence)
1440                 fence = dma_fence_get_stub();
1441
1442         switch (info->in.what) {
1443         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1444                 r = drm_syncobj_create(&syncobj, 0, fence);
1445                 dma_fence_put(fence);
1446                 if (r)
1447                         return r;
1448                 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1449                 drm_syncobj_put(syncobj);
1450                 return r;
1451
1452         case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1453                 r = drm_syncobj_create(&syncobj, 0, fence);
1454                 dma_fence_put(fence);
1455                 if (r)
1456                         return r;
1457                 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1458                 drm_syncobj_put(syncobj);
1459                 return r;
1460
1461         case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1462                 fd = get_unused_fd_flags(O_CLOEXEC);
1463                 if (fd < 0) {
1464                         dma_fence_put(fence);
1465                         return fd;
1466                 }
1467
1468                 sync_file = sync_file_create(fence);
1469                 dma_fence_put(fence);
1470                 if (!sync_file) {
1471                         put_unused_fd(fd);
1472                         return -ENOMEM;
1473                 }
1474
1475                 fd_install(fd, sync_file->file);
1476                 info->out.handle = fd;
1477                 return 0;
1478
1479         default:
1480                 dma_fence_put(fence);
1481                 return -EINVAL;
1482         }
1483 }
1484
1485 /**
1486  * amdgpu_cs_wait_all_fences - wait on all fences to signal
1487  *
1488  * @adev: amdgpu device
1489  * @filp: file private
1490  * @wait: wait parameters
1491  * @fences: array of drm_amdgpu_fence
1492  */
1493 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1494                                      struct drm_file *filp,
1495                                      union drm_amdgpu_wait_fences *wait,
1496                                      struct drm_amdgpu_fence *fences)
1497 {
1498         uint32_t fence_count = wait->in.fence_count;
1499         unsigned int i;
1500         long r = 1;
1501
1502         for (i = 0; i < fence_count; i++) {
1503                 struct dma_fence *fence;
1504                 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1505
1506                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1507                 if (IS_ERR(fence))
1508                         return PTR_ERR(fence);
1509                 else if (!fence)
1510                         continue;
1511
1512                 r = dma_fence_wait_timeout(fence, true, timeout);
1513                 dma_fence_put(fence);
1514                 if (r < 0)
1515                         return r;
1516
1517                 if (r == 0)
1518                         break;
1519
1520                 if (fence->error)
1521                         return fence->error;
1522         }
1523
1524         memset(wait, 0, sizeof(*wait));
1525         wait->out.status = (r > 0);
1526
1527         return 0;
1528 }
1529
1530 /**
1531  * amdgpu_cs_wait_any_fence - wait on any fence to signal
1532  *
1533  * @adev: amdgpu device
1534  * @filp: file private
1535  * @wait: wait parameters
1536  * @fences: array of drm_amdgpu_fence
1537  */
1538 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1539                                     struct drm_file *filp,
1540                                     union drm_amdgpu_wait_fences *wait,
1541                                     struct drm_amdgpu_fence *fences)
1542 {
1543         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1544         uint32_t fence_count = wait->in.fence_count;
1545         uint32_t first = ~0;
1546         struct dma_fence **array;
1547         unsigned int i;
1548         long r;
1549
1550         /* Prepare the fence array */
1551         array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1552
1553         if (array == NULL)
1554                 return -ENOMEM;
1555
1556         for (i = 0; i < fence_count; i++) {
1557                 struct dma_fence *fence;
1558
1559                 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1560                 if (IS_ERR(fence)) {
1561                         r = PTR_ERR(fence);
1562                         goto err_free_fence_array;
1563                 } else if (fence) {
1564                         array[i] = fence;
1565                 } else { /* NULL, the fence has been already signaled */
1566                         r = 1;
1567                         first = i;
1568                         goto out;
1569                 }
1570         }
1571
1572         r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1573                                        &first);
1574         if (r < 0)
1575                 goto err_free_fence_array;
1576
1577 out:
1578         memset(wait, 0, sizeof(*wait));
1579         wait->out.status = (r > 0);
1580         wait->out.first_signaled = first;
1581
1582         if (first < fence_count && array[first])
1583                 r = array[first]->error;
1584         else
1585                 r = 0;
1586
1587 err_free_fence_array:
1588         for (i = 0; i < fence_count; i++)
1589                 dma_fence_put(array[i]);
1590         kfree(array);
1591
1592         return r;
1593 }
1594
1595 /**
1596  * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1597  *
1598  * @dev: drm device
1599  * @data: data from userspace
1600  * @filp: file private
1601  */
1602 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1603                                 struct drm_file *filp)
1604 {
1605         struct amdgpu_device *adev = drm_to_adev(dev);
1606         union drm_amdgpu_wait_fences *wait = data;
1607         uint32_t fence_count = wait->in.fence_count;
1608         struct drm_amdgpu_fence *fences_user;
1609         struct drm_amdgpu_fence *fences;
1610         int r;
1611
1612         /* Get the fences from userspace */
1613         fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1614                         GFP_KERNEL);
1615         if (fences == NULL)
1616                 return -ENOMEM;
1617
1618         fences_user = u64_to_user_ptr(wait->in.fences);
1619         if (copy_from_user(fences, fences_user,
1620                 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1621                 r = -EFAULT;
1622                 goto err_free_fences;
1623         }
1624
1625         if (wait->in.wait_all)
1626                 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1627         else
1628                 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1629
1630 err_free_fences:
1631         kfree(fences);
1632
1633         return r;
1634 }
1635
1636 /**
1637  * amdgpu_cs_find_mapping - find bo_va for VM address
1638  *
1639  * @parser: command submission parser context
1640  * @addr: VM address
1641  * @bo: resulting BO of the mapping found
1642  * @map: Placeholder to return found BO mapping
1643  *
1644  * Search the buffer objects in the command submission context for a certain
1645  * virtual memory address. Returns allocation structure when found, NULL
1646  * otherwise.
1647  */
1648 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1649                            uint64_t addr, struct amdgpu_bo **bo,
1650                            struct amdgpu_bo_va_mapping **map)
1651 {
1652         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1653         struct ttm_operation_ctx ctx = { false, false };
1654         struct amdgpu_vm *vm = &fpriv->vm;
1655         struct amdgpu_bo_va_mapping *mapping;
1656         int r;
1657
1658         addr /= AMDGPU_GPU_PAGE_SIZE;
1659
1660         mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1661         if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1662                 return -EINVAL;
1663
1664         *bo = mapping->bo_va->base.bo;
1665         *map = mapping;
1666
1667         /* Double check that the BO is reserved by this CS */
1668         if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->ticket)
1669                 return -EINVAL;
1670
1671         if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1672                 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1673                 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1674                 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1675                 if (r)
1676                         return r;
1677         }
1678
1679         return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1680 }