drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_discovery.h"
  28 #include "soc15_hw_ip.h"
  29 #include "discovery.h"
  30
  31 #include "soc15.h"
  32 #include "gfx_v9_0.h"
  33 #include "gmc_v9_0.h"
  34 #include "df_v1_7.h"
  35 #include "df_v3_6.h"
  36 #include "nbio_v6_1.h"
  37 #include "nbio_v7_0.h"
  38 #include "nbio_v7_4.h"
  39 #include "hdp_v4_0.h"
  40 #include "vega10_ih.h"
  41 #include "vega20_ih.h"
  42 #include "sdma_v4_0.h"
  43 #include "uvd_v7_0.h"
  44 #include "vce_v4_0.h"
  45 #include "vcn_v1_0.h"
  46 #include "vcn_v2_5.h"
  47 #include "jpeg_v2_5.h"
  48 #include "smuio_v9_0.h"
  49 #include "gmc_v10_0.h"
  50 #include "gfxhub_v2_0.h"
  51 #include "mmhub_v2_0.h"
  52 #include "nbio_v2_3.h"
  53 #include "nbio_v7_2.h"
  54 #include "hdp_v5_0.h"
  55 #include "nv.h"
  56 #include "navi10_ih.h"
  57 #include "gfx_v10_0.h"
  58 #include "sdma_v5_0.h"
  59 #include "sdma_v5_2.h"
  60 #include "vcn_v2_0.h"
  61 #include "jpeg_v2_0.h"
  62 #include "vcn_v3_0.h"
  63 #include "jpeg_v3_0.h"
  64 #include "amdgpu_vkms.h"
  65 #include "mes_v10_1.h"
  66 #include "smuio_v11_0.h"
  67 #include "smuio_v11_0_6.h"
  68 #include "smuio_v13_0.h"
  69
  70 MODULE_FIRMWARE("amdgpu/ip_discovery.bin");
  71
  72 #define mmRCC_CONFIG_MEMSIZE    0xde3
  73 #define mmMM_INDEX              0x0
  74 #define mmMM_INDEX_HI           0x6
  75 #define mmMM_DATA               0x1
  76
  77 static const char *hw_id_names[HW_ID_MAX] = {
  78         [MP1_HWID]              = "MP1",
  79         [MP2_HWID]              = "MP2",
  80         [THM_HWID]              = "THM",
  81         [SMUIO_HWID]            = "SMUIO",
  82         [FUSE_HWID]             = "FUSE",
  83         [CLKA_HWID]             = "CLKA",
  84         [PWR_HWID]              = "PWR",
  85         [GC_HWID]               = "GC",
  86         [UVD_HWID]              = "UVD",
  87         [AUDIO_AZ_HWID]         = "AUDIO_AZ",
  88         [ACP_HWID]              = "ACP",
  89         [DCI_HWID]              = "DCI",
  90         [DMU_HWID]              = "DMU",
  91         [DCO_HWID]              = "DCO",
  92         [DIO_HWID]              = "DIO",
  93         [XDMA_HWID]             = "XDMA",
  94         [DCEAZ_HWID]            = "DCEAZ",
  95         [DAZ_HWID]              = "DAZ",
  96         [SDPMUX_HWID]           = "SDPMUX",
  97         [NTB_HWID]              = "NTB",
  98         [IOHC_HWID]             = "IOHC",
  99         [L2IMU_HWID]            = "L2IMU",
 100         [VCE_HWID]              = "VCE",
 101         [MMHUB_HWID]            = "MMHUB",
 102         [ATHUB_HWID]            = "ATHUB",
 103         [DBGU_NBIO_HWID]        = "DBGU_NBIO",
 104         [DFX_HWID]              = "DFX",
 105         [DBGU0_HWID]            = "DBGU0",
 106         [DBGU1_HWID]            = "DBGU1",
 107         [OSSSYS_HWID]           = "OSSSYS",
 108         [HDP_HWID]              = "HDP",
 109         [SDMA0_HWID]            = "SDMA0",
 110         [SDMA1_HWID]            = "SDMA1",
 111         [ISP_HWID]              = "ISP",
 112         [DBGU_IO_HWID]          = "DBGU_IO",
 113         [DF_HWID]               = "DF",
 114         [CLKB_HWID]             = "CLKB",
 115         [FCH_HWID]              = "FCH",
 116         [DFX_DAP_HWID]          = "DFX_DAP",
 117         [L1IMU_PCIE_HWID]       = "L1IMU_PCIE",
 118         [L1IMU_NBIF_HWID]       = "L1IMU_NBIF",
 119         [L1IMU_IOAGR_HWID]      = "L1IMU_IOAGR",
 120         [L1IMU3_HWID]           = "L1IMU3",
 121         [L1IMU4_HWID]           = "L1IMU4",
 122         [L1IMU5_HWID]           = "L1IMU5",
 123         [L1IMU6_HWID]           = "L1IMU6",
 124         [L1IMU7_HWID]           = "L1IMU7",
 125         [L1IMU8_HWID]           = "L1IMU8",
 126         [L1IMU9_HWID]           = "L1IMU9",
 127         [L1IMU10_HWID]          = "L1IMU10",
 128         [L1IMU11_HWID]          = "L1IMU11",
 129         [L1IMU12_HWID]          = "L1IMU12",
 130         [L1IMU13_HWID]          = "L1IMU13",
 131         [L1IMU14_HWID]          = "L1IMU14",
 132         [L1IMU15_HWID]          = "L1IMU15",
 133         [WAFLC_HWID]            = "WAFLC",
 134         [FCH_USB_PD_HWID]       = "FCH_USB_PD",
 135         [PCIE_HWID]             = "PCIE",
 136         [PCS_HWID]              = "PCS",
 137         [DDCL_HWID]             = "DDCL",
 138         [SST_HWID]              = "SST",
 139         [IOAGR_HWID]            = "IOAGR",
 140         [NBIF_HWID]             = "NBIF",
 141         [IOAPIC_HWID]           = "IOAPIC",
 142         [SYSTEMHUB_HWID]        = "SYSTEMHUB",
 143         [NTBCCP_HWID]           = "NTBCCP",
 144         [UMC_HWID]              = "UMC",
 145         [SATA_HWID]             = "SATA",
 146         [USB_HWID]              = "USB",
 147         [CCXSEC_HWID]           = "CCXSEC",
 148         [XGMI_HWID]             = "XGMI",
 149         [XGBE_HWID]             = "XGBE",
 150         [MP0_HWID]              = "MP0",
 151 };
 152
 153 static int hw_id_map[MAX_HWIP] = {
 154         [GC_HWIP]       = GC_HWID,
 155         [HDP_HWIP]      = HDP_HWID,
 156         [SDMA0_HWIP]    = SDMA0_HWID,
 157         [SDMA1_HWIP]    = SDMA1_HWID,
 158         [MMHUB_HWIP]    = MMHUB_HWID,
 159         [ATHUB_HWIP]    = ATHUB_HWID,
 160         [NBIO_HWIP]     = NBIF_HWID,
 161         [MP0_HWIP]      = MP0_HWID,
 162         [MP1_HWIP]      = MP1_HWID,
 163         [UVD_HWIP]      = UVD_HWID,
 164         [VCE_HWIP]      = VCE_HWID,
 165         [DF_HWIP]       = DF_HWID,
 166         [DCE_HWIP]      = DMU_HWID,
 167         [OSSSYS_HWIP]   = OSSSYS_HWID,
 168         [SMUIO_HWIP]    = SMUIO_HWID,
 169         [PWR_HWIP]      = PWR_HWID,
 170         [NBIF_HWIP]     = NBIF_HWID,
 171         [THM_HWIP]      = THM_HWID,
 172         [CLK_HWIP]      = CLKA_HWID,
 173         [UMC_HWIP]      = UMC_HWID,
 174         [XGMI_HWIP]     = XGMI_HWID,
 175         [DCI_HWIP]      = DCI_HWID,
 176 };
 177
 178 static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t *binary)
 179 {
 180         uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
 181         uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET;
 182
 183         amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
 184                                   adev->mman.discovery_tmr_size, false);
 185         return 0;
 186 }
 187
 188 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size)
 189 {
 190         uint16_t checksum = 0;
 191         int i;
 192
 193         for (i = 0; i < size; i++)
 194                 checksum += data[i];
 195
 196         return checksum;
 197 }
 198
 199 static inline bool amdgpu_discovery_verify_checksum(uint8_t *data, uint32_t size,
 200                                                     uint16_t expected)
 201 {
 202         return !!(amdgpu_discovery_calculate_checksum(data, size) == expected);
 203 }
 204
 205 static int amdgpu_discovery_init(struct amdgpu_device *adev)
 206 {
 207         struct table_info *info;
 208         struct binary_header *bhdr;
 209         struct ip_discovery_header *ihdr;
 210         struct gpu_info_header *ghdr;
 211         const struct firmware *fw;
 212         uint16_t offset;
 213         uint16_t size;
 214         uint16_t checksum;
 215         int r;
 216
 217         adev->mman.discovery_tmr_size = DISCOVERY_TMR_SIZE;
 218         adev->mman.discovery_bin = kzalloc(adev->mman.discovery_tmr_size, GFP_KERNEL);
 219         if (!adev->mman.discovery_bin)
 220                 return -ENOMEM;
 221
 222         if (amdgpu_discovery == 2) {
 223                 r = request_firmware(&fw, "amdgpu/ip_discovery.bin", adev->dev);
 224                 if (r)
 225                         goto get_from_vram;
 226                 dev_info(adev->dev, "Using IP discovery from file\n");
 227                 memcpy((u8 *)adev->mman.discovery_bin, (u8 *)fw->data,
 228                        adev->mman.discovery_tmr_size);
 229                 release_firmware(fw);
 230         } else {
 231 get_from_vram:
 232                 r = amdgpu_discovery_read_binary(adev, adev->mman.discovery_bin);
 233                 if (r) {
 234                         DRM_ERROR("failed to read ip discovery binary\n");
 235                         goto out;
 236                 }
 237         }
 238
 239         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 240
 241         if (le32_to_cpu(bhdr->binary_signature) != BINARY_SIGNATURE) {
 242                 DRM_ERROR("invalid ip discovery binary signature\n");
 243                 r = -EINVAL;
 244                 goto out;
 245         }
 246
 247         offset = offsetof(struct binary_header, binary_checksum) +
 248                 sizeof(bhdr->binary_checksum);
 249         size = bhdr->binary_size - offset;
 250         checksum = bhdr->binary_checksum;
 251
 252         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 253                                               size, checksum)) {
 254                 DRM_ERROR("invalid ip discovery binary checksum\n");
 255                 r = -EINVAL;
 256                 goto out;
 257         }
 258
 259         info = &bhdr->table_list[IP_DISCOVERY];
 260         offset = le16_to_cpu(info->offset);
 261         checksum = le16_to_cpu(info->checksum);
 262         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin + offset);
 263
 264         if (le32_to_cpu(ihdr->signature) != DISCOVERY_TABLE_SIGNATURE) {
 265                 DRM_ERROR("invalid ip discovery data table signature\n");
 266                 r = -EINVAL;
 267                 goto out;
 268         }
 269
 270         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 271                                               ihdr->size, checksum)) {
 272                 DRM_ERROR("invalid ip discovery data table checksum\n");
 273                 r = -EINVAL;
 274                 goto out;
 275         }
 276
 277         info = &bhdr->table_list[GC];
 278         offset = le16_to_cpu(info->offset);
 279         checksum = le16_to_cpu(info->checksum);
 280         ghdr = (struct gpu_info_header *)(adev->mman.discovery_bin + offset);
 281
 282         if (!amdgpu_discovery_verify_checksum(adev->mman.discovery_bin + offset,
 283                                               ghdr->size, checksum)) {
 284                 DRM_ERROR("invalid gc data table checksum\n");
 285                 r = -EINVAL;
 286                 goto out;
 287         }
 288
 289         return 0;
 290
 291 out:
 292         kfree(adev->mman.discovery_bin);
 293         adev->mman.discovery_bin = NULL;
 294
 295         return r;
 296 }
 297
 298 void amdgpu_discovery_fini(struct amdgpu_device *adev)
 299 {
 300         kfree(adev->mman.discovery_bin);
 301         adev->mman.discovery_bin = NULL;
 302 }
 303
 304 static int amdgpu_discovery_validate_ip(const struct ip *ip)
 305 {
 306         if (ip->number_instance >= HWIP_MAX_INSTANCE) {
 307                 DRM_ERROR("Unexpected number_instance (%d) from ip discovery blob\n",
 308                           ip->number_instance);
 309                 return -EINVAL;
 310         }
 311         if (le16_to_cpu(ip->hw_id) >= HW_ID_MAX) {
 312                 DRM_ERROR("Unexpected hw_id (%d) from ip discovery blob\n",
 313                           le16_to_cpu(ip->hw_id));
 314                 return -EINVAL;
 315         }
 316
 317         return 0;
 318 }
 319
 320 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 321 {
 322         struct binary_header *bhdr;
 323         struct ip_discovery_header *ihdr;
 324         struct die_header *dhdr;
 325         struct ip *ip;
 326         uint16_t die_offset;
 327         uint16_t ip_offset;
 328         uint16_t num_dies;
 329         uint16_t num_ips;
 330         uint8_t num_base_address;
 331         int hw_ip;
 332         int i, j, k;
 333         int r;
 334
 335         r = amdgpu_discovery_init(adev);
 336         if (r) {
 337                 DRM_ERROR("amdgpu_discovery_init failed\n");
 338                 return r;
 339         }
 340
 341         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 342         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 343                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 344         num_dies = le16_to_cpu(ihdr->num_dies);
 345
 346         DRM_DEBUG("number of dies: %d\n", num_dies);
 347
 348         for (i = 0; i < num_dies; i++) {
 349                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 350                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 351                 num_ips = le16_to_cpu(dhdr->num_ips);
 352                 ip_offset = die_offset + sizeof(*dhdr);
 353
 354                 if (le16_to_cpu(dhdr->die_id) != i) {
 355                         DRM_ERROR("invalid die id %d, expected %d\n",
 356                                         le16_to_cpu(dhdr->die_id), i);
 357                         return -EINVAL;
 358                 }
 359
 360                 DRM_DEBUG("number of hardware IPs on die%d: %d\n",
 361                                 le16_to_cpu(dhdr->die_id), num_ips);
 362
 363                 for (j = 0; j < num_ips; j++) {
 364                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 365
 366                         if (amdgpu_discovery_validate_ip(ip))
 367                                 goto next_ip;
 368
 369                         num_base_address = ip->num_base_address;
 370
 371                         DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n",
 372                                   hw_id_names[le16_to_cpu(ip->hw_id)],
 373                                   le16_to_cpu(ip->hw_id),
 374                                   ip->number_instance,
 375                                   ip->major, ip->minor,
 376                                   ip->revision);
 377
 378                         if (le16_to_cpu(ip->hw_id) == VCN_HWID)
 379                                 adev->vcn.num_vcn_inst++;
 380                         if (le16_to_cpu(ip->hw_id) == SDMA0_HWID ||
 381                             le16_to_cpu(ip->hw_id) == SDMA1_HWID ||
 382                             le16_to_cpu(ip->hw_id) == SDMA2_HWID ||
 383                             le16_to_cpu(ip->hw_id) == SDMA3_HWID)
 384                                 adev->sdma.num_instances++;
 385
 386                         for (k = 0; k < num_base_address; k++) {
 387                                 /*
 388                                  * convert the endianness of base addresses in place,
 389                                  * so that we don't need to convert them when accessing adev->reg_offset.
 390                                  */
 391                                 ip->base_address[k] = le32_to_cpu(ip->base_address[k]);
 392                                 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]);
 393                         }
 394
 395                         for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) {
 396                                 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id)) {
 397                                         DRM_DEBUG("set register base offset for %s\n",
 398                                                         hw_id_names[le16_to_cpu(ip->hw_id)]);
 399                                         adev->reg_offset[hw_ip][ip->number_instance] =
 400                                                 ip->base_address;
 401                                         /* Instance support is somewhat inconsistent.
 402                                          * SDMA is a good example.  Sienna cichlid has 4 total
 403                                          * SDMA instances, each enumerated separately (HWIDs
 404                                          * 42, 43, 68, 69).  Arcturus has 8 total SDMA instances,
 405                                          * but they are enumerated as multiple instances of the
 406                                          * same HWIDs (4x HWID 42, 4x HWID 43).  UMC is another
 407                                          * example.  On most chips there are multiple instances
 408                                          * with the same HWID.
 409                                          */
 410                                         adev->ip_versions[hw_ip][ip->number_instance] =
 411                                                 IP_VERSION(ip->major, ip->minor, ip->revision);
 412                                 }
 413                         }
 414
 415 next_ip:
 416                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 417                 }
 418         }
 419
 420         return 0;
 421 }
 422
 423 int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int number_instance,
 424                                     int *major, int *minor, int *revision)
 425 {
 426         struct binary_header *bhdr;
 427         struct ip_discovery_header *ihdr;
 428         struct die_header *dhdr;
 429         struct ip *ip;
 430         uint16_t die_offset;
 431         uint16_t ip_offset;
 432         uint16_t num_dies;
 433         uint16_t num_ips;
 434         int i, j;
 435
 436         if (!adev->mman.discovery_bin) {
 437                 DRM_ERROR("ip discovery uninitialized\n");
 438                 return -EINVAL;
 439         }
 440
 441         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 442         ihdr = (struct ip_discovery_header *)(adev->mman.discovery_bin +
 443                         le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset));
 444         num_dies = le16_to_cpu(ihdr->num_dies);
 445
 446         for (i = 0; i < num_dies; i++) {
 447                 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset);
 448                 dhdr = (struct die_header *)(adev->mman.discovery_bin + die_offset);
 449                 num_ips = le16_to_cpu(dhdr->num_ips);
 450                 ip_offset = die_offset + sizeof(*dhdr);
 451
 452                 for (j = 0; j < num_ips; j++) {
 453                         ip = (struct ip *)(adev->mman.discovery_bin + ip_offset);
 454
 455                         if ((le16_to_cpu(ip->hw_id) == hw_id) && (ip->number_instance == number_instance)) {
 456                                 if (major)
 457                                         *major = ip->major;
 458                                 if (minor)
 459                                         *minor = ip->minor;
 460                                 if (revision)
 461                                         *revision = ip->revision;
 462                                 return 0;
 463                         }
 464                         ip_offset += sizeof(*ip) + 4 * (ip->num_base_address - 1);
 465                 }
 466         }
 467
 468         return -EINVAL;
 469 }
 470
 471
 472 int amdgpu_discovery_get_vcn_version(struct amdgpu_device *adev, int vcn_instance,
 473                                      int *major, int *minor, int *revision)
 474 {
 475         return amdgpu_discovery_get_ip_version(adev, VCN_HWID,
 476                                                vcn_instance, major, minor, revision);
 477 }
 478
 479 void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 480 {
 481         struct binary_header *bhdr;
 482         struct harvest_table *harvest_info;
 483         int i, vcn_harvest_count = 0;
 484
 485         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 486         harvest_info = (struct harvest_table *)(adev->mman.discovery_bin +
 487                         le16_to_cpu(bhdr->table_list[HARVEST_INFO].offset));
 488
 489         for (i = 0; i < 32; i++) {
 490                 if (le32_to_cpu(harvest_info->list[i].hw_id) == 0)
 491                         break;
 492
 493                 switch (le32_to_cpu(harvest_info->list[i].hw_id)) {
 494                 case VCN_HWID:
 495                         vcn_harvest_count++;
 496                         if (harvest_info->list[i].number_instance == 0)
 497                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0;
 498                         else
 499                                 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1;
 500                         break;
 501                 case DMU_HWID:
 502                         adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
 503                         break;
 504                 default:
 505                         break;
 506                 }
 507         }
 508         if (vcn_harvest_count == adev->vcn.num_vcn_inst) {
 509                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 510                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 511         }
 512         if ((adev->pdev->device == 0x731E &&
 513              (adev->pdev->revision == 0xC6 || adev->pdev->revision == 0xC7)) ||
 514             (adev->pdev->device == 0x7340 && adev->pdev->revision == 0xC9)  ||
 515             (adev->pdev->device == 0x7360 && adev->pdev->revision == 0xC7)) {
 516                 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK;
 517                 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK;
 518         }
 519 }
 520
 521 int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 522 {
 523         struct binary_header *bhdr;
 524         struct gc_info_v1_0 *gc_info;
 525
 526         if (!adev->mman.discovery_bin) {
 527                 DRM_ERROR("ip discovery uninitialized\n");
 528                 return -EINVAL;
 529         }
 530
 531         bhdr = (struct binary_header *)adev->mman.discovery_bin;
 532         gc_info = (struct gc_info_v1_0 *)(adev->mman.discovery_bin +
 533                         le16_to_cpu(bhdr->table_list[GC].offset));
 534
 535         adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->gc_num_se);
 536         adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->gc_num_wgp0_per_sa) +
 537                                               le32_to_cpu(gc_info->gc_num_wgp1_per_sa));
 538         adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->gc_num_sa_per_se);
 539         adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->gc_num_rb_per_se);
 540         adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->gc_num_gl2c);
 541         adev->gfx.config.max_gprs = le32_to_cpu(gc_info->gc_num_gprs);
 542         adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->gc_num_max_gs_thds);
 543         adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->gc_gs_table_depth);
 544         adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->gc_gsprim_buff_depth);
 545         adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->gc_double_offchip_lds_buffer);
 546         adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->gc_wave_size);
 547         adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->gc_max_waves_per_simd);
 548         adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->gc_max_scratch_slots_per_cu);
 549         adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->gc_lds_size);
 550         adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->gc_num_sc_per_se) /
 551                                          le32_to_cpu(gc_info->gc_num_sa_per_se);
 552         adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->gc_num_packer_per_sc);
 553
 554         return 0;
 555 }
 556
 557 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
 558 {
 559         /* what IP to use for this? */
 560         switch (adev->ip_versions[GC_HWIP][0]) {
 561         case IP_VERSION(9, 0, 1):
 562         case IP_VERSION(9, 1, 0):
 563         case IP_VERSION(9, 2, 1):
 564         case IP_VERSION(9, 2, 2):
 565         case IP_VERSION(9, 3, 0):
 566         case IP_VERSION(9, 4, 0):
 567         case IP_VERSION(9, 4, 1):
 568         case IP_VERSION(9, 4, 2):
 569                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
 570                 break;
 571         case IP_VERSION(10, 1, 10):
 572         case IP_VERSION(10, 1, 1):
 573         case IP_VERSION(10, 1, 2):
 574         case IP_VERSION(10, 1, 3):
 575         case IP_VERSION(10, 3, 0):
 576         case IP_VERSION(10, 3, 1):
 577         case IP_VERSION(10, 3, 2):
 578         case IP_VERSION(10, 3, 3):
 579         case IP_VERSION(10, 3, 4):
 580         case IP_VERSION(10, 3, 5):
 581                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 582                 break;
 583         default:
 584                 return -EINVAL;
 585         }
 586         return 0;
 587 }
 588
 589 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev)
 590 {
 591         /* use GC or MMHUB IP version */
 592         switch (adev->ip_versions[GC_HWIP][0]) {
 593         case IP_VERSION(9, 0, 1):
 594         case IP_VERSION(9, 1, 0):
 595         case IP_VERSION(9, 2, 1):
 596         case IP_VERSION(9, 2, 2):
 597         case IP_VERSION(9, 3, 0):
 598         case IP_VERSION(9, 4, 0):
 599         case IP_VERSION(9, 4, 1):
 600         case IP_VERSION(9, 4, 2):
 601                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
 602                 break;
 603         case IP_VERSION(10, 1, 10):
 604         case IP_VERSION(10, 1, 1):
 605         case IP_VERSION(10, 1, 2):
 606         case IP_VERSION(10, 1, 3):
 607         case IP_VERSION(10, 3, 0):
 608         case IP_VERSION(10, 3, 1):
 609         case IP_VERSION(10, 3, 2):
 610         case IP_VERSION(10, 3, 3):
 611         case IP_VERSION(10, 3, 4):
 612         case IP_VERSION(10, 3, 5):
 613                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618         return 0;
 619 }
 620
 621 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
 622 {
 623         switch (adev->ip_versions[OSSSYS_HWIP][0]) {
 624         case IP_VERSION(4, 0, 0):
 625         case IP_VERSION(4, 0, 1):
 626         case IP_VERSION(4, 1, 0):
 627         case IP_VERSION(4, 1, 1):
 628         case IP_VERSION(4, 3, 0):
 629                 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
 630                 break;
 631         case IP_VERSION(4, 2, 0):
 632         case IP_VERSION(4, 2, 1):
 633         case IP_VERSION(4, 4, 0):
 634                 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block);
 635                 break;
 636         case IP_VERSION(5, 0, 0):
 637         case IP_VERSION(5, 0, 1):
 638         case IP_VERSION(5, 0, 2):
 639         case IP_VERSION(5, 0, 3):
 640         case IP_VERSION(5, 2, 0):
 641         case IP_VERSION(5, 2, 1):
 642                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 643                 break;
 644         default:
 645                 return -EINVAL;
 646         }
 647         return 0;
 648 }
 649
 650 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev)
 651 {
 652         switch (adev->ip_versions[MP0_HWIP][0]) {
 653         case IP_VERSION(9, 0, 0):
 654                 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
 655                 break;
 656         case IP_VERSION(10, 0, 0):
 657         case IP_VERSION(10, 0, 1):
 658                 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
 659                 break;
 660         case IP_VERSION(11, 0, 0):
 661         case IP_VERSION(11, 0, 2):
 662         case IP_VERSION(11, 0, 4):
 663         case IP_VERSION(11, 0, 5):
 664         case IP_VERSION(11, 0, 9):
 665         case IP_VERSION(11, 0, 7):
 666         case IP_VERSION(11, 0, 11):
 667         case IP_VERSION(11, 0, 12):
 668         case IP_VERSION(11, 0, 13):
 669         case IP_VERSION(11, 5, 0):
 670                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 671                 break;
 672         case IP_VERSION(11, 0, 8):
 673                 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block);
 674                 break;
 675         case IP_VERSION(11, 0, 3):
 676         case IP_VERSION(12, 0, 1):
 677                 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block);
 678                 break;
 679         case IP_VERSION(13, 0, 1):
 680         case IP_VERSION(13, 0, 2):
 681         case IP_VERSION(13, 0, 3):
 682                 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block);
 683                 break;
 684         default:
 685                 return -EINVAL;
 686         }
 687         return 0;
 688 }
 689
 690 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
 691 {
 692         switch (adev->ip_versions[MP1_HWIP][0]) {
 693         case IP_VERSION(9, 0, 0):
 694         case IP_VERSION(10, 0, 0):
 695         case IP_VERSION(10, 0, 1):
 696         case IP_VERSION(11, 0, 2):
 697                 if (adev->asic_type == CHIP_ARCTURUS)
 698                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 699                 else
 700                         amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
 701                 break;
 702         case IP_VERSION(11, 0, 0):
 703         case IP_VERSION(11, 0, 5):
 704         case IP_VERSION(11, 0, 9):
 705         case IP_VERSION(11, 0, 7):
 706         case IP_VERSION(11, 0, 8):
 707         case IP_VERSION(11, 0, 11):
 708         case IP_VERSION(11, 0, 12):
 709         case IP_VERSION(11, 0, 13):
 710         case IP_VERSION(11, 5, 0):
 711                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 712                 break;
 713         case IP_VERSION(12, 0, 0):
 714         case IP_VERSION(12, 0, 1):
 715                 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block);
 716                 break;
 717         case IP_VERSION(13, 0, 1):
 718         case IP_VERSION(13, 0, 2):
 719         case IP_VERSION(13, 0, 3):
 720                 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
 721                 break;
 722         default:
 723                 return -EINVAL;
 724         }
 725         return 0;
 726 }
 727
 728 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev)
 729 {
 730         if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) {
 731                 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
 732 #if defined(CONFIG_DRM_AMD_DC)
 733         } else if (adev->ip_versions[DCE_HWIP][0]) {
 734                 switch (adev->ip_versions[DCE_HWIP][0]) {
 735                 case IP_VERSION(1, 0, 0):
 736                 case IP_VERSION(1, 0, 1):
 737                 case IP_VERSION(2, 0, 2):
 738                 case IP_VERSION(2, 0, 0):
 739                 case IP_VERSION(2, 1, 0):
 740                 case IP_VERSION(3, 0, 0):
 741                 case IP_VERSION(3, 0, 2):
 742                 case IP_VERSION(3, 0, 3):
 743                 case IP_VERSION(3, 0, 1):
 744                 case IP_VERSION(3, 1, 2):
 745                 case IP_VERSION(3, 1, 3):
 746                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 747                         break;
 748                 case IP_VERSION(2, 0, 3):
 749                         break;
 750                 default:
 751                         return -EINVAL;
 752                 }
 753         } else if (adev->ip_versions[DCI_HWIP][0]) {
 754                 switch (adev->ip_versions[DCI_HWIP][0]) {
 755                 case IP_VERSION(12, 0, 0):
 756                 case IP_VERSION(12, 0, 1):
 757                 case IP_VERSION(12, 1, 0):
 758                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 759                         break;
 760                 default:
 761                         return -EINVAL;
 762                 }
 763 #endif
 764         }
 765         return 0;
 766 }
 767
 768 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
 769 {
 770         switch (adev->ip_versions[GC_HWIP][0]) {
 771         case IP_VERSION(9, 0, 1):
 772         case IP_VERSION(9, 1, 0):
 773         case IP_VERSION(9, 2, 1):
 774         case IP_VERSION(9, 2, 2):
 775         case IP_VERSION(9, 3, 0):
 776         case IP_VERSION(9, 4, 0):
 777         case IP_VERSION(9, 4, 1):
 778         case IP_VERSION(9, 4, 2):
 779                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
 780                 break;
 781         case IP_VERSION(10, 1, 10):
 782         case IP_VERSION(10, 1, 2):
 783         case IP_VERSION(10, 1, 1):
 784         case IP_VERSION(10, 1, 3):
 785         case IP_VERSION(10, 3, 0):
 786         case IP_VERSION(10, 3, 2):
 787         case IP_VERSION(10, 3, 1):
 788         case IP_VERSION(10, 3, 4):
 789         case IP_VERSION(10, 3, 5):
 790         case IP_VERSION(10, 3, 3):
 791                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 792                 break;
 793         default:
 794                 return -EINVAL;
 795         }
 796         return 0;
 797 }
 798
 799 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev)
 800 {
 801         switch (adev->ip_versions[SDMA0_HWIP][0]) {
 802         case IP_VERSION(4, 0, 0):
 803         case IP_VERSION(4, 0, 1):
 804         case IP_VERSION(4, 1, 0):
 805         case IP_VERSION(4, 1, 1):
 806         case IP_VERSION(4, 1, 2):
 807         case IP_VERSION(4, 2, 0):
 808         case IP_VERSION(4, 2, 2):
 809         case IP_VERSION(4, 4, 0):
 810                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
 811                 break;
 812         case IP_VERSION(5, 0, 0):
 813         case IP_VERSION(5, 0, 1):
 814         case IP_VERSION(5, 0, 2):
 815         case IP_VERSION(5, 0, 5):
 816                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 817                 break;
 818         case IP_VERSION(5, 2, 0):
 819         case IP_VERSION(5, 2, 2):
 820         case IP_VERSION(5, 2, 4):
 821         case IP_VERSION(5, 2, 5):
 822         case IP_VERSION(5, 2, 3):
 823         case IP_VERSION(5, 2, 1):
 824                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 825                 break;
 826         default:
 827                 return -EINVAL;
 828         }
 829         return 0;
 830 }
 831
 832 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev)
 833 {
 834         if (adev->ip_versions[VCE_HWIP][0]) {
 835                 switch (adev->ip_versions[UVD_HWIP][0]) {
 836                 case IP_VERSION(7, 0, 0):
 837                 case IP_VERSION(7, 2, 0):
 838                         /* UVD is not supported on vega20 SR-IOV */
 839                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 840                                 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
 841                         break;
 842                 default:
 843                         return -EINVAL;
 844                 }
 845                 switch (adev->ip_versions[VCE_HWIP][0]) {
 846                 case IP_VERSION(4, 0, 0):
 847                 case IP_VERSION(4, 1, 0):
 848                         /* VCE is not supported on vega20 SR-IOV */
 849                         if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev)))
 850                                 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
 851                         break;
 852                 default:
 853                         return -EINVAL;
 854                 }
 855         } else {
 856                 switch (adev->ip_versions[UVD_HWIP][0]) {
 857                 case IP_VERSION(1, 0, 0):
 858                 case IP_VERSION(1, 0, 1):
 859                         amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
 860                         break;
 861                 case IP_VERSION(2, 0, 0):
 862                 case IP_VERSION(2, 0, 2):
 863                 case IP_VERSION(2, 2, 0):
 864                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 865                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 866                         break;
 867                 case IP_VERSION(2, 0, 3):
 868                         break;
 869                 case IP_VERSION(2, 5, 0):
 870                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
 871                         amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block);
 872                         break;
 873                 case IP_VERSION(2, 6, 0):
 874                         amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block);
 875                         amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block);
 876                         break;
 877                 case IP_VERSION(3, 0, 0):
 878                 case IP_VERSION(3, 0, 16):
 879                 case IP_VERSION(3, 1, 1):
 880                 case IP_VERSION(3, 0, 2):
 881                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 882                         if (!amdgpu_sriov_vf(adev))
 883                                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 884                         break;
 885                 case IP_VERSION(3, 0, 33):
 886                         amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 887                         break;
 888                 default:
 889                         return -EINVAL;
 890                 }
 891         }
 892         return 0;
 893 }
 894
 895 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
 896 {
 897         switch (adev->ip_versions[GC_HWIP][0]) {
 898         case IP_VERSION(10, 1, 10):
 899         case IP_VERSION(10, 1, 1):
 900         case IP_VERSION(10, 1, 2):
 901         case IP_VERSION(10, 1, 3):
 902         case IP_VERSION(10, 3, 0):
 903         case IP_VERSION(10, 3, 1):
 904         case IP_VERSION(10, 3, 2):
 905         case IP_VERSION(10, 3, 3):
 906         case IP_VERSION(10, 3, 4):
 907         case IP_VERSION(10, 3, 5):
 908                 amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 909                 break;
 910         default:
 911                 break;;
 912         }
 913         return 0;
 914 }
 915
 916 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 917 {
 918         int r;
 919
 920         switch (adev->asic_type) {
 921         case CHIP_VEGA10:
 922                 vega10_reg_base_init(adev);
 923                 adev->sdma.num_instances = 2;
 924                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 925                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 926                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
 927                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0);
 928                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0);
 929                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
 930                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0);
 931                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0);
 932                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
 933                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
 934                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
 935                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0);
 936                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1);
 937                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
 938                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
 939                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0);
 940                 break;
 941         case CHIP_VEGA12:
 942                 vega10_reg_base_init(adev);
 943                 adev->sdma.num_instances = 2;
 944                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 945                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 946                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
 947                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1);
 948                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1);
 949                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0);
 950                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0);
 951                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0);
 952                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0);
 953                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0);
 954                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0);
 955                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1);
 956                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1);
 957                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0);
 958                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0);
 959                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1);
 960                 break;
 961         case CHIP_RAVEN:
 962                 vega10_reg_base_init(adev);
 963                 adev->sdma.num_instances = 1;
 964                 adev->vcn.num_vcn_inst = 1;
 965                 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
 966                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
 967                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
 968                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1);
 969                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1);
 970                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1);
 971                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1);
 972                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1);
 973                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0);
 974                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1);
 975                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1);
 976                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0);
 977                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1);
 978                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2);
 979                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1);
 980                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1);
 981                 } else {
 982                         adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0);
 983                         adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0);
 984                         adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0);
 985                         adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0);
 986                         adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0);
 987                         adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0);
 988                         adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0);
 989                         adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0);
 990                         adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0);
 991                         adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0);
 992                         adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0);
 993                         adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0);
 994                         adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0);
 995                         adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0);
 996                         adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0);
 997                 }
 998                 break;
 999         case CHIP_VEGA20:
1000                 vega20_reg_base_init(adev);
1001                 adev->sdma.num_instances = 2;
1002                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1003                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
1004                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
1005                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0);
1006                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0);
1007                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0);
1008                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0);
1009                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1);
1010                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2);
1011                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1012                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2);
1013                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2);
1014                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0);
1015                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0);
1016                 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0);
1017                 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0);
1018                 break;
1019         case CHIP_ARCTURUS:
1020                 arct_reg_base_init(adev);
1021                 adev->sdma.num_instances = 8;
1022                 adev->vcn.num_vcn_inst = 2;
1023                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1024                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
1025                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
1026                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1);
1027                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2);
1028                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1);
1029                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1);
1030                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2);
1031                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4);
1032                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2);
1033                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3);
1034                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3);
1035                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1);
1036                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0);
1037                 break;
1038         case CHIP_ALDEBARAN:
1039                 aldebaran_reg_base_init(adev);
1040                 adev->sdma.num_instances = 5;
1041                 adev->vcn.num_vcn_inst = 2;
1042                 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1043                 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
1044                 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
1045                 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0);
1046                 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0);
1047                 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2);
1048                 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4);
1049                 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0);
1050                 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2);
1051                 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2);
1052                 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2);
1053                 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2);
1054                 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2);
1055                 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0);
1056                 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0);
1057                 break;
1058         default:
1059                 r = amdgpu_discovery_reg_base_init(adev);
1060                 if (r)
1061                         return -EINVAL;
1062
1063                 amdgpu_discovery_harvest_ip(adev);
1064
1065                 if (!adev->mman.discovery_bin) {
1066                         DRM_ERROR("ip discovery uninitialized\n");
1067                         return -EINVAL;
1068                 }
1069                 break;
1070         }
1071
1072         switch (adev->ip_versions[GC_HWIP][0]) {
1073         case IP_VERSION(9, 0, 1):
1074         case IP_VERSION(9, 2, 1):
1075         case IP_VERSION(9, 4, 0):
1076         case IP_VERSION(9, 4, 1):
1077         case IP_VERSION(9, 4, 2):
1078                 adev->family = AMDGPU_FAMILY_AI;
1079                 break;
1080         case IP_VERSION(9, 1, 0):
1081         case IP_VERSION(9, 2, 2):
1082         case IP_VERSION(9, 3, 0):
1083                 adev->family = AMDGPU_FAMILY_RV;
1084                 break;
1085         case IP_VERSION(10, 1, 10):
1086         case IP_VERSION(10, 1, 1):
1087         case IP_VERSION(10, 1, 2):
1088         case IP_VERSION(10, 1, 3):
1089         case IP_VERSION(10, 3, 0):
1090         case IP_VERSION(10, 3, 2):
1091         case IP_VERSION(10, 3, 4):
1092         case IP_VERSION(10, 3, 5):
1093                 adev->family = AMDGPU_FAMILY_NV;
1094                 break;
1095         case IP_VERSION(10, 3, 1):
1096                 adev->family = AMDGPU_FAMILY_VGH;
1097                 break;
1098         case IP_VERSION(10, 3, 3):
1099                 adev->family = AMDGPU_FAMILY_YC;
1100                 break;
1101         default:
1102                 return -EINVAL;
1103         }
1104
1105         if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(4, 8, 0))
1106                 adev->gmc.xgmi.supported = true;
1107
1108         /* set NBIO version */
1109         switch (adev->ip_versions[NBIO_HWIP][0]) {
1110         case IP_VERSION(6, 1, 0):
1111         case IP_VERSION(6, 2, 0):
1112                 adev->nbio.funcs = &nbio_v6_1_funcs;
1113                 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg;
1114                 break;
1115         case IP_VERSION(7, 0, 0):
1116         case IP_VERSION(7, 0, 1):
1117         case IP_VERSION(2, 5, 0):
1118                 adev->nbio.funcs = &nbio_v7_0_funcs;
1119                 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
1120                 break;
1121         case IP_VERSION(7, 4, 0):
1122         case IP_VERSION(7, 4, 1):
1123         case IP_VERSION(7, 4, 4):
1124                 adev->nbio.funcs = &nbio_v7_4_funcs;
1125                 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
1126                 break;
1127         case IP_VERSION(7, 2, 0):
1128         case IP_VERSION(7, 2, 1):
1129         case IP_VERSION(7, 5, 0):
1130                 adev->nbio.funcs = &nbio_v7_2_funcs;
1131                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
1132                 break;
1133         case IP_VERSION(2, 1, 1):
1134         case IP_VERSION(2, 3, 0):
1135         case IP_VERSION(2, 3, 1):
1136         case IP_VERSION(2, 3, 2):
1137         case IP_VERSION(3, 3, 0):
1138         case IP_VERSION(3, 3, 1):
1139         case IP_VERSION(3, 3, 2):
1140         case IP_VERSION(3, 3, 3):
1141                 adev->nbio.funcs = &nbio_v2_3_funcs;
1142                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
1143                 break;
1144         default:
1145                 break;
1146         }
1147
1148         switch (adev->ip_versions[HDP_HWIP][0]) {
1149         case IP_VERSION(4, 0, 0):
1150         case IP_VERSION(4, 0, 1):
1151         case IP_VERSION(4, 1, 0):
1152         case IP_VERSION(4, 1, 1):
1153         case IP_VERSION(4, 1, 2):
1154         case IP_VERSION(4, 2, 0):
1155         case IP_VERSION(4, 2, 1):
1156         case IP_VERSION(4, 4, 0):
1157                 adev->hdp.funcs = &hdp_v4_0_funcs;
1158                 break;
1159         case IP_VERSION(5, 0, 0):
1160         case IP_VERSION(5, 0, 1):
1161         case IP_VERSION(5, 0, 2):
1162         case IP_VERSION(5, 0, 3):
1163         case IP_VERSION(5, 0, 4):
1164         case IP_VERSION(5, 2, 0):
1165                 adev->hdp.funcs = &hdp_v5_0_funcs;
1166                 break;
1167         default:
1168                 break;
1169         }
1170
1171         switch (adev->ip_versions[DF_HWIP][0]) {
1172         case IP_VERSION(3, 6, 0):
1173         case IP_VERSION(3, 6, 1):
1174         case IP_VERSION(3, 6, 2):
1175                 adev->df.funcs = &df_v3_6_funcs;
1176                 break;
1177         case IP_VERSION(2, 1, 0):
1178         case IP_VERSION(2, 1, 1):
1179         case IP_VERSION(2, 5, 0):
1180         case IP_VERSION(3, 5, 1):
1181         case IP_VERSION(3, 5, 2):
1182                 adev->df.funcs = &df_v1_7_funcs;
1183                 break;
1184         default:
1185                 break;
1186         }
1187
1188         switch (adev->ip_versions[SMUIO_HWIP][0]) {
1189         case IP_VERSION(9, 0, 0):
1190         case IP_VERSION(9, 0, 1):
1191         case IP_VERSION(10, 0, 0):
1192         case IP_VERSION(10, 0, 1):
1193         case IP_VERSION(10, 0, 2):
1194                 adev->smuio.funcs = &smuio_v9_0_funcs;
1195                 break;
1196         case IP_VERSION(11, 0, 0):
1197         case IP_VERSION(11, 0, 2):
1198         case IP_VERSION(11, 0, 3):
1199         case IP_VERSION(11, 0, 4):
1200         case IP_VERSION(11, 0, 7):
1201         case IP_VERSION(11, 0, 8):
1202                 adev->smuio.funcs = &smuio_v11_0_funcs;
1203                 break;
1204         case IP_VERSION(11, 0, 6):
1205         case IP_VERSION(11, 0, 10):
1206         case IP_VERSION(11, 0, 11):
1207         case IP_VERSION(11, 5, 0):
1208         case IP_VERSION(13, 0, 1):
1209                 adev->smuio.funcs = &smuio_v11_0_6_funcs;
1210                 break;
1211         case IP_VERSION(13, 0, 2):
1212                 adev->smuio.funcs = &smuio_v13_0_funcs;
1213                 break;
1214         default:
1215                 break;
1216         }
1217
1218         r = amdgpu_discovery_set_common_ip_blocks(adev);
1219         if (r)
1220                 return r;
1221
1222         r = amdgpu_discovery_set_gmc_ip_blocks(adev);
1223         if (r)
1224                 return r;
1225
1226         /* For SR-IOV, PSP needs to be initialized before IH */
1227         if (amdgpu_sriov_vf(adev)) {
1228                 r = amdgpu_discovery_set_psp_ip_blocks(adev);
1229                 if (r)
1230                         return r;
1231                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1232                 if (r)
1233                         return r;
1234         } else {
1235                 r = amdgpu_discovery_set_ih_ip_blocks(adev);
1236                 if (r)
1237                         return r;
1238
1239                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1240                         r = amdgpu_discovery_set_psp_ip_blocks(adev);
1241                         if (r)
1242                                 return r;
1243                 }
1244         }
1245
1246         if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1247                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1248                 if (r)
1249                         return r;
1250         }
1251
1252         r = amdgpu_discovery_set_display_ip_blocks(adev);
1253         if (r)
1254                 return r;
1255
1256         r = amdgpu_discovery_set_gc_ip_blocks(adev);
1257         if (r)
1258                 return r;
1259
1260         r = amdgpu_discovery_set_sdma_ip_blocks(adev);
1261         if (r)
1262                 return r;
1263
1264         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
1265             !amdgpu_sriov_vf(adev)) {
1266                 r = amdgpu_discovery_set_smu_ip_blocks(adev);
1267                 if (r)
1268                         return r;
1269         }
1270
1271         r = amdgpu_discovery_set_mm_ip_blocks(adev);
1272         if (r)
1273                 return r;
1274
1275         if (adev->enable_mes) {
1276                 r = amdgpu_discovery_set_mes_ip_blocks(adev);
1277                 if (r)
1278                         return r;
1279         }
1280
1281         return 0;
1282 }
1283