drivers/soc/mediatek/mt8183-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8183-power.h>
   8
   9 /*
  10  * MT8183 power domain support
  11  */
  12
  13 static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
  14         [MT8183_POWER_DOMAIN_AUDIO] = {
  15                 .name = "audio",
  16                 .sta_mask = PWR_STATUS_AUDIO,
  17                 .ctl_offs = 0x0314,
  18                 .sram_pdn_bits = GENMASK(11, 8),
  19                 .sram_pdn_ack_bits = GENMASK(15, 12),
  20         },
  21         [MT8183_POWER_DOMAIN_CONN] = {
  22                 .name = "conn",
  23                 .sta_mask = PWR_STATUS_CONN,
  24                 .ctl_offs = 0x032c,
  25                 .sram_pdn_bits = 0,
  26                 .sram_pdn_ack_bits = 0,
  27                 .bp_infracfg = {
  28                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
  29                                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
  30                 },
  31         },
  32         [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
  33                 .name = "mfg_async",
  34                 .sta_mask = PWR_STATUS_MFG_ASYNC,
  35                 .ctl_offs = 0x0334,
  36                 .sram_pdn_bits = 0,
  37                 .sram_pdn_ack_bits = 0,
  38         },
  39         [MT8183_POWER_DOMAIN_MFG] = {
  40                 .name = "mfg",
  41                 .sta_mask = PWR_STATUS_MFG,
  42                 .ctl_offs = 0x0338,
  43                 .sram_pdn_bits = GENMASK(8, 8),
  44                 .sram_pdn_ack_bits = GENMASK(12, 12),
  45                 .caps = MTK_SCPD_DOMAIN_SUPPLY,
  46         },
  47         [MT8183_POWER_DOMAIN_MFG_CORE0] = {
  48                 .name = "mfg_core0",
  49                 .sta_mask = BIT(7),
  50                 .ctl_offs = 0x034c,
  51                 .sram_pdn_bits = GENMASK(8, 8),
  52                 .sram_pdn_ack_bits = GENMASK(12, 12),
  53         },
  54         [MT8183_POWER_DOMAIN_MFG_CORE1] = {
  55                 .name = "mfg_core1",
  56                 .sta_mask = BIT(20),
  57                 .ctl_offs = 0x0310,
  58                 .sram_pdn_bits = GENMASK(8, 8),
  59                 .sram_pdn_ack_bits = GENMASK(12, 12),
  60         },
  61         [MT8183_POWER_DOMAIN_MFG_2D] = {
  62                 .name = "mfg_2d",
  63                 .sta_mask = PWR_STATUS_MFG_2D,
  64                 .ctl_offs = 0x0348,
  65                 .sram_pdn_bits = GENMASK(8, 8),
  66                 .sram_pdn_ack_bits = GENMASK(12, 12),
  67                 .bp_infracfg = {
  68                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
  69                                     MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
  70                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
  71                                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
  72                 },
  73         },
  74         [MT8183_POWER_DOMAIN_DISP] = {
  75                 .name = "disp",
  76                 .sta_mask = PWR_STATUS_DISP,
  77                 .ctl_offs = 0x030c,
  78                 .sram_pdn_bits = GENMASK(8, 8),
  79                 .sram_pdn_ack_bits = GENMASK(12, 12),
  80                 .bp_infracfg = {
  81                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
  82                                     MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
  83                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
  84                                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
  85                 },
  86                 .bp_smi = {
  87                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
  88                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
  89                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
  90                                     MT8183_SMI_COMMON_CLAMP_EN),
  91                 },
  92         },
  93         [MT8183_POWER_DOMAIN_CAM] = {
  94                 .name = "cam",
  95                 .sta_mask = BIT(25),
  96                 .ctl_offs = 0x0344,
  97                 .sram_pdn_bits = GENMASK(9, 8),
  98                 .sram_pdn_ack_bits = GENMASK(13, 12),
  99                 .bp_infracfg = {
 100                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
 101                                     MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
 102                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
 103                                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
 104                         BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
 105                                         MT8183_TOP_AXI_PROT_EN_MM_SET,
 106                                         MT8183_TOP_AXI_PROT_EN_MM_CLR,
 107                                         MT8183_TOP_AXI_PROT_EN_MM_STA1),
 108                 },
 109                 .bp_smi = {
 110                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
 111                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
 112                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
 113                                     MT8183_SMI_COMMON_CLAMP_EN),
 114                 },
 115         },
 116         [MT8183_POWER_DOMAIN_ISP] = {
 117                 .name = "isp",
 118                 .sta_mask = PWR_STATUS_ISP,
 119                 .ctl_offs = 0x0308,
 120                 .sram_pdn_bits = GENMASK(9, 8),
 121                 .sram_pdn_ack_bits = GENMASK(13, 12),
 122                 .bp_infracfg = {
 123                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
 124                                     MT8183_TOP_AXI_PROT_EN_MM_SET,
 125                                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
 126                                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
 127                         BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
 128                                         MT8183_TOP_AXI_PROT_EN_MM_SET,
 129                                         MT8183_TOP_AXI_PROT_EN_MM_CLR,
 130                                         MT8183_TOP_AXI_PROT_EN_MM_STA1),
 131                 },
 132                 .bp_smi = {
 133                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
 134                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
 135                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
 136                                     MT8183_SMI_COMMON_CLAMP_EN),
 137                 },
 138         },
 139         [MT8183_POWER_DOMAIN_VDEC] = {
 140                 .name = "vdec",
 141                 .sta_mask = BIT(31),
 142                 .ctl_offs = 0x0300,
 143                 .sram_pdn_bits = GENMASK(8, 8),
 144                 .sram_pdn_ack_bits = GENMASK(12, 12),
 145                 .bp_smi = {
 146                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
 147                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
 148                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
 149                                     MT8183_SMI_COMMON_CLAMP_EN),
 150                 },
 151         },
 152         [MT8183_POWER_DOMAIN_VENC] = {
 153                 .name = "venc",
 154                 .sta_mask = PWR_STATUS_VENC,
 155                 .ctl_offs = 0x0304,
 156                 .sram_pdn_bits = GENMASK(11, 8),
 157                 .sram_pdn_ack_bits = GENMASK(15, 12),
 158                 .bp_smi = {
 159                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
 160                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
 161                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
 162                                     MT8183_SMI_COMMON_CLAMP_EN),
 163                 },
 164         },
 165         [MT8183_POWER_DOMAIN_VPU_TOP] = {
 166                 .name = "vpu_top",
 167                 .sta_mask = BIT(26),
 168                 .ctl_offs = 0x0324,
 169                 .sram_pdn_bits = GENMASK(8, 8),
 170                 .sram_pdn_ack_bits = GENMASK(12, 12),
 171                 .bp_infracfg = {
 172                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
 173                                     MT8183_TOP_AXI_PROT_EN_MM_SET,
 174                                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
 175                                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
 176                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
 177                                     MT8183_TOP_AXI_PROT_EN_SET,
 178                                     MT8183_TOP_AXI_PROT_EN_CLR,
 179                                     MT8183_TOP_AXI_PROT_EN_STA1),
 180                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
 181                                     MT8183_TOP_AXI_PROT_EN_MM_SET,
 182                                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
 183                                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
 184                 },
 185                 .bp_smi = {
 186                         BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
 187                                     MT8183_SMI_COMMON_CLAMP_EN_SET,
 188                                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
 189                                     MT8183_SMI_COMMON_CLAMP_EN),
 190                 },
 191         },
 192         [MT8183_POWER_DOMAIN_VPU_CORE0] = {
 193                 .name = "vpu_core0",
 194                 .sta_mask = BIT(27),
 195                 .ctl_offs = 0x33c,
 196                 .sram_pdn_bits = GENMASK(11, 8),
 197                 .sram_pdn_ack_bits = GENMASK(13, 12),
 198                 .bp_infracfg = {
 199                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
 200                                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
 201                                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
 202                                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
 203                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
 204                                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
 205                                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
 206                                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
 207                 },
 208                 .caps = MTK_SCPD_SRAM_ISO,
 209         },
 210         [MT8183_POWER_DOMAIN_VPU_CORE1] = {
 211                 .name = "vpu_core1",
 212                 .sta_mask = BIT(28),
 213                 .ctl_offs = 0x0340,
 214                 .sram_pdn_bits = GENMASK(11, 8),
 215                 .sram_pdn_ack_bits = GENMASK(13, 12),
 216                 .bp_infracfg = {
 217                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
 218                                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
 219                                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
 220                                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
 221                         BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
 222                                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
 223                                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
 224                                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
 225                 },
 226                 .caps = MTK_SCPD_SRAM_ISO,
 227         },
 228 };
 229
 230 static const struct scpsys_soc_data mt8183_scpsys_data = {
 231         .domains_data = scpsys_domain_data_mt8183,
 232         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
 233         .pwr_sta_offs = 0x0180,
 234         .pwr_sta2nd_offs = 0x0184
 235 };
 236
 237 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */