drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
  27 #define __DAL_TIMING_GENERATOR_TYPES_H__
  28
  29 #include "hw_shared.h"
  30
  31 struct dc_bios;
  32
  33 /* Contains CRTC vertical/horizontal pixel counters */
  34 struct crtc_position {
  35         int32_t vertical_count;
  36         int32_t horizontal_count;
  37         int32_t nominal_vcount;
  38 };
  39
  40 struct dcp_gsl_params {
  41         int gsl_group;
  42         int gsl_master;
  43 };
  44
  45 struct gsl_params {
  46         int gsl0_en;
  47         int gsl1_en;
  48         int gsl2_en;
  49         int gsl_master_en;
  50         int gsl_master_mode;
  51         int master_update_lock_gsl_en;
  52         int gsl_window_start_x;
  53         int gsl_window_end_x;
  54         int gsl_window_start_y;
  55         int gsl_window_end_y;
  56 };
  57
  58 /* define the structure of Dynamic Refresh Mode */
  59 struct drr_params {
  60         uint32_t vertical_total_min;
  61         uint32_t vertical_total_max;
  62         uint32_t vertical_total_mid;
  63         uint32_t vertical_total_mid_frame_num;
  64         bool immediate_flip;
  65 };
  66
  67 struct long_vtotal_params {
  68         uint32_t vertical_total_min;
  69         uint32_t vertical_total_max;
  70         uint32_t vertical_blank_start;
  71 };
  72
  73 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
  74 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
  75
  76 enum crtc_state {
  77         CRTC_STATE_VBLANK = 0,
  78         CRTC_STATE_VACTIVE
  79 };
  80
  81 struct vupdate_keepout_params {
  82         int start_offset;
  83         int end_offset;
  84         int enable;
  85 };
  86
  87 struct crtc_stereo_flags {
  88         uint8_t PROGRAM_STEREO         : 1;
  89         uint8_t PROGRAM_POLARITY       : 1;
  90         uint8_t RIGHT_EYE_POLARITY     : 1;
  91         uint8_t FRAME_PACKED           : 1;
  92         uint8_t DISABLE_STEREO_DP_SYNC : 1;
  93 };
  94
  95 enum crc_selection {
  96         /* Order must match values expected by hardware */
  97         UNION_WINDOW_A_B = 0,
  98         UNION_WINDOW_A_NOT_B,
  99         UNION_WINDOW_NOT_A_B,
 100         UNION_WINDOW_NOT_A_NOT_B,
 101         INTERSECT_WINDOW_A_B,
 102         INTERSECT_WINDOW_A_NOT_B,
 103         INTERSECT_WINDOW_NOT_A_B,
 104         INTERSECT_WINDOW_NOT_A_NOT_B,
 105 };
 106
 107 enum otg_out_mux_dest {
 108         OUT_MUX_DIO = 0,
 109         OUT_MUX_HPO_DP = 2,
 110 };
 111
 112 enum h_timing_div_mode {
 113         H_TIMING_NO_DIV,
 114         H_TIMING_DIV_BY2,
 115         H_TIMING_RESERVED,
 116         H_TIMING_DIV_BY4,
 117 };
 118
 119 enum timing_synchronization_type {
 120         NOT_SYNCHRONIZABLE,
 121         TIMING_SYNCHRONIZABLE,
 122         VBLANK_SYNCHRONIZABLE
 123 };
 124
 125 struct crc_params {
 126         /* Regions used to calculate CRC*/
 127         uint16_t windowa_x_start;
 128         uint16_t windowa_x_end;
 129         uint16_t windowa_y_start;
 130         uint16_t windowa_y_end;
 131
 132         uint16_t windowb_x_start;
 133         uint16_t windowb_x_end;
 134         uint16_t windowb_y_start;
 135         uint16_t windowb_y_end;
 136
 137         enum crc_selection selection;
 138
 139         uint8_t dsc_mode;
 140         uint8_t odm_mode;
 141
 142         bool continuous_mode;
 143         bool enable;
 144 };
 145
 146 /**
 147  * struct timing_generator - Entry point to Output Timing Generator feature.
 148  */
 149 struct timing_generator {
 150         /**
 151          * @funcs: Timing generator control functions
 152          */
 153         const struct timing_generator_funcs *funcs;
 154         struct dc_bios *bp;
 155         struct dc_context *ctx;
 156         int inst;
 157 };
 158
 159 struct dc_crtc_timing;
 160
 161 struct drr_params;
 162
 163 /**
 164  * struct timing_generator_funcs - Control timing generator on a given device.
 165  */
 166 struct timing_generator_funcs {
 167         bool (*validate_timing)(struct timing_generator *tg,
 168                                                         const struct dc_crtc_timing *timing);
 169         void (*program_timing)(struct timing_generator *tg,
 170                                                         const struct dc_crtc_timing *timing,
 171                                                         int vready_offset,
 172                                                         int vstartup_start,
 173                                                         int vupdate_offset,
 174                                                         int vupdate_width,
 175                                                         int pstate_keepout,
 176                                                         const enum signal_type signal,
 177                                                         bool use_vbios
 178         );
 179         void (*setup_vertical_interrupt0)(
 180                         struct timing_generator *optc,
 181                         uint32_t start_line,
 182                         uint32_t end_line);
 183         void (*setup_vertical_interrupt1)(
 184                         struct timing_generator *optc,
 185                         uint32_t start_line);
 186         void (*setup_vertical_interrupt2)(
 187                         struct timing_generator *optc,
 188                         uint32_t start_line);
 189
 190         bool (*enable_crtc)(struct timing_generator *tg);
 191         bool (*disable_crtc)(struct timing_generator *tg);
 192         void (*phantom_crtc_post_enable)(struct timing_generator *tg);
 193         void (*disable_phantom_crtc)(struct timing_generator *tg);
 194         bool (*immediate_disable_crtc)(struct timing_generator *tg);
 195         bool (*is_counter_moving)(struct timing_generator *tg);
 196         void (*get_position)(struct timing_generator *tg,
 197                                 struct crtc_position *position);
 198
 199         uint32_t (*get_frame_count)(struct timing_generator *tg);
 200         void (*get_scanoutpos)(
 201                 struct timing_generator *tg,
 202                 uint32_t *v_blank_start,
 203                 uint32_t *v_blank_end,
 204                 uint32_t *h_position,
 205                 uint32_t *v_position);
 206         bool (*get_otg_active_size)(struct timing_generator *optc,
 207                         uint32_t *otg_active_width,
 208                         uint32_t *otg_active_height);
 209         bool (*is_matching_timing)(struct timing_generator *tg,
 210                         const struct dc_crtc_timing *otg_timing);
 211         void (*set_early_control)(struct timing_generator *tg,
 212                                                            uint32_t early_cntl);
 213         void (*wait_for_state)(struct timing_generator *tg,
 214                                                         enum crtc_state state);
 215         void (*set_blank)(struct timing_generator *tg,
 216                                         bool enable_blanking);
 217         bool (*is_blanked)(struct timing_generator *tg);
 218         void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
 219         void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
 220         void (*set_colors)(struct timing_generator *tg,
 221                                                 const struct tg_color *blank_color,
 222                                                 const struct tg_color *overscan_color);
 223
 224         void (*disable_vga)(struct timing_generator *tg);
 225         bool (*did_triggered_reset_occur)(struct timing_generator *tg);
 226         void (*setup_global_swap_lock)(struct timing_generator *tg,
 227                                                         const struct dcp_gsl_params *gsl_params);
 228         void (*unlock)(struct timing_generator *tg);
 229         void (*lock)(struct timing_generator *tg);
 230         void (*lock_doublebuffer_disable)(struct timing_generator *tg);
 231         void (*lock_doublebuffer_enable)(struct timing_generator *tg);
 232         void(*triplebuffer_unlock)(struct timing_generator *tg);
 233         void(*triplebuffer_lock)(struct timing_generator *tg);
 234         void (*enable_reset_trigger)(struct timing_generator *tg,
 235                                      int source_tg_inst);
 236         void (*enable_crtc_reset)(struct timing_generator *tg,
 237                                   int source_tg_inst,
 238                                   struct crtc_trigger_info *crtc_tp);
 239         void (*disable_reset_trigger)(struct timing_generator *tg);
 240         void (*tear_down_global_swap_lock)(struct timing_generator *tg);
 241         void (*enable_advanced_request)(struct timing_generator *tg,
 242                                         bool enable, const struct dc_crtc_timing *timing);
 243         void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
 244         void (*set_vtotal_min_max)(struct timing_generator *optc, int vtotal_min, int vtotal_max);
 245         void (*get_last_used_drr_vtotal)(struct timing_generator *optc, uint32_t *refresh_rate);
 246         void (*set_static_screen_control)(struct timing_generator *tg,
 247                                                 uint32_t event_triggers,
 248                                                 uint32_t num_frames);
 249         void (*set_test_pattern)(
 250                 struct timing_generator *tg,
 251                 enum controller_dp_test_pattern test_pattern,
 252                 enum dc_color_depth color_depth);
 253
 254         bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);
 255
 256         void (*program_global_sync)(struct timing_generator *tg,
 257                         int vready_offset,
 258                         int vstartup_start,
 259                         int vupdate_offset,
 260                         int vupdate_width,
 261                         int pstate_keepout);
 262         void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
 263         void (*program_stereo)(struct timing_generator *tg,
 264                 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
 265         bool (*is_stereo_left_eye)(struct timing_generator *tg);
 266
 267         void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);
 268
 269         void (*tg_init)(struct timing_generator *tg);
 270         bool (*is_tg_enabled)(struct timing_generator *tg);
 271         bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
 272         void (*clear_optc_underflow)(struct timing_generator *tg);
 273
 274         void (*set_dwb_source)(struct timing_generator *optc,
 275                 uint32_t dwb_pipe_inst);
 276
 277         void (*get_optc_source)(struct timing_generator *optc,
 278                         uint32_t *num_of_input_segments,
 279                         uint32_t *seg0_src_sel,
 280                         uint32_t *seg1_src_sel);
 281         bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing);
 282
 283         /**
 284          * Configure CRCs for the given timing generator. Return false if TG is
 285          * not on.
 286          */
 287         bool (*configure_crc)(struct timing_generator *tg,
 288                                const struct crc_params *params);
 289
 290         /**
 291          * @get_crc: Get CRCs for the given timing generator. Return false if
 292          * CRCs are not enabled (via configure_crc).
 293          */
 294         bool (*get_crc)(struct timing_generator *tg,
 295                         uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);
 296
 297         void (*program_manual_trigger)(struct timing_generator *optc);
 298         void (*setup_manual_trigger)(struct timing_generator *optc);
 299         bool (*get_hw_timing)(struct timing_generator *optc,
 300                         struct dc_crtc_timing *hw_crtc_timing);
 301
 302         void (*set_vtg_params)(struct timing_generator *optc,
 303                         const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
 304
 305         void (*set_dsc_config)(struct timing_generator *optc,
 306                                enum optc_dsc_mode dsc_mode,
 307                                uint32_t dsc_bytes_per_pixel,
 308                                uint32_t dsc_slice_width);
 309         void (*get_dsc_status)(struct timing_generator *optc,
 310                                         uint32_t *dsc_mode);
 311         void (*set_odm_bypass)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing);
 312
 313         /**
 314          * @set_odm_combine: Set up the ODM block to read from the correct
 315          * OPP(s) and turn on/off ODM memory.
 316          */
 317         void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
 318                         int segment_width, int last_segment_width);
 319         void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments);
 320         void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode);
 321         void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params);
 322         void (*set_gsl_source_select)(struct timing_generator *optc,
 323                         int group_idx,
 324                         uint32_t gsl_ready_signal);
 325         void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
 326         void (*set_drr_trigger_window)(struct timing_generator *optc,
 327                         uint32_t window_start, uint32_t window_end);
 328         void (*set_vtotal_change_limit)(struct timing_generator *optc,
 329                         uint32_t limit);
 330         void (*align_vblanks)(struct timing_generator *master_optc,
 331                         struct timing_generator *slave_optc,
 332                         uint32_t master_pixel_clock_100Hz,
 333                         uint32_t slave_pixel_clock_100Hz,
 334                         uint8_t master_clock_divider,
 335                         uint8_t slave_clock_divider);
 336         bool (*validate_vmin_vmax)(struct timing_generator *optc,
 337                         int vmin, int vmax);
 338         bool (*validate_vtotal_change_limit)(struct timing_generator *optc,
 339                         uint32_t vtotal_change_limit);
 340
 341         void (*init_odm)(struct timing_generator *tg);
 342         void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg);
 343         void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params);
 344         void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg);
 345         bool (*get_double_buffer_pending)(struct timing_generator *tg);
 346 };
 347
 348 #endif