drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <drm/drm_atomic_helper.h>
   4 #include <drm/drm_edid.h>
   5 #include <drm/drm_simple_kms_helper.h>
   6 #include <drm/drm_gem_framebuffer_helper.h>
   7 #include <drm/drm_vblank.h>
   8
   9 #include "amdgpu.h"
  10 #ifdef CONFIG_DRM_AMDGPU_SI
  11 #include "dce_v6_0.h"
  12 #endif
  13 #ifdef CONFIG_DRM_AMDGPU_CIK
  14 #include "dce_v8_0.h"
  15 #endif
  16 #include "dce_v10_0.h"
  17 #include "dce_v11_0.h"
  18 #include "ivsrcid/ivsrcid_vislands30.h"
  19 #include "amdgpu_vkms.h"
  20 #include "amdgpu_display.h"
  21 #include "atom.h"
  22 #include "amdgpu_irq.h"
  23
  24 /**
  25  * DOC: amdgpu_vkms
  26  *
  27  * The amdgpu vkms interface provides a virtual KMS interface for several use
  28  * cases: devices without display hardware, platforms where the actual display
  29  * hardware is not useful (e.g., servers), SR-IOV virtual functions, device
  30  * emulation/simulation, and device bring up prior to display hardware being
  31  * usable. We previously emulated a legacy KMS interface, but there was a desire
  32  * to move to the atomic KMS interface. The vkms driver did everything we
  33  * needed, but we wanted KMS support natively in the driver without buffer
  34  * sharing and the ability to support an instance of VKMS per device. We first
  35  * looked at splitting vkms into a stub driver and a helper module that other
  36  * drivers could use to implement a virtual display, but this strategy ended up
  37  * being messy due to driver specific callbacks needed for buffer management.
  38  * Ultimately, it proved easier to import the vkms code as it mostly used core
  39  * drm helpers anyway.
  40  */
  41
  42 static const u32 amdgpu_vkms_formats[] = {
  43         DRM_FORMAT_XRGB8888,
  44 };
  45
  46 static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
  47 {
  48         struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer);
  49         struct drm_crtc *crtc = &amdgpu_crtc->base;
  50         struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
  51         u64 ret_overrun;
  52         bool ret;
  53
  54         ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer,
  55                                           output->period_ns);
  56         if (ret_overrun != 1)
  57                 DRM_WARN("%s: vblank timer overrun\n", __func__);
  58
  59         ret = drm_crtc_handle_vblank(crtc);
  60         /* Don't queue timer again when vblank is disabled. */
  61         if (!ret)
  62                 return HRTIMER_NORESTART;
  63
  64         return HRTIMER_RESTART;
  65 }
  66
  67 static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
  68 {
  69         struct drm_device *dev = crtc->dev;
  70         unsigned int pipe = drm_crtc_index(crtc);
  71         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
  72         struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
  73         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  74
  75         drm_calc_timestamping_constants(crtc, &crtc->mode);
  76
  77         out->period_ns = ktime_set(0, vblank->framedur_ns);
  78         hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL);
  79
  80         return 0;
  81 }
  82
  83 static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc)
  84 {
  85         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  86
  87         hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer);
  88 }
  89
  90 static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,
  91                                              int *max_error,
  92                                              ktime_t *vblank_time,
  93                                              bool in_vblank_irq)
  94 {
  95         struct drm_device *dev = crtc->dev;
  96         unsigned int pipe = crtc->index;
  97         struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
  98         struct drm_vblank_crtc *vblank = &dev->vblank[pipe];
  99         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 100
 101         if (!READ_ONCE(vblank->enabled)) {
 102                 *vblank_time = ktime_get();
 103                 return true;
 104         }
 105
 106         *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires);
 107
 108         if (WARN_ON(*vblank_time == vblank->time))
 109                 return true;
 110
 111         /*
 112          * To prevent races we roll the hrtimer forward before we do any
 113          * interrupt processing - this is how real hw works (the interrupt is
 114          * only generated after all the vblank registers are updated) and what
 115          * the vblank core expects. Therefore we need to always correct the
 116          * timestampe by one frame.
 117          */
 118         *vblank_time -= output->period_ns;
 119
 120         return true;
 121 }
 122
 123 static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
 124         .set_config             = drm_atomic_helper_set_config,
 125         .destroy                = drm_crtc_cleanup,
 126         .page_flip              = drm_atomic_helper_page_flip,
 127         .reset                  = drm_atomic_helper_crtc_reset,
 128         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 129         .atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
 130         .enable_vblank          = amdgpu_vkms_enable_vblank,
 131         .disable_vblank         = amdgpu_vkms_disable_vblank,
 132         .get_vblank_timestamp   = amdgpu_vkms_get_vblank_timestamp,
 133 };
 134
 135 static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc,
 136                                            struct drm_atomic_state *state)
 137 {
 138         drm_crtc_vblank_on(crtc);
 139 }
 140
 141 static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc,
 142                                             struct drm_atomic_state *state)
 143 {
 144         drm_crtc_vblank_off(crtc);
 145 }
 146
 147 static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
 148                                           struct drm_atomic_state *state)
 149 {
 150         unsigned long flags;
 151         if (crtc->state->event) {
 152                 spin_lock_irqsave(&crtc->dev->event_lock, flags);
 153
 154                 if (drm_crtc_vblank_get(crtc) != 0)
 155                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
 156                 else
 157                         drm_crtc_arm_vblank_event(crtc, crtc->state->event);
 158
 159                 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
 160
 161                 crtc->state->event = NULL;
 162         }
 163 }
 164
 165 static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = {
 166         .atomic_flush   = amdgpu_vkms_crtc_atomic_flush,
 167         .atomic_enable  = amdgpu_vkms_crtc_atomic_enable,
 168         .atomic_disable = amdgpu_vkms_crtc_atomic_disable,
 169 };
 170
 171 static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
 172                           struct drm_plane *primary, struct drm_plane *cursor)
 173 {
 174         struct amdgpu_device *adev = drm_to_adev(dev);
 175         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
 176         int ret;
 177
 178         ret = drm_crtc_init_with_planes(dev, crtc, primary, cursor,
 179                                         &amdgpu_vkms_crtc_funcs, NULL);
 180         if (ret) {
 181                 DRM_ERROR("Failed to init CRTC\n");
 182                 return ret;
 183         }
 184
 185         drm_crtc_helper_add(crtc, &amdgpu_vkms_crtc_helper_funcs);
 186
 187         amdgpu_crtc->crtc_id = drm_crtc_index(crtc);
 188         adev->mode_info.crtcs[drm_crtc_index(crtc)] = amdgpu_crtc;
 189
 190         amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 191         amdgpu_crtc->encoder = NULL;
 192         amdgpu_crtc->connector = NULL;
 193         amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
 194
 195         hrtimer_init(&amdgpu_crtc->vblank_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
 196         amdgpu_crtc->vblank_timer.function = &amdgpu_vkms_vblank_simulate;
 197
 198         return ret;
 199 }
 200
 201 static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = {
 202         .fill_modes = drm_helper_probe_single_connector_modes,
 203         .destroy = drm_connector_cleanup,
 204         .reset = drm_atomic_helper_connector_reset,
 205         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 206         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 207 };
 208
 209 static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector)
 210 {
 211         struct drm_device *dev = connector->dev;
 212         struct drm_display_mode *mode = NULL;
 213         unsigned i;
 214         static const struct mode_size {
 215                 int w;
 216                 int h;
 217         } common_modes[] = {
 218                 { 640,  480},
 219                 { 720,  480},
 220                 { 800,  600},
 221                 { 848,  480},
 222                 {1024,  768},
 223                 {1152,  768},
 224                 {1280,  720},
 225                 {1280,  800},
 226                 {1280,  854},
 227                 {1280,  960},
 228                 {1280, 1024},
 229                 {1440,  900},
 230                 {1400, 1050},
 231                 {1680, 1050},
 232                 {1600, 1200},
 233                 {1920, 1080},
 234                 {1920, 1200},
 235                 {2560, 1440},
 236                 {4096, 3112},
 237                 {3656, 2664},
 238                 {3840, 2160},
 239                 {4096, 2160},
 240         };
 241
 242         for (i = 0; i < ARRAY_SIZE(common_modes); i++) {
 243                 mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
 244                 if (!mode)
 245                         continue;
 246                 drm_mode_probed_add(connector, mode);
 247         }
 248
 249         drm_set_preferred_mode(connector, XRES_DEF, YRES_DEF);
 250
 251         return ARRAY_SIZE(common_modes);
 252 }
 253
 254 static const struct drm_connector_helper_funcs amdgpu_vkms_conn_helper_funcs = {
 255         .get_modes    = amdgpu_vkms_conn_get_modes,
 256 };
 257
 258 static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = {
 259         .update_plane           = drm_atomic_helper_update_plane,
 260         .disable_plane          = drm_atomic_helper_disable_plane,
 261         .destroy                = drm_plane_cleanup,
 262         .reset                  = drm_atomic_helper_plane_reset,
 263         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 264         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 265 };
 266
 267 static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane,
 268                                             struct drm_atomic_state *old_state)
 269 {
 270         return;
 271 }
 272
 273 static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane,
 274                                           struct drm_atomic_state *state)
 275 {
 276         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 277                                                                                  plane);
 278         struct drm_crtc_state *crtc_state;
 279         int ret;
 280
 281         if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc))
 282                 return 0;
 283
 284         crtc_state = drm_atomic_get_crtc_state(state,
 285                                                new_plane_state->crtc);
 286         if (IS_ERR(crtc_state))
 287                 return PTR_ERR(crtc_state);
 288
 289         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 290                                                   DRM_PLANE_NO_SCALING,
 291                                                   DRM_PLANE_NO_SCALING,
 292                                                   false, true);
 293         if (ret != 0)
 294                 return ret;
 295
 296         /* for now primary plane must be visible and full screen */
 297         if (!new_plane_state->visible)
 298                 return -EINVAL;
 299
 300         return 0;
 301 }
 302
 303 static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,
 304                                   struct drm_plane_state *new_state)
 305 {
 306         struct amdgpu_framebuffer *afb;
 307         struct drm_gem_object *obj;
 308         struct amdgpu_device *adev;
 309         struct amdgpu_bo *rbo;
 310         uint32_t domain;
 311         int r;
 312
 313         if (!new_state->fb) {
 314                 DRM_DEBUG_KMS("No FB bound\n");
 315                 return 0;
 316         }
 317         afb = to_amdgpu_framebuffer(new_state->fb);
 318
 319         obj = drm_gem_fb_get_obj(new_state->fb, 0);
 320         if (!obj) {
 321                 DRM_ERROR("Failed to get obj from framebuffer\n");
 322                 return -EINVAL;
 323         }
 324
 325         rbo = gem_to_amdgpu_bo(obj);
 326         adev = amdgpu_ttm_adev(rbo->tbo.bdev);
 327
 328         r = amdgpu_bo_reserve(rbo, true);
 329         if (r) {
 330                 dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
 331                 return r;
 332         }
 333
 334         r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
 335         if (r) {
 336                 dev_err(adev->dev, "allocating fence slot failed (%d)\n", r);
 337                 goto error_unlock;
 338         }
 339
 340         if (plane->type != DRM_PLANE_TYPE_CURSOR)
 341                 domain = amdgpu_display_supported_domains(adev, rbo->flags);
 342         else
 343                 domain = AMDGPU_GEM_DOMAIN_VRAM;
 344
 345         r = amdgpu_bo_pin(rbo, domain);
 346         if (unlikely(r != 0)) {
 347                 if (r != -ERESTARTSYS)
 348                         DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
 349                 goto error_unlock;
 350         }
 351
 352         r = amdgpu_ttm_alloc_gart(&rbo->tbo);
 353         if (unlikely(r != 0)) {
 354                 DRM_ERROR("%p bind failed\n", rbo);
 355                 goto error_unpin;
 356         }
 357
 358         amdgpu_bo_unreserve(rbo);
 359
 360         afb->address = amdgpu_bo_gpu_offset(rbo);
 361
 362         amdgpu_bo_ref(rbo);
 363
 364         return 0;
 365
 366 error_unpin:
 367         amdgpu_bo_unpin(rbo);
 368
 369 error_unlock:
 370         amdgpu_bo_unreserve(rbo);
 371         return r;
 372 }
 373
 374 static void amdgpu_vkms_cleanup_fb(struct drm_plane *plane,
 375                                    struct drm_plane_state *old_state)
 376 {
 377         struct amdgpu_bo *rbo;
 378         struct drm_gem_object *obj;
 379         int r;
 380
 381         if (!old_state->fb)
 382                 return;
 383
 384         obj = drm_gem_fb_get_obj(old_state->fb, 0);
 385         if (!obj) {
 386                 DRM_ERROR("Failed to get obj from framebuffer\n");
 387                 return;
 388         }
 389
 390         rbo = gem_to_amdgpu_bo(obj);
 391         r = amdgpu_bo_reserve(rbo, false);
 392         if (unlikely(r)) {
 393                 DRM_ERROR("failed to reserve rbo before unpin\n");
 394                 return;
 395         }
 396
 397         amdgpu_bo_unpin(rbo);
 398         amdgpu_bo_unreserve(rbo);
 399         amdgpu_bo_unref(&rbo);
 400 }
 401
 402 static const struct drm_plane_helper_funcs amdgpu_vkms_primary_helper_funcs = {
 403         .atomic_update          = amdgpu_vkms_plane_atomic_update,
 404         .atomic_check           = amdgpu_vkms_plane_atomic_check,
 405         .prepare_fb             = amdgpu_vkms_prepare_fb,
 406         .cleanup_fb             = amdgpu_vkms_cleanup_fb,
 407 };
 408
 409 static struct drm_plane *amdgpu_vkms_plane_init(struct drm_device *dev,
 410                                                 enum drm_plane_type type,
 411                                                 int index)
 412 {
 413         struct drm_plane *plane;
 414         int ret;
 415
 416         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 417         if (!plane)
 418                 return ERR_PTR(-ENOMEM);
 419
 420         ret = drm_universal_plane_init(dev, plane, 1 << index,
 421                                        &amdgpu_vkms_plane_funcs,
 422                                        amdgpu_vkms_formats,
 423                                        ARRAY_SIZE(amdgpu_vkms_formats),
 424                                        NULL, type, NULL);
 425         if (ret) {
 426                 kfree(plane);
 427                 return ERR_PTR(ret);
 428         }
 429
 430         drm_plane_helper_add(plane, &amdgpu_vkms_primary_helper_funcs);
 431
 432         return plane;
 433 }
 434
 435 static int amdgpu_vkms_output_init(struct drm_device *dev, struct
 436                                    amdgpu_vkms_output *output, int index)
 437 {
 438         struct drm_connector *connector = &output->connector;
 439         struct drm_encoder *encoder = &output->encoder;
 440         struct drm_crtc *crtc = &output->crtc.base;
 441         struct drm_plane *primary, *cursor = NULL;
 442         int ret;
 443
 444         primary = amdgpu_vkms_plane_init(dev, DRM_PLANE_TYPE_PRIMARY, index);
 445         if (IS_ERR(primary))
 446                 return PTR_ERR(primary);
 447
 448         ret = amdgpu_vkms_crtc_init(dev, crtc, primary, cursor);
 449         if (ret)
 450                 goto err_crtc;
 451
 452         ret = drm_connector_init(dev, connector, &amdgpu_vkms_connector_funcs,
 453                                  DRM_MODE_CONNECTOR_VIRTUAL);
 454         if (ret) {
 455                 DRM_ERROR("Failed to init connector\n");
 456                 goto err_connector;
 457         }
 458
 459         drm_connector_helper_add(connector, &amdgpu_vkms_conn_helper_funcs);
 460
 461         ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_VIRTUAL);
 462         if (ret) {
 463                 DRM_ERROR("Failed to init encoder\n");
 464                 goto err_encoder;
 465         }
 466         encoder->possible_crtcs = 1 << index;
 467
 468         ret = drm_connector_attach_encoder(connector, encoder);
 469         if (ret) {
 470                 DRM_ERROR("Failed to attach connector to encoder\n");
 471                 goto err_attach;
 472         }
 473
 474         drm_mode_config_reset(dev);
 475
 476         return 0;
 477
 478 err_attach:
 479         drm_encoder_cleanup(encoder);
 480
 481 err_encoder:
 482         drm_connector_cleanup(connector);
 483
 484 err_connector:
 485         drm_crtc_cleanup(crtc);
 486
 487 err_crtc:
 488         drm_plane_cleanup(primary);
 489
 490         return ret;
 491 }
 492
 493 const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = {
 494         .fb_create = amdgpu_display_user_framebuffer_create,
 495         .atomic_check = drm_atomic_helper_check,
 496         .atomic_commit = drm_atomic_helper_commit,
 497 };
 498
 499 static int amdgpu_vkms_sw_init(void *handle)
 500 {
 501         int r, i;
 502         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 503
 504         adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc,
 505                 sizeof(struct amdgpu_vkms_output), GFP_KERNEL);
 506         if (!adev->amdgpu_vkms_output)
 507                 return -ENOMEM;
 508
 509         adev_to_drm(adev)->max_vblank_count = 0;
 510
 511         adev_to_drm(adev)->mode_config.funcs = &amdgpu_vkms_mode_funcs;
 512
 513         adev_to_drm(adev)->mode_config.max_width = XRES_MAX;
 514         adev_to_drm(adev)->mode_config.max_height = YRES_MAX;
 515
 516         adev_to_drm(adev)->mode_config.preferred_depth = 24;
 517         adev_to_drm(adev)->mode_config.prefer_shadow = 1;
 518
 519         adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
 520
 521         r = amdgpu_display_modeset_create_props(adev);
 522         if (r)
 523                 return r;
 524
 525         /* allocate crtcs, encoders, connectors */
 526         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 527                 r = amdgpu_vkms_output_init(adev_to_drm(adev), &adev->amdgpu_vkms_output[i], i);
 528                 if (r)
 529                         return r;
 530         }
 531
 532         r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
 533         if (r)
 534                 return r;
 535
 536         drm_kms_helper_poll_init(adev_to_drm(adev));
 537
 538         adev->mode_info.mode_config_initialized = true;
 539         return 0;
 540 }
 541
 542 static int amdgpu_vkms_sw_fini(void *handle)
 543 {
 544         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 545         int i = 0;
 546
 547         for (i = 0; i < adev->mode_info.num_crtc; i++)
 548                 if (adev->mode_info.crtcs[i])
 549                         hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
 550
 551         drm_kms_helper_poll_fini(adev_to_drm(adev));
 552         drm_mode_config_cleanup(adev_to_drm(adev));
 553
 554         adev->mode_info.mode_config_initialized = false;
 555
 556         kfree(adev->mode_info.bios_hardcoded_edid);
 557         kfree(adev->amdgpu_vkms_output);
 558         return 0;
 559 }
 560
 561 static int amdgpu_vkms_hw_init(void *handle)
 562 {
 563         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 564
 565         switch (adev->asic_type) {
 566 #ifdef CONFIG_DRM_AMDGPU_SI
 567         case CHIP_TAHITI:
 568         case CHIP_PITCAIRN:
 569         case CHIP_VERDE:
 570         case CHIP_OLAND:
 571                 dce_v6_0_disable_dce(adev);
 572                 break;
 573 #endif
 574 #ifdef CONFIG_DRM_AMDGPU_CIK
 575         case CHIP_BONAIRE:
 576         case CHIP_HAWAII:
 577         case CHIP_KAVERI:
 578         case CHIP_KABINI:
 579         case CHIP_MULLINS:
 580                 dce_v8_0_disable_dce(adev);
 581                 break;
 582 #endif
 583         case CHIP_FIJI:
 584         case CHIP_TONGA:
 585                 dce_v10_0_disable_dce(adev);
 586                 break;
 587         case CHIP_CARRIZO:
 588         case CHIP_STONEY:
 589         case CHIP_POLARIS10:
 590         case CHIP_POLARIS11:
 591         case CHIP_VEGAM:
 592                 dce_v11_0_disable_dce(adev);
 593                 break;
 594         case CHIP_TOPAZ:
 595 #ifdef CONFIG_DRM_AMDGPU_SI
 596         case CHIP_HAINAN:
 597 #endif
 598                 /* no DCE */
 599                 break;
 600         default:
 601                 break;
 602         }
 603         return 0;
 604 }
 605
 606 static int amdgpu_vkms_hw_fini(void *handle)
 607 {
 608         return 0;
 609 }
 610
 611 static int amdgpu_vkms_suspend(void *handle)
 612 {
 613         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 614         int r;
 615
 616         r = drm_mode_config_helper_suspend(adev_to_drm(adev));
 617         if (r)
 618                 return r;
 619         return amdgpu_vkms_hw_fini(handle);
 620 }
 621
 622 static int amdgpu_vkms_resume(void *handle)
 623 {
 624         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 625         int r;
 626
 627         r = amdgpu_vkms_hw_init(handle);
 628         if (r)
 629                 return r;
 630         return drm_mode_config_helper_resume(adev_to_drm(adev));
 631 }
 632
 633 static bool amdgpu_vkms_is_idle(void *handle)
 634 {
 635         return true;
 636 }
 637
 638 static int amdgpu_vkms_wait_for_idle(void *handle)
 639 {
 640         return 0;
 641 }
 642
 643 static int amdgpu_vkms_soft_reset(void *handle)
 644 {
 645         return 0;
 646 }
 647
 648 static int amdgpu_vkms_set_clockgating_state(void *handle,
 649                                           enum amd_clockgating_state state)
 650 {
 651         return 0;
 652 }
 653
 654 static int amdgpu_vkms_set_powergating_state(void *handle,
 655                                           enum amd_powergating_state state)
 656 {
 657         return 0;
 658 }
 659
 660 static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = {
 661         .name = "amdgpu_vkms",
 662         .early_init = NULL,
 663         .late_init = NULL,
 664         .sw_init = amdgpu_vkms_sw_init,
 665         .sw_fini = amdgpu_vkms_sw_fini,
 666         .hw_init = amdgpu_vkms_hw_init,
 667         .hw_fini = amdgpu_vkms_hw_fini,
 668         .suspend = amdgpu_vkms_suspend,
 669         .resume = amdgpu_vkms_resume,
 670         .is_idle = amdgpu_vkms_is_idle,
 671         .wait_for_idle = amdgpu_vkms_wait_for_idle,
 672         .soft_reset = amdgpu_vkms_soft_reset,
 673         .set_clockgating_state = amdgpu_vkms_set_clockgating_state,
 674         .set_powergating_state = amdgpu_vkms_set_powergating_state,
 675         .dump_ip_state = NULL,
 676         .print_ip_state = NULL,
 677 };
 678
 679 const struct amdgpu_ip_block_version amdgpu_vkms_ip_block = {
 680         .type = AMD_IP_BLOCK_TYPE_DCE,
 681         .major = 1,
 682         .minor = 0,
 683         .rev = 0,
 684         .funcs = &amdgpu_vkms_ip_funcs,
 685 };
 686