drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <linux/pci.h>
  26
  27 #include <drm/drm_cache.h>
  28
  29 #include "amdgpu.h"
  30 #include "gmc_v9_0.h"
  31 #include "amdgpu_atomfirmware.h"
  32 #include "amdgpu_gem.h"
  33
  34 #include "gc/gc_9_0_sh_mask.h"
  35 #include "dce/dce_12_0_offset.h"
  36 #include "dce/dce_12_0_sh_mask.h"
  37 #include "vega10_enum.h"
  38 #include "mmhub/mmhub_1_0_offset.h"
  39 #include "athub/athub_1_0_sh_mask.h"
  40 #include "athub/athub_1_0_offset.h"
  41 #include "oss/osssys_4_0_offset.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "umc/umc_6_0_sh_mask.h"
  47
  48 #include "gfxhub_v1_0.h"
  49 #include "mmhub_v1_0.h"
  50 #include "athub_v1_0.h"
  51 #include "gfxhub_v1_1.h"
  52 #include "gfxhub_v1_2.h"
  53 #include "mmhub_v9_4.h"
  54 #include "mmhub_v1_7.h"
  55 #include "mmhub_v1_8.h"
  56 #include "umc_v6_1.h"
  57 #include "umc_v6_0.h"
  58 #include "umc_v6_7.h"
  59 #include "umc_v12_0.h"
  60 #include "hdp_v4_0.h"
  61 #include "mca_v3_0.h"
  62
  63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  64
  65 #include "amdgpu_ras.h"
  66 #include "amdgpu_xgmi.h"
  67
  68 /* add these here since we already include dce12 headers and these are for DCN */
  69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
  75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0                                                                  0x049d
  76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX                                                         2
  77
  78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2                                                          0x05ea
  79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX                                                 2
  80
  81 #define MAX_MEM_RANGES 8
  82
  83 static const char * const gfxhub_client_ids[] = {
  84         "CB",
  85         "DB",
  86         "IA",
  87         "WD",
  88         "CPF",
  89         "CPC",
  90         "CPG",
  91         "RLC",
  92         "TCP",
  93         "SQC (inst)",
  94         "SQC (data)",
  95         "SQG",
  96         "PA",
  97 };
  98
  99 static const char *mmhub_client_ids_raven[][2] = {
 100         [0][0] = "MP1",
 101         [1][0] = "MP0",
 102         [2][0] = "VCN",
 103         [3][0] = "VCNU",
 104         [4][0] = "HDP",
 105         [5][0] = "DCE",
 106         [13][0] = "UTCL2",
 107         [19][0] = "TLS",
 108         [26][0] = "OSS",
 109         [27][0] = "SDMA0",
 110         [0][1] = "MP1",
 111         [1][1] = "MP0",
 112         [2][1] = "VCN",
 113         [3][1] = "VCNU",
 114         [4][1] = "HDP",
 115         [5][1] = "XDP",
 116         [6][1] = "DBGU0",
 117         [7][1] = "DCE",
 118         [8][1] = "DCEDWB0",
 119         [9][1] = "DCEDWB1",
 120         [26][1] = "OSS",
 121         [27][1] = "SDMA0",
 122 };
 123
 124 static const char *mmhub_client_ids_renoir[][2] = {
 125         [0][0] = "MP1",
 126         [1][0] = "MP0",
 127         [2][0] = "HDP",
 128         [4][0] = "DCEDMC",
 129         [5][0] = "DCEVGA",
 130         [13][0] = "UTCL2",
 131         [19][0] = "TLS",
 132         [26][0] = "OSS",
 133         [27][0] = "SDMA0",
 134         [28][0] = "VCN",
 135         [29][0] = "VCNU",
 136         [30][0] = "JPEG",
 137         [0][1] = "MP1",
 138         [1][1] = "MP0",
 139         [2][1] = "HDP",
 140         [3][1] = "XDP",
 141         [6][1] = "DBGU0",
 142         [7][1] = "DCEDMC",
 143         [8][1] = "DCEVGA",
 144         [9][1] = "DCEDWB",
 145         [26][1] = "OSS",
 146         [27][1] = "SDMA0",
 147         [28][1] = "VCN",
 148         [29][1] = "VCNU",
 149         [30][1] = "JPEG",
 150 };
 151
 152 static const char *mmhub_client_ids_vega10[][2] = {
 153         [0][0] = "MP0",
 154         [1][0] = "UVD",
 155         [2][0] = "UVDU",
 156         [3][0] = "HDP",
 157         [13][0] = "UTCL2",
 158         [14][0] = "OSS",
 159         [15][0] = "SDMA1",
 160         [32+0][0] = "VCE0",
 161         [32+1][0] = "VCE0U",
 162         [32+2][0] = "XDMA",
 163         [32+3][0] = "DCE",
 164         [32+4][0] = "MP1",
 165         [32+14][0] = "SDMA0",
 166         [0][1] = "MP0",
 167         [1][1] = "UVD",
 168         [2][1] = "UVDU",
 169         [3][1] = "DBGU0",
 170         [4][1] = "HDP",
 171         [5][1] = "XDP",
 172         [14][1] = "OSS",
 173         [15][1] = "SDMA0",
 174         [32+0][1] = "VCE0",
 175         [32+1][1] = "VCE0U",
 176         [32+2][1] = "XDMA",
 177         [32+3][1] = "DCE",
 178         [32+4][1] = "DCEDWB",
 179         [32+5][1] = "MP1",
 180         [32+6][1] = "DBGU1",
 181         [32+14][1] = "SDMA1",
 182 };
 183
 184 static const char *mmhub_client_ids_vega12[][2] = {
 185         [0][0] = "MP0",
 186         [1][0] = "VCE0",
 187         [2][0] = "VCE0U",
 188         [3][0] = "HDP",
 189         [13][0] = "UTCL2",
 190         [14][0] = "OSS",
 191         [15][0] = "SDMA1",
 192         [32+0][0] = "DCE",
 193         [32+1][0] = "XDMA",
 194         [32+2][0] = "UVD",
 195         [32+3][0] = "UVDU",
 196         [32+4][0] = "MP1",
 197         [32+15][0] = "SDMA0",
 198         [0][1] = "MP0",
 199         [1][1] = "VCE0",
 200         [2][1] = "VCE0U",
 201         [3][1] = "DBGU0",
 202         [4][1] = "HDP",
 203         [5][1] = "XDP",
 204         [14][1] = "OSS",
 205         [15][1] = "SDMA0",
 206         [32+0][1] = "DCE",
 207         [32+1][1] = "DCEDWB",
 208         [32+2][1] = "XDMA",
 209         [32+3][1] = "UVD",
 210         [32+4][1] = "UVDU",
 211         [32+5][1] = "MP1",
 212         [32+6][1] = "DBGU1",
 213         [32+15][1] = "SDMA1",
 214 };
 215
 216 static const char *mmhub_client_ids_vega20[][2] = {
 217         [0][0] = "XDMA",
 218         [1][0] = "DCE",
 219         [2][0] = "VCE0",
 220         [3][0] = "VCE0U",
 221         [4][0] = "UVD",
 222         [5][0] = "UVD1U",
 223         [13][0] = "OSS",
 224         [14][0] = "HDP",
 225         [15][0] = "SDMA0",
 226         [32+0][0] = "UVD",
 227         [32+1][0] = "UVDU",
 228         [32+2][0] = "MP1",
 229         [32+3][0] = "MP0",
 230         [32+12][0] = "UTCL2",
 231         [32+14][0] = "SDMA1",
 232         [0][1] = "XDMA",
 233         [1][1] = "DCE",
 234         [2][1] = "DCEDWB",
 235         [3][1] = "VCE0",
 236         [4][1] = "VCE0U",
 237         [5][1] = "UVD1",
 238         [6][1] = "UVD1U",
 239         [7][1] = "DBGU0",
 240         [8][1] = "XDP",
 241         [13][1] = "OSS",
 242         [14][1] = "HDP",
 243         [15][1] = "SDMA0",
 244         [32+0][1] = "UVD",
 245         [32+1][1] = "UVDU",
 246         [32+2][1] = "DBGU1",
 247         [32+3][1] = "MP1",
 248         [32+4][1] = "MP0",
 249         [32+14][1] = "SDMA1",
 250 };
 251
 252 static const char *mmhub_client_ids_arcturus[][2] = {
 253         [0][0] = "DBGU1",
 254         [1][0] = "XDP",
 255         [2][0] = "MP1",
 256         [14][0] = "HDP",
 257         [171][0] = "JPEG",
 258         [172][0] = "VCN",
 259         [173][0] = "VCNU",
 260         [203][0] = "JPEG1",
 261         [204][0] = "VCN1",
 262         [205][0] = "VCN1U",
 263         [256][0] = "SDMA0",
 264         [257][0] = "SDMA1",
 265         [258][0] = "SDMA2",
 266         [259][0] = "SDMA3",
 267         [260][0] = "SDMA4",
 268         [261][0] = "SDMA5",
 269         [262][0] = "SDMA6",
 270         [263][0] = "SDMA7",
 271         [384][0] = "OSS",
 272         [0][1] = "DBGU1",
 273         [1][1] = "XDP",
 274         [2][1] = "MP1",
 275         [14][1] = "HDP",
 276         [171][1] = "JPEG",
 277         [172][1] = "VCN",
 278         [173][1] = "VCNU",
 279         [203][1] = "JPEG1",
 280         [204][1] = "VCN1",
 281         [205][1] = "VCN1U",
 282         [256][1] = "SDMA0",
 283         [257][1] = "SDMA1",
 284         [258][1] = "SDMA2",
 285         [259][1] = "SDMA3",
 286         [260][1] = "SDMA4",
 287         [261][1] = "SDMA5",
 288         [262][1] = "SDMA6",
 289         [263][1] = "SDMA7",
 290         [384][1] = "OSS",
 291 };
 292
 293 static const char *mmhub_client_ids_aldebaran[][2] = {
 294         [2][0] = "MP1",
 295         [3][0] = "MP0",
 296         [32+1][0] = "DBGU_IO0",
 297         [32+2][0] = "DBGU_IO2",
 298         [32+4][0] = "MPIO",
 299         [96+11][0] = "JPEG0",
 300         [96+12][0] = "VCN0",
 301         [96+13][0] = "VCNU0",
 302         [128+11][0] = "JPEG1",
 303         [128+12][0] = "VCN1",
 304         [128+13][0] = "VCNU1",
 305         [160+1][0] = "XDP",
 306         [160+14][0] = "HDP",
 307         [256+0][0] = "SDMA0",
 308         [256+1][0] = "SDMA1",
 309         [256+2][0] = "SDMA2",
 310         [256+3][0] = "SDMA3",
 311         [256+4][0] = "SDMA4",
 312         [384+0][0] = "OSS",
 313         [2][1] = "MP1",
 314         [3][1] = "MP0",
 315         [32+1][1] = "DBGU_IO0",
 316         [32+2][1] = "DBGU_IO2",
 317         [32+4][1] = "MPIO",
 318         [96+11][1] = "JPEG0",
 319         [96+12][1] = "VCN0",
 320         [96+13][1] = "VCNU0",
 321         [128+11][1] = "JPEG1",
 322         [128+12][1] = "VCN1",
 323         [128+13][1] = "VCNU1",
 324         [160+1][1] = "XDP",
 325         [160+14][1] = "HDP",
 326         [256+0][1] = "SDMA0",
 327         [256+1][1] = "SDMA1",
 328         [256+2][1] = "SDMA2",
 329         [256+3][1] = "SDMA3",
 330         [256+4][1] = "SDMA4",
 331         [384+0][1] = "OSS",
 332 };
 333
 334 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
 335         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
 336         SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
 337 };
 338
 339 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
 340         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
 341         SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
 342 };
 343
 344 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
 345         (0x000143c0 + 0x00000000),
 346         (0x000143c0 + 0x00000800),
 347         (0x000143c0 + 0x00001000),
 348         (0x000143c0 + 0x00001800),
 349         (0x000543c0 + 0x00000000),
 350         (0x000543c0 + 0x00000800),
 351         (0x000543c0 + 0x00001000),
 352         (0x000543c0 + 0x00001800),
 353         (0x000943c0 + 0x00000000),
 354         (0x000943c0 + 0x00000800),
 355         (0x000943c0 + 0x00001000),
 356         (0x000943c0 + 0x00001800),
 357         (0x000d43c0 + 0x00000000),
 358         (0x000d43c0 + 0x00000800),
 359         (0x000d43c0 + 0x00001000),
 360         (0x000d43c0 + 0x00001800),
 361         (0x001143c0 + 0x00000000),
 362         (0x001143c0 + 0x00000800),
 363         (0x001143c0 + 0x00001000),
 364         (0x001143c0 + 0x00001800),
 365         (0x001543c0 + 0x00000000),
 366         (0x001543c0 + 0x00000800),
 367         (0x001543c0 + 0x00001000),
 368         (0x001543c0 + 0x00001800),
 369         (0x001943c0 + 0x00000000),
 370         (0x001943c0 + 0x00000800),
 371         (0x001943c0 + 0x00001000),
 372         (0x001943c0 + 0x00001800),
 373         (0x001d43c0 + 0x00000000),
 374         (0x001d43c0 + 0x00000800),
 375         (0x001d43c0 + 0x00001000),
 376         (0x001d43c0 + 0x00001800),
 377 };
 378
 379 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 380         (0x000143e0 + 0x00000000),
 381         (0x000143e0 + 0x00000800),
 382         (0x000143e0 + 0x00001000),
 383         (0x000143e0 + 0x00001800),
 384         (0x000543e0 + 0x00000000),
 385         (0x000543e0 + 0x00000800),
 386         (0x000543e0 + 0x00001000),
 387         (0x000543e0 + 0x00001800),
 388         (0x000943e0 + 0x00000000),
 389         (0x000943e0 + 0x00000800),
 390         (0x000943e0 + 0x00001000),
 391         (0x000943e0 + 0x00001800),
 392         (0x000d43e0 + 0x00000000),
 393         (0x000d43e0 + 0x00000800),
 394         (0x000d43e0 + 0x00001000),
 395         (0x000d43e0 + 0x00001800),
 396         (0x001143e0 + 0x00000000),
 397         (0x001143e0 + 0x00000800),
 398         (0x001143e0 + 0x00001000),
 399         (0x001143e0 + 0x00001800),
 400         (0x001543e0 + 0x00000000),
 401         (0x001543e0 + 0x00000800),
 402         (0x001543e0 + 0x00001000),
 403         (0x001543e0 + 0x00001800),
 404         (0x001943e0 + 0x00000000),
 405         (0x001943e0 + 0x00000800),
 406         (0x001943e0 + 0x00001000),
 407         (0x001943e0 + 0x00001800),
 408         (0x001d43e0 + 0x00000000),
 409         (0x001d43e0 + 0x00000800),
 410         (0x001d43e0 + 0x00001000),
 411         (0x001d43e0 + 0x00001800),
 412 };
 413
 414 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 415                 struct amdgpu_irq_src *src,
 416                 unsigned int type,
 417                 enum amdgpu_interrupt_state state)
 418 {
 419         u32 bits, i, tmp, reg;
 420
 421         /* Devices newer then VEGA10/12 shall have these programming
 422          * sequences performed by PSP BL
 423          */
 424         if (adev->asic_type >= CHIP_VEGA20)
 425                 return 0;
 426
 427         bits = 0x7f;
 428
 429         switch (state) {
 430         case AMDGPU_IRQ_STATE_DISABLE:
 431                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 432                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 433                         tmp = RREG32(reg);
 434                         tmp &= ~bits;
 435                         WREG32(reg, tmp);
 436                 }
 437                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 438                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 439                         tmp = RREG32(reg);
 440                         tmp &= ~bits;
 441                         WREG32(reg, tmp);
 442                 }
 443                 break;
 444         case AMDGPU_IRQ_STATE_ENABLE:
 445                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 446                         reg = ecc_umc_mcumc_ctrl_addrs[i];
 447                         tmp = RREG32(reg);
 448                         tmp |= bits;
 449                         WREG32(reg, tmp);
 450                 }
 451                 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 452                         reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 453                         tmp = RREG32(reg);
 454                         tmp |= bits;
 455                         WREG32(reg, tmp);
 456                 }
 457                 break;
 458         default:
 459                 break;
 460         }
 461
 462         return 0;
 463 }
 464
 465 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 466                                         struct amdgpu_irq_src *src,
 467                                         unsigned int type,
 468                                         enum amdgpu_interrupt_state state)
 469 {
 470         struct amdgpu_vmhub *hub;
 471         u32 tmp, reg, bits, i, j;
 472
 473         bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 474                 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 475                 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 476                 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 477                 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 478                 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 479                 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 480
 481         switch (state) {
 482         case AMDGPU_IRQ_STATE_DISABLE:
 483                 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
 484                         hub = &adev->vmhub[j];
 485                         for (i = 0; i < 16; i++) {
 486                                 reg = hub->vm_context0_cntl + i;
 487
 488                                 /* This works because this interrupt is only
 489                                  * enabled at init/resume and disabled in
 490                                  * fini/suspend, so the overall state doesn't
 491                                  * change over the course of suspend/resume.
 492                                  */
 493                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
 494                                         continue;
 495
 496                                 if (j >= AMDGPU_MMHUB0(0))
 497                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 498                                 else
 499                                         tmp = RREG32_XCC(reg, j);
 500
 501                                 tmp &= ~bits;
 502
 503                                 if (j >= AMDGPU_MMHUB0(0))
 504                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 505                                 else
 506                                         WREG32_XCC(reg, tmp, j);
 507                         }
 508                 }
 509                 break;
 510         case AMDGPU_IRQ_STATE_ENABLE:
 511                 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
 512                         hub = &adev->vmhub[j];
 513                         for (i = 0; i < 16; i++) {
 514                                 reg = hub->vm_context0_cntl + i;
 515
 516                                 /* This works because this interrupt is only
 517                                  * enabled at init/resume and disabled in
 518                                  * fini/suspend, so the overall state doesn't
 519                                  * change over the course of suspend/resume.
 520                                  */
 521                                 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
 522                                         continue;
 523
 524                                 if (j >= AMDGPU_MMHUB0(0))
 525                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
 526                                 else
 527                                         tmp = RREG32_XCC(reg, j);
 528
 529                                 tmp |= bits;
 530
 531                                 if (j >= AMDGPU_MMHUB0(0))
 532                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
 533                                 else
 534                                         WREG32_XCC(reg, tmp, j);
 535                         }
 536                 }
 537                 break;
 538         default:
 539                 break;
 540         }
 541
 542         return 0;
 543 }
 544
 545 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 546                                       struct amdgpu_irq_src *source,
 547                                       struct amdgpu_iv_entry *entry)
 548 {
 549         bool retry_fault = !!(entry->src_data[1] & 0x80);
 550         bool write_fault = !!(entry->src_data[1] & 0x20);
 551         uint32_t status = 0, cid = 0, rw = 0, fed = 0;
 552         struct amdgpu_task_info *task_info;
 553         struct amdgpu_vmhub *hub;
 554         const char *mmhub_cid;
 555         const char *hub_name;
 556         unsigned int vmhub;
 557         u64 addr;
 558         uint32_t cam_index = 0;
 559         int ret, xcc_id = 0;
 560         uint32_t node_id;
 561
 562         node_id = entry->node_id;
 563
 564         addr = (u64)entry->src_data[0] << 12;
 565         addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 566
 567         if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 568                 hub_name = "mmhub0";
 569                 vmhub = AMDGPU_MMHUB0(node_id / 4);
 570         } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 571                 hub_name = "mmhub1";
 572                 vmhub = AMDGPU_MMHUB1(0);
 573         } else {
 574                 hub_name = "gfxhub0";
 575                 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
 576                         xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
 577                                 node_id);
 578                         if (xcc_id < 0)
 579                                 xcc_id = 0;
 580                 }
 581                 vmhub = xcc_id;
 582         }
 583         hub = &adev->vmhub[vmhub];
 584
 585         if (retry_fault) {
 586                 if (adev->irq.retry_cam_enabled) {
 587                         /* Delegate it to a different ring if the hardware hasn't
 588                          * already done it.
 589                          */
 590                         if (entry->ih == &adev->irq.ih) {
 591                                 amdgpu_irq_delegate(adev, entry, 8);
 592                                 return 1;
 593                         }
 594
 595                         cam_index = entry->src_data[2] & 0x3ff;
 596
 597                         ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
 598                                                      addr, write_fault);
 599                         WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
 600                         if (ret)
 601                                 return 1;
 602                 } else {
 603                         /* Process it onyl if it's the first fault for this address */
 604                         if (entry->ih != &adev->irq.ih_soft &&
 605                             amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
 606                                              entry->timestamp))
 607                                 return 1;
 608
 609                         /* Delegate it to a different ring if the hardware hasn't
 610                          * already done it.
 611                          */
 612                         if (entry->ih == &adev->irq.ih) {
 613                                 amdgpu_irq_delegate(adev, entry, 8);
 614                                 return 1;
 615                         }
 616
 617                         /* Try to handle the recoverable page faults by filling page
 618                          * tables
 619                          */
 620                         if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
 621                                                    addr, write_fault))
 622                                 return 1;
 623                 }
 624         }
 625
 626         if (!printk_ratelimit())
 627                 return 0;
 628
 629         dev_err(adev->dev,
 630                 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
 631                 retry_fault ? "retry" : "no-retry",
 632                 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
 633
 634         task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
 635         if (task_info) {
 636                 dev_err(adev->dev,
 637                         " for process %s pid %d thread %s pid %d)\n",
 638                         task_info->process_name, task_info->tgid,
 639                         task_info->task_name, task_info->pid);
 640                 amdgpu_vm_put_task_info(task_info);
 641         }
 642
 643         dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
 644                 addr, entry->client_id,
 645                 soc15_ih_clientid_name[entry->client_id]);
 646
 647         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
 648                 dev_err(adev->dev, "  cookie node_id %d fault from die %s%d%s\n",
 649                         node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
 650                         node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
 651
 652         if (amdgpu_sriov_vf(adev))
 653                 return 0;
 654
 655         /*
 656          * Issue a dummy read to wait for the status register to
 657          * be updated to avoid reading an incorrect value due to
 658          * the new fast GRBM interface.
 659          */
 660         if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
 661             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
 662                 RREG32(hub->vm_l2_pro_fault_status);
 663
 664         status = RREG32(hub->vm_l2_pro_fault_status);
 665         cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
 666         rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
 667         fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
 668
 669         /* for fed error, kfd will handle it, return directly */
 670         if (fed && amdgpu_ras_is_poison_mode_supported(adev) &&
 671             (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2)))
 672                 return 0;
 673
 674         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 675
 676         amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
 677
 678         dev_err(adev->dev,
 679                 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 680                 status);
 681         if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
 682                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 683                         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
 684                         gfxhub_client_ids[cid],
 685                         cid);
 686         } else {
 687                 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
 688                 case IP_VERSION(9, 0, 0):
 689                         mmhub_cid = mmhub_client_ids_vega10[cid][rw];
 690                         break;
 691                 case IP_VERSION(9, 3, 0):
 692                         mmhub_cid = mmhub_client_ids_vega12[cid][rw];
 693                         break;
 694                 case IP_VERSION(9, 4, 0):
 695                         mmhub_cid = mmhub_client_ids_vega20[cid][rw];
 696                         break;
 697                 case IP_VERSION(9, 4, 1):
 698                         mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
 699                         break;
 700                 case IP_VERSION(9, 1, 0):
 701                 case IP_VERSION(9, 2, 0):
 702                         mmhub_cid = mmhub_client_ids_raven[cid][rw];
 703                         break;
 704                 case IP_VERSION(1, 5, 0):
 705                 case IP_VERSION(2, 4, 0):
 706                         mmhub_cid = mmhub_client_ids_renoir[cid][rw];
 707                         break;
 708                 case IP_VERSION(1, 8, 0):
 709                 case IP_VERSION(9, 4, 2):
 710                         mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
 711                         break;
 712                 default:
 713                         mmhub_cid = NULL;
 714                         break;
 715                 }
 716                 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 717                         mmhub_cid ? mmhub_cid : "unknown", cid);
 718         }
 719         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 720                 REG_GET_FIELD(status,
 721                 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 722         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 723                 REG_GET_FIELD(status,
 724                 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 725         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 726                 REG_GET_FIELD(status,
 727                 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 728         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 729                 REG_GET_FIELD(status,
 730                 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 731         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 732         return 0;
 733 }
 734
 735 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 736         .set = gmc_v9_0_vm_fault_interrupt_state,
 737         .process = gmc_v9_0_process_interrupt,
 738 };
 739
 740
 741 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 742         .set = gmc_v9_0_ecc_interrupt_state,
 743         .process = amdgpu_umc_process_ecc_irq,
 744 };
 745
 746 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 747 {
 748         adev->gmc.vm_fault.num_types = 1;
 749         adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 750
 751         if (!amdgpu_sriov_vf(adev) &&
 752             !adev->gmc.xgmi.connected_to_cpu &&
 753             !adev->gmc.is_app_apu) {
 754                 adev->gmc.ecc_irq.num_types = 1;
 755                 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 756         }
 757 }
 758
 759 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 760                                         uint32_t flush_type)
 761 {
 762         u32 req = 0;
 763
 764         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 765                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 766         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 767         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 768         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 769         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 770         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 771         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 772         req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 773                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 774
 775         return req;
 776 }
 777
 778 /**
 779  * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 780  *
 781  * @adev: amdgpu_device pointer
 782  * @vmhub: vmhub type
 783  *
 784  */
 785 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 786                                        uint32_t vmhub)
 787 {
 788         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
 789             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
 790                 return false;
 791
 792         return ((vmhub == AMDGPU_MMHUB0(0) ||
 793                  vmhub == AMDGPU_MMHUB1(0)) &&
 794                 (!amdgpu_sriov_vf(adev)) &&
 795                 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 796                    (adev->apu_flags & AMD_APU_IS_PICASSO))));
 797 }
 798
 799 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 800                                         uint8_t vmid, uint16_t *p_pasid)
 801 {
 802         uint32_t value;
 803
 804         value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 805                      + vmid);
 806         *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 807
 808         return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 809 }
 810
 811 /*
 812  * GART
 813  * VMID 0 is the physical GPU addresses as used by the kernel.
 814  * VMIDs 1-15 are used for userspace clients and are handled
 815  * by the amdgpu vm/hsa code.
 816  */
 817
 818 /**
 819  * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 820  *
 821  * @adev: amdgpu_device pointer
 822  * @vmid: vm instance to flush
 823  * @vmhub: which hub to flush
 824  * @flush_type: the flush type
 825  *
 826  * Flush the TLB for the requested page table using certain type.
 827  */
 828 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 829                                         uint32_t vmhub, uint32_t flush_type)
 830 {
 831         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 832         u32 j, inv_req, tmp, sem, req, ack, inst;
 833         const unsigned int eng = 17;
 834         struct amdgpu_vmhub *hub;
 835
 836         BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
 837
 838         hub = &adev->vmhub[vmhub];
 839         inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 840         sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
 841         req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 842         ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 843
 844         if (vmhub >= AMDGPU_MMHUB0(0))
 845                 inst = GET_INST(GC, 0);
 846         else
 847                 inst = vmhub;
 848
 849         /* This is necessary for SRIOV as well as for GFXOFF to function
 850          * properly under bare metal
 851          */
 852         if (adev->gfx.kiq[inst].ring.sched.ready &&
 853             (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
 854                 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 855                 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 856
 857                 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
 858                                                  1 << vmid, inst);
 859                 return;
 860         }
 861
 862         /* This path is needed before KIQ/MES/GFXOFF are set up */
 863         spin_lock(&adev->gmc.invalidate_lock);
 864
 865         /*
 866          * It may lose gpuvm invalidate acknowldege state across power-gating
 867          * off cycle, add semaphore acquire before invalidation and semaphore
 868          * release after invalidation to avoid entering power gated state
 869          * to WA the Issue
 870          */
 871
 872         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 873         if (use_semaphore) {
 874                 for (j = 0; j < adev->usec_timeout; j++) {
 875                         /* a read return value of 1 means semaphore acquire */
 876                         if (vmhub >= AMDGPU_MMHUB0(0))
 877                                 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst);
 878                         else
 879                                 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst);
 880                         if (tmp & 0x1)
 881                                 break;
 882                         udelay(1);
 883                 }
 884
 885                 if (j >= adev->usec_timeout)
 886                         DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 887         }
 888
 889         if (vmhub >= AMDGPU_MMHUB0(0))
 890                 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst);
 891         else
 892                 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst);
 893
 894         /*
 895          * Issue a dummy read to wait for the ACK register to
 896          * be cleared to avoid a false ACK due to the new fast
 897          * GRBM interface.
 898          */
 899         if ((vmhub == AMDGPU_GFXHUB(0)) &&
 900             (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
 901                 RREG32_NO_KIQ(req);
 902
 903         for (j = 0; j < adev->usec_timeout; j++) {
 904                 if (vmhub >= AMDGPU_MMHUB0(0))
 905                         tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst);
 906                 else
 907                         tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst);
 908                 if (tmp & (1 << vmid))
 909                         break;
 910                 udelay(1);
 911         }
 912
 913         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 914         if (use_semaphore) {
 915                 /*
 916                  * add semaphore release after invalidation,
 917                  * write with 0 means semaphore release
 918                  */
 919                 if (vmhub >= AMDGPU_MMHUB0(0))
 920                         WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst);
 921                 else
 922                         WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst);
 923         }
 924
 925         spin_unlock(&adev->gmc.invalidate_lock);
 926
 927         if (j < adev->usec_timeout)
 928                 return;
 929
 930         DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 931 }
 932
 933 /**
 934  * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 935  *
 936  * @adev: amdgpu_device pointer
 937  * @pasid: pasid to be flush
 938  * @flush_type: the flush type
 939  * @all_hub: flush all hubs
 940  * @inst: is used to select which instance of KIQ to use for the invalidation
 941  *
 942  * Flush the TLB for the requested pasid.
 943  */
 944 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 945                                          uint16_t pasid, uint32_t flush_type,
 946                                          bool all_hub, uint32_t inst)
 947 {
 948         uint16_t queried;
 949         int i, vmid;
 950
 951         for (vmid = 1; vmid < 16; vmid++) {
 952                 bool valid;
 953
 954                 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 955                                                                  &queried);
 956                 if (!valid || queried != pasid)
 957                         continue;
 958
 959                 if (all_hub) {
 960                         for_each_set_bit(i, adev->vmhubs_mask,
 961                                          AMDGPU_MAX_VMHUBS)
 962                                 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
 963                                                        flush_type);
 964                 } else {
 965                         gmc_v9_0_flush_gpu_tlb(adev, vmid,
 966                                                AMDGPU_GFXHUB(0),
 967                                                flush_type);
 968                 }
 969         }
 970 }
 971
 972 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 973                                             unsigned int vmid, uint64_t pd_addr)
 974 {
 975         bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
 976         struct amdgpu_device *adev = ring->adev;
 977         struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
 978         uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 979         unsigned int eng = ring->vm_inv_eng;
 980
 981         /*
 982          * It may lose gpuvm invalidate acknowldege state across power-gating
 983          * off cycle, add semaphore acquire before invalidation and semaphore
 984          * release after invalidation to avoid entering power gated state
 985          * to WA the Issue
 986          */
 987
 988         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 989         if (use_semaphore)
 990                 /* a read return value of 1 means semaphore acuqire */
 991                 amdgpu_ring_emit_reg_wait(ring,
 992                                           hub->vm_inv_eng0_sem +
 993                                           hub->eng_distance * eng, 0x1, 0x1);
 994
 995         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 996                               (hub->ctx_addr_distance * vmid),
 997                               lower_32_bits(pd_addr));
 998
 999         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1000                               (hub->ctx_addr_distance * vmid),
1001                               upper_32_bits(pd_addr));
1002
1003         amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
1004                                             hub->eng_distance * eng,
1005                                             hub->vm_inv_eng0_ack +
1006                                             hub->eng_distance * eng,
1007                                             req, 1 << vmid);
1008
1009         /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
1010         if (use_semaphore)
1011                 /*
1012                  * add semaphore release after invalidation,
1013                  * write with 0 means semaphore release
1014                  */
1015                 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1016                                       hub->eng_distance * eng, 0);
1017
1018         return pd_addr;
1019 }
1020
1021 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
1022                                         unsigned int pasid)
1023 {
1024         struct amdgpu_device *adev = ring->adev;
1025         uint32_t reg;
1026
1027         /* Do nothing because there's no lut register for mmhub1. */
1028         if (ring->vm_hub == AMDGPU_MMHUB1(0))
1029                 return;
1030
1031         if (ring->vm_hub == AMDGPU_GFXHUB(0))
1032                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1033         else
1034                 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1035
1036         amdgpu_ring_emit_wreg(ring, reg, pasid);
1037 }
1038
1039 /*
1040  * PTE format on VEGA 10:
1041  * 63:59 reserved
1042  * 58:57 mtype
1043  * 56 F
1044  * 55 L
1045  * 54 P
1046  * 53 SW
1047  * 52 T
1048  * 50:48 reserved
1049  * 47:12 4k physical page base address
1050  * 11:7 fragment
1051  * 6 write
1052  * 5 read
1053  * 4 exe
1054  * 3 Z
1055  * 2 snooped
1056  * 1 system
1057  * 0 valid
1058  *
1059  * PDE format on VEGA 10:
1060  * 63:59 block fragment size
1061  * 58:55 reserved
1062  * 54 P
1063  * 53:48 reserved
1064  * 47:6 physical base address of PD or PTE
1065  * 5:3 reserved
1066  * 2 C
1067  * 1 system
1068  * 0 valid
1069  */
1070
1071 static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1072
1073 {
1074         switch (flags) {
1075         case AMDGPU_VM_MTYPE_DEFAULT:
1076                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1077         case AMDGPU_VM_MTYPE_NC:
1078                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1079         case AMDGPU_VM_MTYPE_WC:
1080                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1081         case AMDGPU_VM_MTYPE_RW:
1082                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1083         case AMDGPU_VM_MTYPE_CC:
1084                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1085         case AMDGPU_VM_MTYPE_UC:
1086                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1087         default:
1088                 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1089         }
1090 }
1091
1092 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1093                                 uint64_t *addr, uint64_t *flags)
1094 {
1095         if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1096                 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1097         BUG_ON(*addr & 0xFFFF00000000003FULL);
1098
1099         if (!adev->gmc.translate_further)
1100                 return;
1101
1102         if (level == AMDGPU_VM_PDB1) {
1103                 /* Set the block fragment size */
1104                 if (!(*flags & AMDGPU_PDE_PTE))
1105                         *flags |= AMDGPU_PDE_BFS(0x9);
1106
1107         } else if (level == AMDGPU_VM_PDB0) {
1108                 if (*flags & AMDGPU_PDE_PTE) {
1109                         *flags &= ~AMDGPU_PDE_PTE;
1110                         if (!(*flags & AMDGPU_PTE_VALID))
1111                                 *addr |= 1 << PAGE_SHIFT;
1112                 } else {
1113                         *flags |= AMDGPU_PTE_TF;
1114                 }
1115         }
1116 }
1117
1118 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1119                                          struct amdgpu_bo *bo,
1120                                          struct amdgpu_bo_va_mapping *mapping,
1121                                          uint64_t *flags)
1122 {
1123         struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1124         bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
1125         bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);
1126         bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1127         bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1128         struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1129         unsigned int mtype_local, mtype;
1130         bool snoop = false;
1131         bool is_local;
1132
1133         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1134         case IP_VERSION(9, 4, 1):
1135         case IP_VERSION(9, 4, 2):
1136                 if (is_vram) {
1137                         if (bo_adev == adev) {
1138                                 if (uncached)
1139                                         mtype = MTYPE_UC;
1140                                 else if (coherent)
1141                                         mtype = MTYPE_CC;
1142                                 else
1143                                         mtype = MTYPE_RW;
1144                                 /* FIXME: is this still needed? Or does
1145                                  * amdgpu_ttm_tt_pde_flags already handle this?
1146                                  */
1147                                 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
1148                                              IP_VERSION(9, 4, 2) ||
1149                                      amdgpu_ip_version(adev, GC_HWIP, 0) ==
1150                                              IP_VERSION(9, 4, 3)) &&
1151                                     adev->gmc.xgmi.connected_to_cpu)
1152                                         snoop = true;
1153                         } else {
1154                                 if (uncached || coherent)
1155                                         mtype = MTYPE_UC;
1156                                 else
1157                                         mtype = MTYPE_NC;
1158                                 if (mapping->bo_va->is_xgmi)
1159                                         snoop = true;
1160                         }
1161                 } else {
1162                         if (uncached || coherent)
1163                                 mtype = MTYPE_UC;
1164                         else
1165                                 mtype = MTYPE_NC;
1166                         /* FIXME: is this still needed? Or does
1167                          * amdgpu_ttm_tt_pde_flags already handle this?
1168                          */
1169                         snoop = true;
1170                 }
1171                 break;
1172         case IP_VERSION(9, 4, 3):
1173                 /* Only local VRAM BOs or system memory on non-NUMA APUs
1174                  * can be assumed to be local in their entirety. Choose
1175                  * MTYPE_NC as safe fallback for all system memory BOs on
1176                  * NUMA systems. Their MTYPE can be overridden per-page in
1177                  * gmc_v9_0_override_vm_pte_flags.
1178                  */
1179                 mtype_local = MTYPE_RW;
1180                 if (amdgpu_mtype_local == 1) {
1181                         DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
1182                         mtype_local = MTYPE_NC;
1183                 } else if (amdgpu_mtype_local == 2) {
1184                         DRM_INFO_ONCE("Using MTYPE_CC for local memory\n");
1185                         mtype_local = MTYPE_CC;
1186                 } else {
1187                         DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
1188                 }
1189                 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1190                             num_possible_nodes() <= 1) ||
1191                            (is_vram && adev == bo_adev &&
1192                             KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1193                 snoop = true;
1194                 if (uncached) {
1195                         mtype = MTYPE_UC;
1196                 } else if (ext_coherent) {
1197                         if (adev->rev_id)
1198                                 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1199                         else
1200                                 mtype = MTYPE_UC;
1201                 } else if (adev->flags & AMD_IS_APU) {
1202                         mtype = is_local ? mtype_local : MTYPE_NC;
1203                 } else {
1204                         /* dGPU */
1205                         if (is_local)
1206                                 mtype = mtype_local;
1207                         else if (is_vram)
1208                                 mtype = MTYPE_NC;
1209                         else
1210                                 mtype = MTYPE_UC;
1211                 }
1212
1213                 break;
1214         default:
1215                 if (uncached || coherent)
1216                         mtype = MTYPE_UC;
1217                 else
1218                         mtype = MTYPE_NC;
1219
1220                 /* FIXME: is this still needed? Or does
1221                  * amdgpu_ttm_tt_pde_flags already handle this?
1222                  */
1223                 if (!is_vram)
1224                         snoop = true;
1225         }
1226
1227         if (mtype != MTYPE_NC)
1228                 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1229                          AMDGPU_PTE_MTYPE_VG10(mtype);
1230         *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1231 }
1232
1233 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1234                                 struct amdgpu_bo_va_mapping *mapping,
1235                                 uint64_t *flags)
1236 {
1237         struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1238
1239         *flags &= ~AMDGPU_PTE_EXECUTABLE;
1240         *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1241
1242         *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1243         *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1244
1245         if (mapping->flags & AMDGPU_PTE_PRT) {
1246                 *flags |= AMDGPU_PTE_PRT;
1247                 *flags &= ~AMDGPU_PTE_VALID;
1248         }
1249
1250         if (bo && bo->tbo.resource)
1251                 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
1252                                              mapping, flags);
1253 }
1254
1255 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1256                                            struct amdgpu_vm *vm,
1257                                            uint64_t addr, uint64_t *flags)
1258 {
1259         int local_node, nid;
1260
1261         /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1262          * memory can use more efficient MTYPEs.
1263          */
1264         if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))
1265                 return;
1266
1267         /* Only direct-mapped memory allows us to determine the NUMA node from
1268          * the DMA address.
1269          */
1270         if (!adev->ram_is_direct_mapped) {
1271                 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1272                 return;
1273         }
1274
1275         /* MTYPE_NC is the same default and can be overridden.
1276          * MTYPE_UC will be present if the memory is extended-coherent
1277          * and can also be overridden.
1278          */
1279         if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1280             AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) &&
1281             (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1282             AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) {
1283                 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1284                 return;
1285         }
1286
1287         /* FIXME: Only supported on native mode for now. For carve-out, the
1288          * NUMA affinity of the GPU/VM needs to come from the PCI info because
1289          * memory partitions are not associated with different NUMA nodes.
1290          */
1291         if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1292                 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1293         } else {
1294                 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1295                 return;
1296         }
1297
1298         /* Only handle real RAM. Mappings of PCIe resources don't have struct
1299          * page or NUMA nodes.
1300          */
1301         if (!page_is_ram(addr >> PAGE_SHIFT)) {
1302                 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1303                 return;
1304         }
1305         nid = pfn_to_nid(addr >> PAGE_SHIFT);
1306         dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1307                             vm->mem_id, local_node, nid);
1308         if (nid == local_node) {
1309                 uint64_t old_flags = *flags;
1310                 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1311                         AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) {
1312                         unsigned int mtype_local = MTYPE_RW;
1313
1314                         if (amdgpu_mtype_local == 1)
1315                                 mtype_local = MTYPE_NC;
1316                         else if (amdgpu_mtype_local == 2)
1317                                 mtype_local = MTYPE_CC;
1318
1319                         *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1320                                  AMDGPU_PTE_MTYPE_VG10(mtype_local);
1321                 } else if (adev->rev_id) {
1322                         /* MTYPE_UC case */
1323                         *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1324                                  AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1325                 }
1326
1327                 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1328                                     old_flags, *flags);
1329         }
1330 }
1331
1332 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1333 {
1334         u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1335         unsigned int size;
1336
1337         /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1338
1339         if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1340                 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1341         } else {
1342                 u32 viewport;
1343
1344                 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1345                 case IP_VERSION(1, 0, 0):
1346                 case IP_VERSION(1, 0, 1):
1347                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1348                         size = (REG_GET_FIELD(viewport,
1349                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1350                                 REG_GET_FIELD(viewport,
1351                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1352                                 4);
1353                         break;
1354                 case IP_VERSION(2, 1, 0):
1355                         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1356                         size = (REG_GET_FIELD(viewport,
1357                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1358                                 REG_GET_FIELD(viewport,
1359                                               HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1360                                 4);
1361                         break;
1362                 default:
1363                         viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1364                         size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1365                                 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1366                                 4);
1367                         break;
1368                 }
1369         }
1370
1371         return size;
1372 }
1373
1374 static enum amdgpu_memory_partition
1375 gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
1376 {
1377         enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
1378
1379         if (adev->nbio.funcs->get_memory_partition_mode)
1380                 mode = adev->nbio.funcs->get_memory_partition_mode(adev,
1381                                                                    supp_modes);
1382
1383         return mode;
1384 }
1385
1386 static enum amdgpu_memory_partition
1387 gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
1388 {
1389         if (amdgpu_sriov_vf(adev))
1390                 return AMDGPU_NPS1_PARTITION_MODE;
1391
1392         return gmc_v9_0_get_memory_partition(adev, NULL);
1393 }
1394
1395 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1396         .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1397         .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1398         .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1399         .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1400         .map_mtype = gmc_v9_0_map_mtype,
1401         .get_vm_pde = gmc_v9_0_get_vm_pde,
1402         .get_vm_pte = gmc_v9_0_get_vm_pte,
1403         .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1404         .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1405         .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
1406 };
1407
1408 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1409 {
1410         adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1411 }
1412
1413 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1414 {
1415         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1416         case IP_VERSION(6, 0, 0):
1417                 adev->umc.funcs = &umc_v6_0_funcs;
1418                 break;
1419         case IP_VERSION(6, 1, 1):
1420                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1421                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1422                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1423                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1424                 adev->umc.retire_unit = 1;
1425                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1426                 adev->umc.ras = &umc_v6_1_ras;
1427                 break;
1428         case IP_VERSION(6, 1, 2):
1429                 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1430                 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1431                 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1432                 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1433                 adev->umc.retire_unit = 1;
1434                 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1435                 adev->umc.ras = &umc_v6_1_ras;
1436                 break;
1437         case IP_VERSION(6, 7, 0):
1438                 adev->umc.max_ras_err_cnt_per_query =
1439                         UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1440                 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1441                 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1442                 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1443                 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1444                 if (!adev->gmc.xgmi.connected_to_cpu)
1445                         adev->umc.ras = &umc_v6_7_ras;
1446                 if (1 & adev->smuio.funcs->get_die_id(adev))
1447                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1448                 else
1449                         adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1450                 break;
1451         case IP_VERSION(12, 0, 0):
1452                 adev->umc.max_ras_err_cnt_per_query =
1453                         UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1454                 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1455                 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1456                 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1457                 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1458                 adev->umc.active_mask = adev->aid_mask;
1459                 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1460                 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1461                         adev->umc.ras = &umc_v12_0_ras;
1462                 break;
1463         default:
1464                 break;
1465         }
1466 }
1467
1468 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1469 {
1470         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1471         case IP_VERSION(9, 4, 1):
1472                 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1473                 break;
1474         case IP_VERSION(9, 4, 2):
1475                 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1476                 break;
1477         case IP_VERSION(1, 8, 0):
1478                 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1479                 break;
1480         default:
1481                 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1482                 break;
1483         }
1484 }
1485
1486 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1487 {
1488         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1489         case IP_VERSION(9, 4, 0):
1490                 adev->mmhub.ras = &mmhub_v1_0_ras;
1491                 break;
1492         case IP_VERSION(9, 4, 1):
1493                 adev->mmhub.ras = &mmhub_v9_4_ras;
1494                 break;
1495         case IP_VERSION(9, 4, 2):
1496                 adev->mmhub.ras = &mmhub_v1_7_ras;
1497                 break;
1498         case IP_VERSION(1, 8, 0):
1499                 adev->mmhub.ras = &mmhub_v1_8_ras;
1500                 break;
1501         default:
1502                 /* mmhub ras is not available */
1503                 break;
1504         }
1505 }
1506
1507 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1508 {
1509         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
1510                 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1511         else
1512                 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1513 }
1514
1515 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1516 {
1517         adev->hdp.ras = &hdp_v4_0_ras;
1518 }
1519
1520 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1521 {
1522         struct amdgpu_mca *mca = &adev->mca;
1523
1524         /* is UMC the right IP to check for MCA?  Maybe DF? */
1525         switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1526         case IP_VERSION(6, 7, 0):
1527                 if (!adev->gmc.xgmi.connected_to_cpu) {
1528                         mca->mp0.ras = &mca_v3_0_mp0_ras;
1529                         mca->mp1.ras = &mca_v3_0_mp1_ras;
1530                         mca->mpio.ras = &mca_v3_0_mpio_ras;
1531                 }
1532                 break;
1533         default:
1534                 break;
1535         }
1536 }
1537
1538 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1539 {
1540         if (!adev->gmc.xgmi.connected_to_cpu)
1541                 adev->gmc.xgmi.ras = &xgmi_ras;
1542 }
1543
1544 static int gmc_v9_0_early_init(void *handle)
1545 {
1546         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1547
1548         /*
1549          * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1550          * in their IP discovery tables
1551          */
1552         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1553             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1554             amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
1555                 adev->gmc.xgmi.supported = true;
1556
1557         if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1558                 adev->gmc.xgmi.supported = true;
1559                 adev->gmc.xgmi.connected_to_cpu =
1560                         adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1561         }
1562
1563         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1564                 enum amdgpu_pkg_type pkg_type =
1565                         adev->smuio.funcs->get_pkg_type(adev);
1566                 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1567                  * and the APU, can be in used two possible modes:
1568                  *  - carveout mode
1569                  *  - native APU mode
1570                  * "is_app_apu" can be used to identify the APU in the native
1571                  * mode.
1572                  */
1573                 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1574                                         !pci_resource_len(adev->pdev, 0));
1575         }
1576
1577         gmc_v9_0_set_gmc_funcs(adev);
1578         gmc_v9_0_set_irq_funcs(adev);
1579         gmc_v9_0_set_umc_funcs(adev);
1580         gmc_v9_0_set_mmhub_funcs(adev);
1581         gmc_v9_0_set_mmhub_ras_funcs(adev);
1582         gmc_v9_0_set_gfxhub_funcs(adev);
1583         gmc_v9_0_set_hdp_ras_funcs(adev);
1584         gmc_v9_0_set_mca_ras_funcs(adev);
1585         gmc_v9_0_set_xgmi_ras_funcs(adev);
1586
1587         adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1588         adev->gmc.shared_aperture_end =
1589                 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1590         adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1591         adev->gmc.private_aperture_end =
1592                 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1593         adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1594
1595         return 0;
1596 }
1597
1598 static int gmc_v9_0_late_init(void *handle)
1599 {
1600         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1601         int r;
1602
1603         r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1604         if (r)
1605                 return r;
1606
1607         /*
1608          * Workaround performance drop issue with VBIOS enables partial
1609          * writes, while disables HBM ECC for vega10.
1610          */
1611         if (!amdgpu_sriov_vf(adev) &&
1612             (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1613                 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1614                         if (adev->df.funcs &&
1615                             adev->df.funcs->enable_ecc_force_par_wr_rmw)
1616                                 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1617                 }
1618         }
1619
1620         if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1621                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1622                 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1623         }
1624
1625         r = amdgpu_gmc_ras_late_init(adev);
1626         if (r)
1627                 return r;
1628
1629         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1630 }
1631
1632 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1633                                         struct amdgpu_gmc *mc)
1634 {
1635         u64 base = adev->mmhub.funcs->get_fb_location(adev);
1636
1637         amdgpu_gmc_set_agp_default(adev, mc);
1638
1639         /* add the xgmi offset of the physical node */
1640         base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1641         if (adev->gmc.xgmi.connected_to_cpu) {
1642                 amdgpu_gmc_sysvm_location(adev, mc);
1643         } else {
1644                 amdgpu_gmc_vram_location(adev, mc, base);
1645                 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1646                 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1647                         amdgpu_gmc_agp_location(adev, mc);
1648         }
1649         /* base offset of vram pages */
1650         adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1651
1652         /* XXX: add the xgmi offset of the physical node? */
1653         adev->vm_manager.vram_base_offset +=
1654                 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1655 }
1656
1657 /**
1658  * gmc_v9_0_mc_init - initialize the memory controller driver params
1659  *
1660  * @adev: amdgpu_device pointer
1661  *
1662  * Look up the amount of vram, vram width, and decide how to place
1663  * vram and gart within the GPU's physical address space.
1664  * Returns 0 for success.
1665  */
1666 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1667 {
1668         int r;
1669
1670         /* size in MB on si */
1671         if (!adev->gmc.is_app_apu) {
1672                 adev->gmc.mc_vram_size =
1673                         adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1674         } else {
1675                 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1676                 adev->gmc.mc_vram_size = 0;
1677         }
1678         adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1679
1680         if (!(adev->flags & AMD_IS_APU) &&
1681             !adev->gmc.xgmi.connected_to_cpu) {
1682                 r = amdgpu_device_resize_fb_bar(adev);
1683                 if (r)
1684                         return r;
1685         }
1686         adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1687         adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1688
1689 #ifdef CONFIG_X86_64
1690         /*
1691          * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1692          * interface can use VRAM through here as it appears system reserved
1693          * memory in host address space.
1694          *
1695          * For APUs, VRAM is just the stolen system memory and can be accessed
1696          * directly.
1697          *
1698          * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1699          */
1700
1701         /* check whether both host-gpu and gpu-gpu xgmi links exist */
1702         if ((!amdgpu_sriov_vf(adev) &&
1703                 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1704             (adev->gmc.xgmi.supported &&
1705              adev->gmc.xgmi.connected_to_cpu)) {
1706                 adev->gmc.aper_base =
1707                         adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1708                         adev->gmc.xgmi.physical_node_id *
1709                         adev->gmc.xgmi.node_segment_size;
1710                 adev->gmc.aper_size = adev->gmc.real_vram_size;
1711         }
1712
1713 #endif
1714         adev->gmc.visible_vram_size = adev->gmc.aper_size;
1715
1716         /* set the gart size */
1717         if (amdgpu_gart_size == -1) {
1718                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1719                 case IP_VERSION(9, 0, 1):  /* all engines support GPUVM */
1720                 case IP_VERSION(9, 2, 1):  /* all engines support GPUVM */
1721                 case IP_VERSION(9, 4, 0):
1722                 case IP_VERSION(9, 4, 1):
1723                 case IP_VERSION(9, 4, 2):
1724                 case IP_VERSION(9, 4, 3):
1725                 default:
1726                         adev->gmc.gart_size = 512ULL << 20;
1727                         break;
1728                 case IP_VERSION(9, 1, 0):   /* DCE SG support */
1729                 case IP_VERSION(9, 2, 2):   /* DCE SG support */
1730                 case IP_VERSION(9, 3, 0):
1731                         adev->gmc.gart_size = 1024ULL << 20;
1732                         break;
1733                 }
1734         } else {
1735                 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1736         }
1737
1738         adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1739
1740         gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1741
1742         return 0;
1743 }
1744
1745 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1746 {
1747         int r;
1748
1749         if (adev->gart.bo) {
1750                 WARN(1, "VEGA10 PCIE GART already initialized\n");
1751                 return 0;
1752         }
1753
1754         if (adev->gmc.xgmi.connected_to_cpu) {
1755                 adev->gmc.vmid0_page_table_depth = 1;
1756                 adev->gmc.vmid0_page_table_block_size = 12;
1757         } else {
1758                 adev->gmc.vmid0_page_table_depth = 0;
1759                 adev->gmc.vmid0_page_table_block_size = 0;
1760         }
1761
1762         /* Initialize common gart structure */
1763         r = amdgpu_gart_init(adev);
1764         if (r)
1765                 return r;
1766         adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1767         adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1768                                  AMDGPU_PTE_EXECUTABLE;
1769
1770         if (!adev->gmc.real_vram_size) {
1771                 dev_info(adev->dev, "Put GART in system memory for APU\n");
1772                 r = amdgpu_gart_table_ram_alloc(adev);
1773                 if (r)
1774                         dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1775         } else {
1776                 r = amdgpu_gart_table_vram_alloc(adev);
1777                 if (r)
1778                         return r;
1779
1780                 if (adev->gmc.xgmi.connected_to_cpu)
1781                         r = amdgpu_gmc_pdb0_alloc(adev);
1782         }
1783
1784         return r;
1785 }
1786
1787 /**
1788  * gmc_v9_0_save_registers - saves regs
1789  *
1790  * @adev: amdgpu_device pointer
1791  *
1792  * This saves potential register values that should be
1793  * restored upon resume
1794  */
1795 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1796 {
1797         if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1798             (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1799                 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1800 }
1801
1802 static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
1803 {
1804         enum amdgpu_memory_partition mode;
1805         u32 supp_modes;
1806         bool valid;
1807
1808         mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1809
1810         /* Mode detected by hardware not present in supported modes */
1811         if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &&
1812             !(BIT(mode - 1) & supp_modes))
1813                 return false;
1814
1815         switch (mode) {
1816         case UNKNOWN_MEMORY_PARTITION_MODE:
1817         case AMDGPU_NPS1_PARTITION_MODE:
1818                 valid = (adev->gmc.num_mem_partitions == 1);
1819                 break;
1820         case AMDGPU_NPS2_PARTITION_MODE:
1821                 valid = (adev->gmc.num_mem_partitions == 2);
1822                 break;
1823         case AMDGPU_NPS4_PARTITION_MODE:
1824                 valid = (adev->gmc.num_mem_partitions == 3 ||
1825                          adev->gmc.num_mem_partitions == 4);
1826                 break;
1827         default:
1828                 valid = false;
1829         }
1830
1831         return valid;
1832 }
1833
1834 static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
1835 {
1836         int i;
1837
1838         /* Check if node with id 'nid' is present in 'node_ids' array */
1839         for (i = 0; i < num_ids; ++i)
1840                 if (node_ids[i] == nid)
1841                         return true;
1842
1843         return false;
1844 }
1845
1846 static void
1847 gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
1848                               struct amdgpu_mem_partition_info *mem_ranges)
1849 {
1850         struct amdgpu_numa_info numa_info;
1851         int node_ids[MAX_MEM_RANGES];
1852         int num_ranges = 0, ret;
1853         int num_xcc, xcc_id;
1854         uint32_t xcc_mask;
1855
1856         num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1857         xcc_mask = (1U << num_xcc) - 1;
1858
1859         for_each_inst(xcc_id, xcc_mask) {
1860                 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
1861                 if (ret)
1862                         continue;
1863
1864                 if (numa_info.nid == NUMA_NO_NODE) {
1865                         mem_ranges[0].size = numa_info.size;
1866                         mem_ranges[0].numa.node = numa_info.nid;
1867                         num_ranges = 1;
1868                         break;
1869                 }
1870
1871                 if (gmc_v9_0_is_node_present(node_ids, num_ranges,
1872                                              numa_info.nid))
1873                         continue;
1874
1875                 node_ids[num_ranges] = numa_info.nid;
1876                 mem_ranges[num_ranges].numa.node = numa_info.nid;
1877                 mem_ranges[num_ranges].size = numa_info.size;
1878                 ++num_ranges;
1879         }
1880
1881         adev->gmc.num_mem_partitions = num_ranges;
1882 }
1883
1884 static void
1885 gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
1886                             struct amdgpu_mem_partition_info *mem_ranges)
1887 {
1888         enum amdgpu_memory_partition mode;
1889         u32 start_addr = 0, size;
1890         int i;
1891
1892         mode = gmc_v9_0_query_memory_partition(adev);
1893
1894         switch (mode) {
1895         case UNKNOWN_MEMORY_PARTITION_MODE:
1896         case AMDGPU_NPS1_PARTITION_MODE:
1897                 adev->gmc.num_mem_partitions = 1;
1898                 break;
1899         case AMDGPU_NPS2_PARTITION_MODE:
1900                 adev->gmc.num_mem_partitions = 2;
1901                 break;
1902         case AMDGPU_NPS4_PARTITION_MODE:
1903                 if (adev->flags & AMD_IS_APU)
1904                         adev->gmc.num_mem_partitions = 3;
1905                 else
1906                         adev->gmc.num_mem_partitions = 4;
1907                 break;
1908         default:
1909                 adev->gmc.num_mem_partitions = 1;
1910                 break;
1911         }
1912
1913         size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT;
1914         size /= adev->gmc.num_mem_partitions;
1915
1916         for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
1917                 mem_ranges[i].range.fpfn = start_addr;
1918                 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT);
1919                 mem_ranges[i].range.lpfn = start_addr + size - 1;
1920                 start_addr += size;
1921         }
1922
1923         /* Adjust the last one */
1924         mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn =
1925                 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
1926         mem_ranges[adev->gmc.num_mem_partitions - 1].size =
1927                 adev->gmc.real_vram_size -
1928                 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn
1929                  << AMDGPU_GPU_PAGE_SHIFT);
1930 }
1931
1932 static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
1933 {
1934         bool valid;
1935
1936         adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,
1937                                            sizeof(struct amdgpu_mem_partition_info),
1938                                            GFP_KERNEL);
1939         if (!adev->gmc.mem_partitions)
1940                 return -ENOMEM;
1941
1942         /* TODO : Get the range from PSP/Discovery for dGPU */
1943         if (adev->gmc.is_app_apu)
1944                 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
1945         else
1946                 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
1947
1948         if (amdgpu_sriov_vf(adev))
1949                 valid = true;
1950         else
1951                 valid = gmc_v9_0_validate_partition_info(adev);
1952         if (!valid) {
1953                 /* TODO: handle invalid case */
1954                 dev_WARN(adev->dev,
1955                          "Mem ranges not matching with hardware config");
1956         }
1957
1958         return 0;
1959 }
1960
1961 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
1962 {
1963         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1964         adev->gmc.vram_width = 128 * 64;
1965 }
1966
1967 static int gmc_v9_0_sw_init(void *handle)
1968 {
1969         int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
1970         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1971         unsigned long inst_mask = adev->aid_mask;
1972
1973         adev->gfxhub.funcs->init(adev);
1974
1975         adev->mmhub.funcs->init(adev);
1976
1977         spin_lock_init(&adev->gmc.invalidate_lock);
1978
1979         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1980                 gmc_v9_4_3_init_vram_info(adev);
1981         } else if (!adev->bios) {
1982                 if (adev->flags & AMD_IS_APU) {
1983                         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
1984                         adev->gmc.vram_width = 64 * 64;
1985                 } else {
1986                         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1987                         adev->gmc.vram_width = 128 * 64;
1988                 }
1989         } else {
1990                 r = amdgpu_atomfirmware_get_vram_info(adev,
1991                         &vram_width, &vram_type, &vram_vendor);
1992                 if (amdgpu_sriov_vf(adev))
1993                         /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1994                          * and DF related registers is not readable, seems hardcord is the
1995                          * only way to set the correct vram_width
1996                          */
1997                         adev->gmc.vram_width = 2048;
1998                 else if (amdgpu_emu_mode != 1)
1999                         adev->gmc.vram_width = vram_width;
2000
2001                 if (!adev->gmc.vram_width) {
2002                         int chansize, numchan;
2003
2004                         /* hbm memory channel size */
2005                         if (adev->flags & AMD_IS_APU)
2006                                 chansize = 64;
2007                         else
2008                                 chansize = 128;
2009                         if (adev->df.funcs &&
2010                             adev->df.funcs->get_hbm_channel_number) {
2011                                 numchan = adev->df.funcs->get_hbm_channel_number(adev);
2012                                 adev->gmc.vram_width = numchan * chansize;
2013                         }
2014                 }
2015
2016                 adev->gmc.vram_type = vram_type;
2017                 adev->gmc.vram_vendor = vram_vendor;
2018         }
2019         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2020         case IP_VERSION(9, 1, 0):
2021         case IP_VERSION(9, 2, 2):
2022                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2023                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2024
2025                 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
2026                         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2027                 } else {
2028                         /* vm_size is 128TB + 512GB for legacy 3-level page support */
2029                         amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
2030                         adev->gmc.translate_further =
2031                                 adev->vm_manager.num_level > 1;
2032                 }
2033                 break;
2034         case IP_VERSION(9, 0, 1):
2035         case IP_VERSION(9, 2, 1):
2036         case IP_VERSION(9, 4, 0):
2037         case IP_VERSION(9, 3, 0):
2038         case IP_VERSION(9, 4, 2):
2039                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2040                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2041
2042                 /*
2043                  * To fulfill 4-level page support,
2044                  * vm size is 256TB (48bit), maximum size of Vega10,
2045                  * block size 512 (9bit)
2046                  */
2047
2048                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2049                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
2050                         adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2051                 break;
2052         case IP_VERSION(9, 4, 1):
2053                 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2054                 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2055                 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
2056
2057                 /* Keep the vm size same with Vega20 */
2058                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2059                 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2060                 break;
2061         case IP_VERSION(9, 4, 3):
2062                 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
2063                                   NUM_XCC(adev->gfx.xcc_mask));
2064
2065                 inst_mask <<= AMDGPU_MMHUB0(0);
2066                 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2067
2068                 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2069                 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2070                 break;
2071         default:
2072                 break;
2073         }
2074
2075         /* This interrupt is VMC page fault.*/
2076         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
2077                                 &adev->gmc.vm_fault);
2078         if (r)
2079                 return r;
2080
2081         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
2082                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
2083                                         &adev->gmc.vm_fault);
2084                 if (r)
2085                         return r;
2086         }
2087
2088         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
2089                                 &adev->gmc.vm_fault);
2090
2091         if (r)
2092                 return r;
2093
2094         if (!amdgpu_sriov_vf(adev) &&
2095             !adev->gmc.xgmi.connected_to_cpu &&
2096             !adev->gmc.is_app_apu) {
2097                 /* interrupt sent to DF. */
2098                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
2099                                       &adev->gmc.ecc_irq);
2100                 if (r)
2101                         return r;
2102         }
2103
2104         /* Set the internal MC address mask
2105          * This is the max address of the GPU's
2106          * internal address space.
2107          */
2108         adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
2109
2110         dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
2111                                         IP_VERSION(9, 4, 2) ?
2112                                 48 :
2113                                 44;
2114         r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
2115         if (r) {
2116                 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
2117                 return r;
2118         }
2119         adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
2120
2121         r = gmc_v9_0_mc_init(adev);
2122         if (r)
2123                 return r;
2124
2125         amdgpu_gmc_get_vbios_allocations(adev);
2126
2127         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
2128                 r = gmc_v9_0_init_mem_ranges(adev);
2129                 if (r)
2130                         return r;
2131         }
2132
2133         /* Memory manager */
2134         r = amdgpu_bo_init(adev);
2135         if (r)
2136                 return r;
2137
2138         r = gmc_v9_0_gart_init(adev);
2139         if (r)
2140                 return r;
2141
2142         /*
2143          * number of VMs
2144          * VMID 0 is reserved for System
2145          * amdgpu graphics/compute will use VMIDs 1..n-1
2146          * amdkfd will use VMIDs n..15
2147          *
2148          * The first KFD VMID is 8 for GPUs with graphics, 3 for
2149          * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2150          * for video processing.
2151          */
2152         adev->vm_manager.first_kfd_vmid =
2153                 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2154                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2155                  amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ?
2156                         3 :
2157                         8;
2158
2159         amdgpu_vm_manager_init(adev);
2160
2161         gmc_v9_0_save_registers(adev);
2162
2163         r = amdgpu_gmc_ras_sw_init(adev);
2164         if (r)
2165                 return r;
2166
2167         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
2168                 amdgpu_gmc_sysfs_init(adev);
2169
2170         return 0;
2171 }
2172
2173 static int gmc_v9_0_sw_fini(void *handle)
2174 {
2175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2176
2177         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
2178                 amdgpu_gmc_sysfs_fini(adev);
2179
2180         amdgpu_gmc_ras_fini(adev);
2181         amdgpu_gem_force_release(adev);
2182         amdgpu_vm_manager_fini(adev);
2183         if (!adev->gmc.real_vram_size) {
2184                 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2185                 amdgpu_gart_table_ram_free(adev);
2186         } else {
2187                 amdgpu_gart_table_vram_free(adev);
2188         }
2189         amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2190         amdgpu_bo_fini(adev);
2191
2192         adev->gmc.num_mem_partitions = 0;
2193         kfree(adev->gmc.mem_partitions);
2194
2195         return 0;
2196 }
2197
2198 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2199 {
2200         switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2201         case IP_VERSION(9, 0, 0):
2202                 if (amdgpu_sriov_vf(adev))
2203                         break;
2204                 fallthrough;
2205         case IP_VERSION(9, 4, 0):
2206                 soc15_program_register_sequence(adev,
2207                                                 golden_settings_mmhub_1_0_0,
2208                                                 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2209                 soc15_program_register_sequence(adev,
2210                                                 golden_settings_athub_1_0_0,
2211                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
2212                 break;
2213         case IP_VERSION(9, 1, 0):
2214         case IP_VERSION(9, 2, 0):
2215                 /* TODO for renoir */
2216                 soc15_program_register_sequence(adev,
2217                                                 golden_settings_athub_1_0_0,
2218                                                 ARRAY_SIZE(golden_settings_athub_1_0_0));
2219                 break;
2220         default:
2221                 break;
2222         }
2223 }
2224
2225 /**
2226  * gmc_v9_0_restore_registers - restores regs
2227  *
2228  * @adev: amdgpu_device pointer
2229  *
2230  * This restores register values, saved at suspend.
2231  */
2232 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2233 {
2234         if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2235             (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2236                 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2237                 WARN_ON(adev->gmc.sdpif_register !=
2238                         RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2239         }
2240 }
2241
2242 /**
2243  * gmc_v9_0_gart_enable - gart enable
2244  *
2245  * @adev: amdgpu_device pointer
2246  */
2247 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2248 {
2249         int r;
2250
2251         if (adev->gmc.xgmi.connected_to_cpu)
2252                 amdgpu_gmc_init_pdb0(adev);
2253
2254         if (adev->gart.bo == NULL) {
2255                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2256                 return -EINVAL;
2257         }
2258
2259         amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2260
2261         if (!adev->in_s0ix) {
2262                 r = adev->gfxhub.funcs->gart_enable(adev);
2263                 if (r)
2264                         return r;
2265         }
2266
2267         r = adev->mmhub.funcs->gart_enable(adev);
2268         if (r)
2269                 return r;
2270
2271         DRM_INFO("PCIE GART of %uM enabled.\n",
2272                  (unsigned int)(adev->gmc.gart_size >> 20));
2273         if (adev->gmc.pdb0_bo)
2274                 DRM_INFO("PDB0 located at 0x%016llX\n",
2275                                 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2276         DRM_INFO("PTB located at 0x%016llX\n",
2277                         (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2278
2279         return 0;
2280 }
2281
2282 static int gmc_v9_0_hw_init(void *handle)
2283 {
2284         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2285         bool value;
2286         int i, r;
2287
2288         adev->gmc.flush_pasid_uses_kiq = true;
2289
2290         /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2291          * (type 2), which flushes both. Due to a race condition with
2292          * concurrent memory accesses using the same TLB cache line, we still
2293          * need a second TLB flush after this.
2294          */
2295         adev->gmc.flush_tlb_needs_extra_type_2 =
2296                 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2297                 adev->gmc.xgmi.num_physical_nodes;
2298         /*
2299          * TODO: This workaround is badly documented and had a buggy
2300          * implementation. We should probably verify what we do here.
2301          */
2302         adev->gmc.flush_tlb_needs_extra_type_0 =
2303                 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &&
2304                 adev->rev_id == 0;
2305
2306         /* The sequence of these two function calls matters.*/
2307         gmc_v9_0_init_golden_registers(adev);
2308
2309         if (adev->mode_info.num_crtc) {
2310                 /* Lockout access through VGA aperture*/
2311                 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2312                 /* disable VGA render */
2313                 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2314         }
2315
2316         if (adev->mmhub.funcs->update_power_gating)
2317                 adev->mmhub.funcs->update_power_gating(adev, true);
2318
2319         adev->hdp.funcs->init_registers(adev);
2320
2321         /* After HDP is initialized, flush HDP.*/
2322         adev->hdp.funcs->flush_hdp(adev, NULL);
2323
2324         if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2325                 value = false;
2326         else
2327                 value = true;
2328
2329         if (!amdgpu_sriov_vf(adev)) {
2330                 if (!adev->in_s0ix)
2331                         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2332                 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2333         }
2334         for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2335                 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2336                         continue;
2337                 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2338         }
2339
2340         if (adev->umc.funcs && adev->umc.funcs->init_registers)
2341                 adev->umc.funcs->init_registers(adev);
2342
2343         r = gmc_v9_0_gart_enable(adev);
2344         if (r)
2345                 return r;
2346
2347         if (amdgpu_emu_mode == 1)
2348                 return amdgpu_gmc_vram_checking(adev);
2349
2350         return 0;
2351 }
2352
2353 /**
2354  * gmc_v9_0_gart_disable - gart disable
2355  *
2356  * @adev: amdgpu_device pointer
2357  *
2358  * This disables all VM page table.
2359  */
2360 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2361 {
2362         if (!adev->in_s0ix)
2363                 adev->gfxhub.funcs->gart_disable(adev);
2364         adev->mmhub.funcs->gart_disable(adev);
2365 }
2366
2367 static int gmc_v9_0_hw_fini(void *handle)
2368 {
2369         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2370
2371         gmc_v9_0_gart_disable(adev);
2372
2373         if (amdgpu_sriov_vf(adev)) {
2374                 /* full access mode, so don't touch any GMC register */
2375                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2376                 return 0;
2377         }
2378
2379         /*
2380          * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2381          * a correct cached state for GMC. Otherwise, the "gate" again
2382          * operation on S3 resuming will fail due to wrong cached state.
2383          */
2384         if (adev->mmhub.funcs->update_power_gating)
2385                 adev->mmhub.funcs->update_power_gating(adev, false);
2386
2387         amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2388
2389         if (adev->gmc.ecc_irq.funcs &&
2390                 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2391                 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2392
2393         return 0;
2394 }
2395
2396 static int gmc_v9_0_suspend(void *handle)
2397 {
2398         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2399
2400         return gmc_v9_0_hw_fini(adev);
2401 }
2402
2403 static int gmc_v9_0_resume(void *handle)
2404 {
2405         int r;
2406         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2407
2408         r = gmc_v9_0_hw_init(adev);
2409         if (r)
2410                 return r;
2411
2412         amdgpu_vmid_reset_all(adev);
2413
2414         return 0;
2415 }
2416
2417 static bool gmc_v9_0_is_idle(void *handle)
2418 {
2419         /* MC is always ready in GMC v9.*/
2420         return true;
2421 }
2422
2423 static int gmc_v9_0_wait_for_idle(void *handle)
2424 {
2425         /* There is no need to wait for MC idle in GMC v9.*/
2426         return 0;
2427 }
2428
2429 static int gmc_v9_0_soft_reset(void *handle)
2430 {
2431         /* XXX for emulation.*/
2432         return 0;
2433 }
2434
2435 static int gmc_v9_0_set_clockgating_state(void *handle,
2436                                         enum amd_clockgating_state state)
2437 {
2438         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2439
2440         adev->mmhub.funcs->set_clockgating(adev, state);
2441
2442         athub_v1_0_set_clockgating(adev, state);
2443
2444         return 0;
2445 }
2446
2447 static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
2448 {
2449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2450
2451         adev->mmhub.funcs->get_clockgating(adev, flags);
2452
2453         athub_v1_0_get_clockgating(adev, flags);
2454 }
2455
2456 static int gmc_v9_0_set_powergating_state(void *handle,
2457                                         enum amd_powergating_state state)
2458 {
2459         return 0;
2460 }
2461
2462 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2463         .name = "gmc_v9_0",
2464         .early_init = gmc_v9_0_early_init,
2465         .late_init = gmc_v9_0_late_init,
2466         .sw_init = gmc_v9_0_sw_init,
2467         .sw_fini = gmc_v9_0_sw_fini,
2468         .hw_init = gmc_v9_0_hw_init,
2469         .hw_fini = gmc_v9_0_hw_fini,
2470         .suspend = gmc_v9_0_suspend,
2471         .resume = gmc_v9_0_resume,
2472         .is_idle = gmc_v9_0_is_idle,
2473         .wait_for_idle = gmc_v9_0_wait_for_idle,
2474         .soft_reset = gmc_v9_0_soft_reset,
2475         .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2476         .set_powergating_state = gmc_v9_0_set_powergating_state,
2477         .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2478 };
2479
2480 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2481         .type = AMD_IP_BLOCK_TYPE_GMC,
2482         .major = 9,
2483         .minor = 0,
2484         .rev = 0,
2485         .funcs = &gmc_v9_0_ip_funcs,
2486 };