drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 #define PHYSTATUS_4_20                          BIT(7)
  39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  40 #define PCS_READY                               BIT(0)
  41
  42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  43 /* DP PHY soft reset */
  44 #define SW_DPPHY_RESET                          BIT(0)
  45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  46 #define SW_DPPHY_RESET_MUX                      BIT(1)
  47 /* USB3 PHY soft reset */
  48 #define SW_USB3PHY_RESET                        BIT(2)
  49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  50 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  51
  52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  53 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  54 #define DP_MODE                                 BIT(1) /* enables DP mode */
  55
  56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  57 #define ARCVR_DTCT_EN                           BIT(0)
  58 #define ALFPS_DTCT_EN                           BIT(1)
  59 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  60
  61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  62 #define IRQ_CLEAR                               BIT(0)
  63
  64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  65 #define RCVR_DETECT                             BIT(0)
  66
  67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  68 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  69
  70 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  71 #define POWER_DOWN_DELAY_US_MIN                 10
  72 #define POWER_DOWN_DELAY_US_MAX                 11
  73
  74 #define MAX_PROP_NAME                           32
  75
  76 /* Define the assumed distance between lanes for underspecified device trees. */
  77 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  78
  79 struct qmp_phy_init_tbl {
  80         unsigned int offset;
  81         unsigned int val;
  82         /*
  83          * register part of layout ?
  84          * if yes, then offset gives index in the reg-layout
  85          */
  86         bool in_layout;
  87         /*
  88          * mask of lanes for which this register is written
  89          * for cases when second lane needs different values
  90          */
  91         u8 lane_mask;
  92 };
  93
  94 #define QMP_PHY_INIT_CFG(o, v)          \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .lane_mask = 0xff,      \
  99         }
 100
 101 #define QMP_PHY_INIT_CFG_L(o, v)        \
 102         {                               \
 103                 .offset = o,            \
 104                 .val = v,               \
 105                 .in_layout = true,      \
 106                 .lane_mask = 0xff,      \
 107         }
 108
 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 110         {                               \
 111                 .offset = o,            \
 112                 .val = v,               \
 113                 .lane_mask = l,         \
 114         }
 115
 116 /* set of registers with offsets different per-PHY */
 117 enum qphy_reg_layout {
 118         /* Common block control registers */
 119         QPHY_COM_SW_RESET,
 120         QPHY_COM_POWER_DOWN_CONTROL,
 121         QPHY_COM_START_CONTROL,
 122         QPHY_COM_PCS_READY_STATUS,
 123         /* PCS registers */
 124         QPHY_PLL_LOCK_CHK_DLY_TIME,
 125         QPHY_FLL_CNTRL1,
 126         QPHY_FLL_CNTRL2,
 127         QPHY_FLL_CNT_VAL_L,
 128         QPHY_FLL_CNT_VAL_H_TOL,
 129         QPHY_FLL_MAN_CODE,
 130         QPHY_SW_RESET,
 131         QPHY_START_CTRL,
 132         QPHY_PCS_READY_STATUS,
 133         QPHY_PCS_STATUS,
 134         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 135         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 136         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 137         QPHY_PCS_POWER_DOWN_CONTROL,
 138         /* PCS_MISC registers */
 139         QPHY_PCS_MISC_TYPEC_CTRL,
 140         /* Keep last to ensure regs_layout arrays are properly initialized */
 141         QPHY_LAYOUT_SIZE
 142 };
 143
 144 static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 145         [QPHY_START_CTRL]               = 0x00,
 146         [QPHY_PCS_READY_STATUS]         = 0x168,
 147 };
 148
 149 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
 150         [QPHY_SW_RESET]                         = 0x00,
 151         [QPHY_START_CTRL]                       = 0x44,
 152         [QPHY_PCS_STATUS]                       = 0x14,
 153         [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
 154 };
 155
 156 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 157         [QPHY_COM_SW_RESET]             = 0x400,
 158         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 159         [QPHY_COM_START_CONTROL]        = 0x408,
 160         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 161         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 162         [QPHY_FLL_CNTRL1]               = 0xc4,
 163         [QPHY_FLL_CNTRL2]               = 0xc8,
 164         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 165         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 166         [QPHY_FLL_MAN_CODE]             = 0xd4,
 167         [QPHY_SW_RESET]                 = 0x00,
 168         [QPHY_START_CTRL]               = 0x08,
 169         [QPHY_PCS_STATUS]               = 0x174,
 170 };
 171
 172 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 173         [QPHY_FLL_CNTRL1]               = 0xc0,
 174         [QPHY_FLL_CNTRL2]               = 0xc4,
 175         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 176         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 177         [QPHY_FLL_MAN_CODE]             = 0xd0,
 178         [QPHY_SW_RESET]                 = 0x00,
 179         [QPHY_START_CTRL]               = 0x08,
 180         [QPHY_PCS_STATUS]               = 0x17c,
 181         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 182         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 183         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 184 };
 185
 186 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 187         [QPHY_SW_RESET]                 = 0x00,
 188         [QPHY_START_CTRL]               = 0x08,
 189         [QPHY_PCS_STATUS]               = 0x174,
 190         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 191         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 192         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 193 };
 194
 195 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 196         [QPHY_SW_RESET]                 = 0x00,
 197         [QPHY_START_CTRL]               = 0x08,
 198         [QPHY_PCS_STATUS]               = 0x174,
 199 };
 200
 201 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 202         [QPHY_SW_RESET]                 = 0x00,
 203         [QPHY_START_CTRL]               = 0x08,
 204         [QPHY_PCS_STATUS]               = 0x2ac,
 205 };
 206
 207 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 208         [QPHY_SW_RESET]                 = 0x00,
 209         [QPHY_START_CTRL]               = 0x44,
 210         [QPHY_PCS_STATUS]               = 0x14,
 211         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 212         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
 213         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
 214 };
 215
 216 static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 217         [QPHY_SW_RESET]                 = 0x00,
 218         [QPHY_START_CTRL]               = 0x44,
 219         [QPHY_PCS_STATUS]               = 0x14,
 220         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 221         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
 222         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
 223 };
 224
 225 static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 226         [QPHY_SW_RESET]                 = 0x00,
 227         [QPHY_START_CTRL]               = 0x44,
 228         [QPHY_PCS_STATUS]               = 0x14,
 229         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 230         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
 231         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
 232 };
 233
 234 static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 235         [QPHY_SW_RESET]                 = 0x00,
 236         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
 237         [QPHY_START_CTRL]               = 0x08,
 238         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
 239         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
 240         [QPHY_PCS_STATUS]               = 0x174,
 241         [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
 242 };
 243
 244 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 245         [QPHY_START_CTRL]               = 0x00,
 246         [QPHY_PCS_READY_STATUS]         = 0x160,
 247 };
 248
 249 static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 250         [QPHY_START_CTRL]               = 0x00,
 251         [QPHY_PCS_READY_STATUS]         = 0x168,
 252 };
 253
 254 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
 255         [QPHY_SW_RESET]                 = 0x00,
 256         [QPHY_START_CTRL]               = 0x44,
 257         [QPHY_PCS_STATUS]               = 0x14,
 258         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 259 };
 260
 261 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 262         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
 263         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
 264         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
 265 };
 266
 267 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 268         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 272         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 278         /* PLL and Loop filter settings */
 279         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 280         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 294         /* SSC settings */
 295         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 302 };
 303
 304 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 305         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 306         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 307         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 308         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 309         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 310         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 311         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 312         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 313         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 314 };
 315
 316 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 326         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 327         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 332         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 333         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 334         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 340 };
 341
 342 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 343         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 355         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 358         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 359         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 360         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 361         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 362         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 363         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 364         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 365         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 366         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 367         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 368         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 369         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 370         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 371         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 372         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 373         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 374         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 375         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 376         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 377         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 378         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 379         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 380         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 381         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 382         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 383         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 384         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 385         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 386 };
 387
 388 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 389         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 390         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 391 };
 392
 393 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 394         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 395         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 396         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 397         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 398         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 399         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 400         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 401         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 402         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 403         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 404 };
 405
 406 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 407         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 408         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 409         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 410
 411         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 412
 413         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 414         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 415         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 416         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 417         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 418 };
 419
 420 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 424         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 425         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 443         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 446         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 447         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 448         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 449         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 450         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 451         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 452         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 453         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 454         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 455         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 456         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 457         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 458         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 459         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 460         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 461         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 462         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 463 };
 464
 465 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 466         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 467         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 468         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 469         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 470 };
 471
 472 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 473         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 474         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 475         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 476         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 477         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 478         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 479         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 480         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 481         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 487 };
 488
 489 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 490         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 491         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 492         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 493         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 494         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 495         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 496         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 497         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 498         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 499         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 500 };
 501
 502 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 503         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 504         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 505         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 506         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 507         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 508         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 509         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 510         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 511         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 512         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 513         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 514         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 515         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 516         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 517         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 518         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 519         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 520         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 521         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 522         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 523         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 524         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 525         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 526         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 527         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 528         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 529         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 530         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 531         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 532         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 533         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 534         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 535         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 536         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 537         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 538         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 539         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 540         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 541         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 542         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 543         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 544         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 545         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 546         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 547         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 548         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 549         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 550 };
 551
 552 static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 553         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 554         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 555 };
 556
 557 static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 558         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 559         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 560         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 561         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 562         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 563         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 564         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 565         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 566         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 567         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 568         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 569 };
 570
 571 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 572         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 573         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 574         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 575         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 576         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 577         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 578         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 579         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 580         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 581         /* PLL and Loop filter settings */
 582         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 583         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 584         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 585         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 586         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 587         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 588         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 589         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 590         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 591         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 592         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 593         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 594         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 595         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 596         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 597         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 598         /* SSC settings */
 599         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 600         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 601         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 602         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 603         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 604         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 605         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 606 };
 607
 608 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 609         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 610         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 611         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 612 };
 613
 614 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 615         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 616         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 617         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 618         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 619         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 620         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 621         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 622         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 623         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 624         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 625 };
 626
 627 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 628         /* FLL settings */
 629         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 630         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 631         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 632         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 633         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 634
 635         /* Lock Det settings */
 636         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 637         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 638         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 639         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 640 };
 641
 642 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
 643         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 644         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 645         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 646         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 647         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 648         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 649         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 650         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 651         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 652         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 653         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 654         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 655         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 656         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 657         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 658         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 659         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 660         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 661         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 662         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 663         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 664         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 665         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 666         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 667         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 668         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 669         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 670         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 671         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 672         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 673         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 674         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 675         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 676         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 677         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 678         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 679         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 680         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 681         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 682         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 683         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 684         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 685         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 686         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 687         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 688         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 689 };
 690
 691 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
 692         QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
 693         QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
 694         QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
 695 };
 696
 697 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
 698         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
 699         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
 700         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 701         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
 702         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 703         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 704         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 705         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
 706         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
 707         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 708         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 709         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
 710         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
 711         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
 712         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
 713         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
 714         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
 715         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
 716         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
 717         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
 718         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
 719         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
 720         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
 721         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
 722         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
 723         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
 724         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
 725         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
 726         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
 727         QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
 728 };
 729
 730 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 731         QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
 732         QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
 733         QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
 734         QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
 735         QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 736         QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
 737         QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
 738         QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 739         QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 740         QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 741         QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 742         QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 743         QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 744         QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
 745         QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
 746         QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
 747 };
 748
 749 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 750         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 751         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 752         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 753         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 754         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 755         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 756         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 757         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 758         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 759         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 760         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 761         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 762         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 763         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 764         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 765         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 766         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 767         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 768         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 769         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 770         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 771         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 772         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 773         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 774         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 775         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 776         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 777         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 778         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 779         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 780         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 781         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 782         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 783         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 784         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 785         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 786         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 787         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 788         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 789         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 790 };
 791
 792 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 793         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 794         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 795         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 796         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 797         QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 798         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 799 };
 800
 801 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 802         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 803         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 804         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 805         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 806         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 807         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 808         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 809 };
 810
 811 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 812         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 813         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 814         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 815         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 816         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 817         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 818         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 819         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 820         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 821         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 822         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 823         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 824         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 825 };
 826
 827 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 828         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 829         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 830         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 831         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 832         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 833         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 834         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 835         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 836         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 837         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 838         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 839         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 840         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 841         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 842         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 843         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 844         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 845         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 846         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 847         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 848         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 849         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 850         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 851         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 852         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 853         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 854         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 855         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 856         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 857         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 858         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 859         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 860         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 861         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 862         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 863         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 864         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 865         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 866         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 867         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 868         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 869         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 870 };
 871
 872 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 873         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 874         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 875         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 876         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 877 };
 878
 879 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 880         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 881         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 882         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 883         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 884         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 885         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 886         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 887         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 888         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 889         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 890         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 891         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 892         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 893         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 894         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 895         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 896 };
 897
 898 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 899         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 900
 901         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 902         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 903         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 904         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 905         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 906
 907         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 908         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 909         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 910         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 911         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 912         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 913         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 914
 915         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 916         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 917         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 918
 919         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 920 };
 921
 922 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 923         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 924         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 925         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 926         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 927         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 928 };
 929
 930 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 931         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 932         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 933         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 934         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 935         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 936         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 937         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 938         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 939         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 940         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 941         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 942         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 943         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 944         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 945         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 946         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 947         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 948         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 949         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 950         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 951         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 952         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 953         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 954         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 955         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 956         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 957         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 958         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 959         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 960         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 961         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 962         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 963         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 964         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 965         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 966         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 967         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 968         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 969         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 970         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 971         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 972         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 973         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 974         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 975         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 976 };
 977
 978 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 979         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 980         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 981         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 982         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 983         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 984         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 985         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 986         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 987         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 988         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 989         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 990         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 991         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 992         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 993         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 994         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 995         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 996         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 997         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 998         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 999         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1000         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
1001         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1002         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1003         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1004         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1005         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1006         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1007         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1008         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1009         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1010         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1011         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1012         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1013         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1014         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1015         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1016         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1017         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1018         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1019         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1020         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1021         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1022         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1023         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1024         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1025         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1026         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1027         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1028         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1029         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1030         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1031         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1032         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1033         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1034         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1035 };
1036
1037 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1038 };
1039
1040 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1041         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1042         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1043         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1044         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1045         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1046         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1047         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1048 };
1049
1050 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1051         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1052         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1053         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1054         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1055         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1056         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1057         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1058         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1059         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1060         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1061         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1062         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1063         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1064         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1065         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1066         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1067         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1068         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1069         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1070         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1071         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1072         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1073         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1074         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1075         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1076         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1077         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1078         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1079         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1080         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1081         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1082         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1083         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1084         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1085         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1086         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1087 };
1088
1089 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1090         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1091         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1092         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1093         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1094         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1095 };
1096
1097 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1098         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1099         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1100         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1101         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1102         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1103         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1104         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1105         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1106         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1107         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1108         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1109         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1110         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1111         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1112         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1113         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1114         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1115         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1116         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1117         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1118         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1119 };
1120
1121 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1129 };
1130
1131 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1139 };
1140
1141 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1149 };
1150
1151 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1157         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1159 };
1160
1161 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1162         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1163         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1164         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1165         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1166         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1167         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1168         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1169         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1170         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1171         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1172         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1173         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1174         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1175         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1176         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1177 };
1178
1179 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1180         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1181         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1182         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1183         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1184         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1185         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1186         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1187         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1188         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1189 };
1190
1191 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1192         /* FLL settings */
1193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1195         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1196         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1197         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1198
1199         /* Lock Det settings */
1200         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1201         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1202         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1203         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1204
1205         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1206         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1207         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1208         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1209         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1210         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1211         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1212         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1213         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1214         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1215         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1216         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1217         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1218         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1219         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1220         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1221         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1222         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1223         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1224
1225         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1226         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1227         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1228         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1229         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1230         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1231         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1232         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1233         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1234         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1235         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1236 };
1237
1238 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1239         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1240         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1241         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1242         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1243         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1244         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1245         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1246         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1252         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1253         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1254         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1255         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1256         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1257         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1258         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1259         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1260         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1261         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1262         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1263         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1264         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1265         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1266         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1267         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1268         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1269         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1275 };
1276
1277 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1278         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1279         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1280         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1281         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1282         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1283 };
1284
1285 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1286         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1287         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1288         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1289         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1290         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1291         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1292         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1293         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1294         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1295         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1296         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1297 };
1298
1299 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1300         /* FLL settings */
1301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1306
1307         /* Lock Det settings */
1308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1309         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1310         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1311         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1312
1313         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1314         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1315         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1326         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1327         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1332
1333         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1334         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1340         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1341         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1342         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1343         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1344
1345         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1346         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1347 };
1348
1349 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1350         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1351         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1352         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1353         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1354         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1355         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1356         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1357         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1358         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1359         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1360         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1361         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1362         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1363         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1364         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1365         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1366         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1367         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1368         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1369         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1370         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1371         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1372         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1373         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1374         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1375         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1376         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1377         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1378         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1379         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1380         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1381         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1382         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1383         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1384         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1385         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1386         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1387         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1388         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1389         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1390         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1391         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1392         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1393         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1394         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1395         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1396         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1397         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1398         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1399         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1400
1401         /* Rate B */
1402         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1403 };
1404
1405 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1406         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1407         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1408 };
1409
1410 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1411         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1412         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1413         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1414         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1415         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1416         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1417         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1418         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1419         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1420         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1421         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1422         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1423         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1424         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1425         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1426 };
1427
1428 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1429         QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1430         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1431         QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1432         QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1433         QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1434         QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1435         QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1436         QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1437         QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1438 };
1439
1440 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1441         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1442         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1443         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1444         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1445         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1446         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1447         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1448         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1449         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1450         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1451         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1452         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1453         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1454         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1455         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1456         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1457         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1458         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1459         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1460         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1461         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1462         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1463         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1464         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1465         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1466         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1467         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1468         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1469         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1470         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1471         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1472         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1473         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1474         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1475         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1476         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1477
1478         /* Rate B */
1479         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1480 };
1481
1482 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1483         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1484         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1485         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1486 };
1487
1488 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1489         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1490         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1491         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1492         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1493         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1494         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1495         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1496         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1497         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1498         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1499         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1500         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1501         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1502         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1503         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1504         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1505 };
1506
1507 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1508         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1509         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1510         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1511         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1512         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1513         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1514         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1515         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1516 };
1517
1518 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1529         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1530         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1531         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1532         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1533         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1534         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1535         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1536         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1537         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1538         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1539         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1540         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1541         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1542         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1543         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1544         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1545         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1546         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1547         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1548         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1549         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1550         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1551         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1552         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1553         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1554         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1555         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1556         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1557 };
1558
1559 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1560         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1561         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1562         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1563         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1564 };
1565
1566 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1567         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1568         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1569         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1570         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1571         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1572         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1573         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1574         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1575         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1576         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1577         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1578         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1579         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1580         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1581         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1582         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1583         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1584 };
1585
1586 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1587         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1588         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1589         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1591         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1595         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1597         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1598         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1600         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1601         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1602         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1603         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1604         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1605         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1606         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1607         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1608         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1609         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1610         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1611         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1612         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1613         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1614         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1615         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1616         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1617         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1618         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1619         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1620         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1621         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1622         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1623         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1624         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1625 };
1626
1627 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1628         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1629         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1630         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1631         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1632         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1633         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1634         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1635         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1636         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1637         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1638         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1639         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1640         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1641         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1642         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1643         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1644         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1645         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1646         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1647         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1648         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1649         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1650         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1651         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1652
1653         /* Rate B */
1654         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1655 };
1656
1657 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1658         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1659         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1660         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1661         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1662         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1663         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1664 };
1665
1666 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1667         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1668         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1669         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1670         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1671         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1672         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1673         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1674         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1675         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1676         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1677         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1678         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1679         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1680         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1681         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1682         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1683         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1684         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1685         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1686         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1687         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1688         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1689         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1690         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1691         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1692         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1693         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1694         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1695         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1696         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1697         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1698         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1699         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1700         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1701
1702 };
1703
1704 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1706         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1707         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1708         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1709         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1710         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1711         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1712 };
1713
1714 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1715         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1716         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1717         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1718         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1719         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1720         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1721         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1722         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1723         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1724         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1725         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1726         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1727         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1728         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1729         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1730         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1731         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1732         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1733         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1734         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1735         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1736         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1737         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1738         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1739         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1740         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1741         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1742         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1743         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1744         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1745         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1746         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1747         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1748         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1749         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1750         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1751         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1752         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1753         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1754         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1755 };
1756
1757 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1758         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1759         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1760         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1761         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1762         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1763 };
1764
1765 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1766         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1767         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1768         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1769         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1770         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1771         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1772         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1773         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1774         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1775         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1776         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1777         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1778         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1779         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1780         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1781         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1782         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1783         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1784         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1785         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1786         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1787         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1788         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1789         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1790         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1791         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1792         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1793         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1794         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1795         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1796         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1797         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1798         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1799         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1800         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1801         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1802 };
1803
1804 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1805         /* Lock Det settings */
1806         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1807         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1808         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1809
1810         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1811         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1812         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1813         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1814         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1815         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1816         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1817         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1818         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1819         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1820 };
1821
1822 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1823         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1824         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1825         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1826         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1827         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1828         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1829         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1830         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1831         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1832         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1833         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1834         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1835         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1836         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1837         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1838         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1839         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1840         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1841         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1842         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1843         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1844         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1845         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1846         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1847         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1848         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1849         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1850         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1851         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1852         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1853         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1854         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1855         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1856         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1857         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1858         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1859         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1860         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1861         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1862         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1863 };
1864
1865 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1866         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1867         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1868         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1869         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1870 };
1871
1872 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1873         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1874         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1875         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1876         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1877         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1878         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1879         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1880         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1881         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1882         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1883         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1884         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1885         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1886         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1887         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1888         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1889         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1890         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1891         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1892         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1893         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1894         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1895         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1896         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1897         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1898         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1899         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1900         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1901         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1902         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1903         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1904         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1905         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1906         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1907         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1908         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1909 };
1910
1911 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1912         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1913         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1914         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1915         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1916         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1917         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1918         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1919         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1920         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1921         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1922         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1923         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1924         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1925         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1926         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1927         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1928 };
1929
1930 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1931         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1932         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1933         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1934         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1935         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1936         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1937         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1938         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1939 };
1940
1941 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1942         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1943         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1944         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1945         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1946         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1947         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1948         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1949         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1950         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1951         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1952         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1953         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1954         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1955         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1956         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1957         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1958         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1959         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1960         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1961         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1962         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1963         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1964         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1965         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1966         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1967         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1968         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1969         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1970         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1971         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1972         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1973         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1974         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1975         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1976         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1977         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1978         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1979         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1980 };
1981
1982 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1983         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1984         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1985         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1986         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1987         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1988         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1989         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1990         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1991         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1992         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1993         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1994         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1995         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1996         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1997 };
1998
1999 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
2000         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2001         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2002         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
2003         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
2004         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2005         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
2006 };
2007
2008 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
2009         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
2010         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
2011         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2012         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2013         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2014         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2015         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2016         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2017         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2018         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2019         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2020         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
2021         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2022         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
2023         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
2024         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2025         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2026         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2027         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2028         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
2029         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2030         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2031         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2032         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2033         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2034         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2035         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2036         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2037         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2038         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2039         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2040         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2041         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2042         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
2043         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2044         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2045 };
2046
2047 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
2048         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2049         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2050         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2051         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2052         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2053         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2054         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
2055         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2056         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2057         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2058         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2059         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2060         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2061         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2062         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2063         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2064 };
2065
2066 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
2067         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
2068         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
2069         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
2070         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
2071         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
2072         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
2073         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2074         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2075         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2076         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2077         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
2078         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
2079         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2080         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
2081         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
2082         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
2083         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
2084         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
2085         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
2086         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
2087 };
2088
2089 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
2090         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
2091         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2092         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2093         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2094         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
2095         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
2096         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
2097 };
2098
2099 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
2100         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
2101         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2102         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2103         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2104         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
2105         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
2106         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2107 };
2108
2109 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2110         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2111         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2112         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2113         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2114         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2115         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2116         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2117 };
2118
2119 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2120         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2121         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2122         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2123         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2124         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2125         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2126         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2127 };
2128
2129 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2130         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2131         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2132         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2133         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2134         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2135         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2136         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2137         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2138         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2139         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2140         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2141         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2142         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2143         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2144 };
2145
2146 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
2147         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2148         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2149         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2150         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2151         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2152         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2153         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2154         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2155         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2156         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2157         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2158         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2159         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2160         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2161         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2162         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2163         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2164         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2165         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2166         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2167         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2168         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2169         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2170         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2171         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2172         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2173         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2174         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2175         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2176         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2177         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2178         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2179         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2180         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2181         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2182         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2183         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2184         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2185         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2186         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2187         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2188         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2189 };
2190
2191 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
2192         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2193         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
2194 };
2195
2196 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
2197         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2198         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2199         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
2200         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
2201         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
2202         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
2203         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
2204         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2205         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2206         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2207         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2208         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2209         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
2210         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2211         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2212         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2213         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
2214         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2215         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2216         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2217         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2218         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
2219         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2220         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2221         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
2222         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2223         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
2224         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
2225         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2226         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2227         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2228         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
2229         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2230         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
2231         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2232         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2233 };
2234
2235 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
2236         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2237         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2238         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2239         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2240         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
2241 };
2242
2243 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
2244         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2245         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2246         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2247         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2248         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2249         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2250         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2251 };
2252
2253 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2254         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2255         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2256         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2257         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2258         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2259         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2260         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2261         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2262         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2263         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2264         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2265         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2266         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2267         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2268         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2269         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2270         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2271         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2272         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2273         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2274         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2275         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2276         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2277         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2278         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2279         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2280         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2281         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2282         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2283         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2284         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2285         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2286         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2287         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2288         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2289         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2290         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2291         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2292         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2293         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2294         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2295 };
2296
2297 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2298         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2299 };
2300
2301 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2302         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2303         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2304         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2305 };
2306
2307 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2308         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2309         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2310         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2311         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2312         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2313         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2314         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2315         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2316         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2317         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2318         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2319         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2320         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2321         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2322         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2323         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2324         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2325         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2326         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2327         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2328         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2329         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2330         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2331         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2332         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2333         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2334         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2335         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2336         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2337         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2338 };
2339
2340 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2341         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2342         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2343         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2344         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2345         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2346         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2347 };
2348
2349 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2350         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2351         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2352         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2353 };
2354
2355 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2356         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2357         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2358 };
2359
2360 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2361         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2362         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2363         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2364         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2365         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2366         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2367         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2368 };
2369
2370 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2371         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2372         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2373 };
2374
2375 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2376         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2377 };
2378
2379 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2380         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2381         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2382         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2383         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2384 };
2385
2386 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2387         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2388         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2389 };
2390
2391 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2392         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2393         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2394 };
2395
2396 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2397         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2398         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2399         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2400         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2401         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2402 };
2403
2404 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2405         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2406         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2407         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2408         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2409         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2410         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2411         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2412         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2413         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2414         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2415         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2416         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2417         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2418         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2419         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2420         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2421         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2422         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2423         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2424         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2425         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2426         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2427         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2428         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2429         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2430         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2431         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2432         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2433         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2434         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2435         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2436         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2437         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2438         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2439         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2440         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2441 };
2442
2443 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2444         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2445         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2446         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2447         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2448         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2449         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2450         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2451         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2452         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2453         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2454         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2455         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2456         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2457         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2458         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2459         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2460         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2461         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2462         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2463         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2464         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2465         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2466         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2467         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2468         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2469         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2470         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2471         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2472         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2473         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2474         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2475         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2476         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2477         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2483 };
2484
2485 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2486         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2487         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2488         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2489         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2490         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2491 };
2492
2493 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2494         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2495         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2496         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2497         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2498         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2499         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2500         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2501         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2502         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2503         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2504         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2505         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2506         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2507         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2508         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2509         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2510         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2511         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2512         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2513         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2514         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2515         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2516         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2517         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2518         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2519 };
2520
2521 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2522         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2523         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2524         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2525         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2526 };
2527
2528 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2529         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2530         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2531         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2532         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2533         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2534         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2535         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2536 };
2537
2538 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2539         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2540         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2541         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2542         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2543         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2544         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2545         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2546         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2547         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2548         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2549         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2550         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2551         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2552         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2553         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2554         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2555         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2556         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2557         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2558         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2559         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2560         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2561         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2562         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2563
2564         /* Rate B */
2565         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2566 };
2567
2568 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2569         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2570         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2571         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2572         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2573         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2574         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2575         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2576         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2577         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2578 };
2579
2580 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2581         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2582         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2583         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2584         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2585         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2586         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2587         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2588         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2589         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2590         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2591         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2592         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2593         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2594         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2595         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2596         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2597         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2598         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2599         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2600         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2601         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2602         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2603         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2604         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2605         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2606         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2607         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2608         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2609         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2610         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2611         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2612         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2613         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2614         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2615         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2616         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2617         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2618 };
2619
2620 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2621         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2622         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2623         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2624         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2625         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2626         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2627         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2628         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2629         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2630         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2631         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2632         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2633         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2634         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2635         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2636 };
2637
2638 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2639         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2640         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2641         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2642         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2643         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2644         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2645         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2646         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2647         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2648         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2649 };
2650
2651 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2652         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2653         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2654         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2655         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2656         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2657         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2658         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2659         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2660         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2661         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2662         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2663         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2664         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2665         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2666         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2667         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2668         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2669         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2670         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2671         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2672         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2676         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2677         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2688         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2689         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2690 };
2691
2692 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2693         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2694         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2695         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2696         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2697         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2698         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2699         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2700         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2701         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2702         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2703         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2704         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2706         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2707         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2708         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2709         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2710         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2711 };
2712
2713 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2714         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2715         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2716         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2717         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2718         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2719         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2720         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2721 };
2722
2723 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2724         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2725         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2726         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2727         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2728         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2729         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2730         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2731         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2732         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2733         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2734         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2735         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2736         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2737         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2738         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2739         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2740         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2741         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2742         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2743         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2744         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2745         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2746         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2747         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2748         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2749         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2750         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2751         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2752         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2753         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2754         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2755 };
2756
2757 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2758         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2759         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2760         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2761         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2762         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2763         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2764         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2765         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2766         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2767         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2768         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2769         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2770         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2771         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2772         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2773         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2774 };
2775
2776 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
2777         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
2778         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
2779         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
2780         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
2781         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
2782         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
2783         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
2784         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
2785         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
2786         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
2787         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
2788         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
2789         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
2790         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
2791         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
2792         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
2793         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
2794         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2795         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
2796         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
2797         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
2798         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
2799         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
2800         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
2801         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
2802         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
2803         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
2804         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
2805         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
2806         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
2807         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
2808         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
2809         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
2810         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
2811         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
2812         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
2813         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
2814         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
2815 };
2816
2817 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
2818         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
2819         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
2820         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
2821         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
2822         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
2823 };
2824
2825 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
2826         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
2827         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
2828         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
2829         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
2830         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
2831         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
2832         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
2833         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
2834         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
2835         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
2836         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
2837         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2838         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
2839         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
2840         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
2841         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
2842         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
2843 };
2844
2845 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
2846         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
2847         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
2848         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
2849         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
2850         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
2851         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
2852         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
2853         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
2854         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
2855         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
2856         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
2857         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
2858         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
2859         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
2860         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
2861         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
2862         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2863         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2864         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
2865         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
2866         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
2867 };
2868
2869 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
2870         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2871         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2872         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
2873         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2874         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2875         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
2876         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
2877         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
2878         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2879         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2880         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2881         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2882         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2883         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2884         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2885         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2886         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
2887         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
2888         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
2889         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
2890         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2891         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2892         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
2893         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2894         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2895         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2896         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2897         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2898         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2899         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2900         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2901         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2902         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2903         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
2904         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
2905         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2906         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2907         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2908         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2909         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2910         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2911         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2912 };
2913
2914 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
2915         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
2916         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
2917         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2918         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2919         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
2920 };
2921
2922 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
2923         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
2924         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
2925         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
2926         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
2927         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
2928         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
2929         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
2930         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
2931         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
2932         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
2933         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
2934         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
2935         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
2936         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2937         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2938         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2939         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
2940         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2941         QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
2942         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
2943         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
2944         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2945 };
2946
2947 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
2948         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
2949         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
2950         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
2951 };
2952
2953 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2954         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2955         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2956         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
2957         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2958 };
2959
2960 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
2961         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2962         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2963         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2964         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2965         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2966         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2967         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
2968         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2969         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2970         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2971         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2972         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2973         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2974         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2975         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2976         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2977         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2978         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2979         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2980         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2981         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2982         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2983         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2984         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2985         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2986         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2987         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2988         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2989         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2990         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2991         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2992         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2993         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2994         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2995         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2996         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2997         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2998         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
2999         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
3000         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
3001         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
3002 };
3003
3004 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
3005         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
3006         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
3007         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
3008         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
3009 };
3010
3011 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
3012         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
3013         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
3014         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
3015         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
3016         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
3017         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
3018         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
3019         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
3020         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
3021         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
3022         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
3023         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
3024         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
3025         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
3026         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
3027         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
3028         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
3029         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
3030         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
3031         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
3032         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
3033         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
3034         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
3035         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
3036
3037         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
3038
3039         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
3040
3041         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
3042         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
3043         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
3044         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
3045         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
3046         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
3047         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
3048         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
3049
3050         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
3051         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
3052         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
3053         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
3054         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
3055         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
3056         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
3057         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
3058         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
3059 };
3060
3061 /* Register names should be validated, they might be different for this PHY */
3062 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
3063         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16),
3064         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22),
3065         QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e),
3066         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99),
3067 };
3068
3069 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
3070         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
3071         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
3072         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
3073         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
3074         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
3075         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
3076 };
3077
3078 struct qmp_phy;
3079
3080 /* struct qmp_phy_cfg - per-PHY initialization config */
3081 struct qmp_phy_cfg {
3082         /* phy-type - PCIE/UFS/USB */
3083         unsigned int type;
3084         /* number of lanes provided by phy */
3085         int nlanes;
3086
3087         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
3088         const struct qmp_phy_init_tbl *serdes_tbl;
3089         int serdes_tbl_num;
3090         const struct qmp_phy_init_tbl *serdes_tbl_sec;
3091         int serdes_tbl_num_sec;
3092         const struct qmp_phy_init_tbl *tx_tbl;
3093         int tx_tbl_num;
3094         const struct qmp_phy_init_tbl *tx_tbl_sec;
3095         int tx_tbl_num_sec;
3096         const struct qmp_phy_init_tbl *rx_tbl;
3097         int rx_tbl_num;
3098         const struct qmp_phy_init_tbl *rx_tbl_sec;
3099         int rx_tbl_num_sec;
3100         const struct qmp_phy_init_tbl *pcs_tbl;
3101         int pcs_tbl_num;
3102         const struct qmp_phy_init_tbl *pcs_tbl_sec;
3103         int pcs_tbl_num_sec;
3104         const struct qmp_phy_init_tbl *pcs_misc_tbl;
3105         int pcs_misc_tbl_num;
3106         const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
3107         int pcs_misc_tbl_num_sec;
3108
3109         /* Init sequence for DP PHY block link rates */
3110         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
3111         int serdes_tbl_rbr_num;
3112         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
3113         int serdes_tbl_hbr_num;
3114         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
3115         int serdes_tbl_hbr2_num;
3116         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
3117         int serdes_tbl_hbr3_num;
3118
3119         /* DP PHY callbacks */
3120         int (*configure_dp_phy)(struct qmp_phy *qphy);
3121         void (*configure_dp_tx)(struct qmp_phy *qphy);
3122         int (*calibrate_dp_phy)(struct qmp_phy *qphy);
3123         void (*dp_aux_init)(struct qmp_phy *qphy);
3124
3125         /* clock ids to be requested */
3126         const char * const *clk_list;
3127         int num_clks;
3128         /* resets to be requested */
3129         const char * const *reset_list;
3130         int num_resets;
3131         /* regulators to be requested */
3132         const char * const *vreg_list;
3133         int num_vregs;
3134
3135         /* array of registers with different offsets */
3136         const unsigned int *regs;
3137
3138         unsigned int start_ctrl;
3139         unsigned int pwrdn_ctrl;
3140         unsigned int mask_com_pcs_ready;
3141         /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
3142         unsigned int phy_status;
3143
3144         /* true, if PHY has a separate PHY_COM control block */
3145         bool has_phy_com_ctrl;
3146         /* true, if PHY has a reset for individual lanes */
3147         bool has_lane_rst;
3148         /* true, if PHY needs delay after POWER_DOWN */
3149         bool has_pwrdn_delay;
3150         /* power_down delay in usec */
3151         int pwrdn_delay_min;
3152         int pwrdn_delay_max;
3153
3154         /* true, if PHY has a separate DP_COM control block */
3155         bool has_phy_dp_com_ctrl;
3156         /* true, if PHY has secondary tx/rx lanes to be configured */
3157         bool is_dual_lane_phy;
3158
3159         /* true, if PCS block has no separate SW_RESET register */
3160         bool no_pcs_sw_reset;
3161 };
3162
3163 struct qmp_phy_combo_cfg {
3164         const struct qmp_phy_cfg *usb_cfg;
3165         const struct qmp_phy_cfg *dp_cfg;
3166 };
3167
3168 /**
3169  * struct qmp_phy - per-lane phy descriptor
3170  *
3171  * @phy: generic phy
3172  * @cfg: phy specific configuration
3173  * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
3174  * @tx: iomapped memory space for lane's tx
3175  * @rx: iomapped memory space for lane's rx
3176  * @pcs: iomapped memory space for lane's pcs
3177  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
3178  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
3179  * @pcs_misc: iomapped memory space for lane's pcs_misc
3180  * @pipe_clk: pipe lock
3181  * @index: lane index
3182  * @qmp: QMP phy to which this lane belongs
3183  * @lane_rst: lane's reset controller
3184  * @mode: current PHY mode
3185  * @dp_aux_cfg: Display port aux config
3186  * @dp_opts: Display port optional config
3187  * @dp_clks: Display port clocks
3188  */
3189 struct qmp_phy {
3190         struct phy *phy;
3191         const struct qmp_phy_cfg *cfg;
3192         void __iomem *serdes;
3193         void __iomem *tx;
3194         void __iomem *rx;
3195         void __iomem *pcs;
3196         void __iomem *tx2;
3197         void __iomem *rx2;
3198         void __iomem *pcs_misc;
3199         struct clk *pipe_clk;
3200         unsigned int index;
3201         struct qcom_qmp *qmp;
3202         struct reset_control *lane_rst;
3203         enum phy_mode mode;
3204         unsigned int dp_aux_cfg;
3205         struct phy_configure_opts_dp dp_opts;
3206         struct qmp_phy_dp_clks *dp_clks;
3207 };
3208
3209 struct qmp_phy_dp_clks {
3210         struct qmp_phy *qphy;
3211         struct clk_hw dp_link_hw;
3212         struct clk_hw dp_pixel_hw;
3213 };
3214
3215 /**
3216  * struct qcom_qmp - structure holding QMP phy block attributes
3217  *
3218  * @dev: device
3219  * @dp_com: iomapped memory space for phy's dp_com control block
3220  *
3221  * @clks: array of clocks required by phy
3222  * @resets: array of resets required by phy
3223  * @vregs: regulator supplies bulk data
3224  *
3225  * @phys: array of per-lane phy descriptors
3226  * @phy_mutex: mutex lock for PHY common block initialization
3227  * @init_count: phy common block initialization count
3228  * @ufs_reset: optional UFS PHY reset handle
3229  */
3230 struct qcom_qmp {
3231         struct device *dev;
3232         void __iomem *dp_com;
3233
3234         struct clk_bulk_data *clks;
3235         struct reset_control **resets;
3236         struct regulator_bulk_data *vregs;
3237
3238         struct qmp_phy **phys;
3239
3240         struct mutex phy_mutex;
3241         int init_count;
3242
3243         struct reset_control *ufs_reset;
3244 };
3245
3246 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
3247 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
3248 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
3249 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
3250
3251 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
3252 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
3253 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
3254 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
3255
3256 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3257 {
3258         u32 reg;
3259
3260         reg = readl(base + offset);
3261         reg |= val;
3262         writel(reg, base + offset);
3263
3264         /* ensure that above write is through */
3265         readl(base + offset);
3266 }
3267
3268 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3269 {
3270         u32 reg;
3271
3272         reg = readl(base + offset);
3273         reg &= ~val;
3274         writel(reg, base + offset);
3275
3276         /* ensure that above write is through */
3277         readl(base + offset);
3278 }
3279
3280 /* list of clocks required by phy */
3281 static const char * const msm8996_phy_clk_l[] = {
3282         "aux", "cfg_ahb", "ref",
3283 };
3284
3285 static const char * const msm8996_ufs_phy_clk_l[] = {
3286         "ref",
3287 };
3288
3289 static const char * const qmp_v3_phy_clk_l[] = {
3290         "aux", "cfg_ahb", "ref", "com_aux",
3291 };
3292
3293 static const char * const sdm845_pciephy_clk_l[] = {
3294         "aux", "cfg_ahb", "ref", "refgen",
3295 };
3296
3297 static const char * const qmp_v4_phy_clk_l[] = {
3298         "aux", "ref_clk_src", "ref", "com_aux",
3299 };
3300
3301 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
3302 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
3303         "aux", "ref_clk_src", "com_aux"
3304 };
3305
3306 static const char * const sm8450_ufs_phy_clk_l[] = {
3307         "qref", "ref", "ref_aux",
3308 };
3309
3310 static const char * const sdm845_ufs_phy_clk_l[] = {
3311         "ref", "ref_aux",
3312 };
3313
3314 /* usb3 phy on sdx55 doesn't have com_aux clock */
3315 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
3316         "aux", "cfg_ahb", "ref"
3317 };
3318
3319 static const char * const qcm2290_usb3phy_clk_l[] = {
3320         "cfg_ahb", "ref", "com_aux",
3321 };
3322
3323 /* list of resets */
3324 static const char * const msm8996_pciephy_reset_l[] = {
3325         "phy", "common", "cfg",
3326 };
3327
3328 static const char * const msm8996_usb3phy_reset_l[] = {
3329         "phy", "common",
3330 };
3331
3332 static const char * const sc7180_usb3phy_reset_l[] = {
3333         "phy",
3334 };
3335
3336 static const char * const qcm2290_usb3phy_reset_l[] = {
3337         "phy_phy", "phy",
3338 };
3339
3340 static const char * const sdm845_pciephy_reset_l[] = {
3341         "phy",
3342 };
3343
3344 /* list of regulators */
3345 static const char * const qmp_phy_vreg_l[] = {
3346         "vdda-phy", "vdda-pll",
3347 };
3348
3349 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
3350         .type                   = PHY_TYPE_USB3,
3351         .nlanes                 = 1,
3352
3353         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
3354         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
3355         .tx_tbl                 = msm8996_usb3_tx_tbl,
3356         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3357         .rx_tbl                 = ipq8074_usb3_rx_tbl,
3358         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
3359         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
3360         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
3361         .clk_list               = msm8996_phy_clk_l,
3362         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3363         .reset_list             = msm8996_usb3phy_reset_l,
3364         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3365         .vreg_list              = qmp_phy_vreg_l,
3366         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3367         .regs                   = usb3phy_regs_layout,
3368
3369         .start_ctrl             = SERDES_START | PCS_START,
3370         .pwrdn_ctrl             = SW_PWRDN,
3371         .phy_status             = PHYSTATUS,
3372 };
3373
3374 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
3375         .type                   = PHY_TYPE_PCIE,
3376         .nlanes                 = 3,
3377
3378         .serdes_tbl             = msm8996_pcie_serdes_tbl,
3379         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
3380         .tx_tbl                 = msm8996_pcie_tx_tbl,
3381         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
3382         .rx_tbl                 = msm8996_pcie_rx_tbl,
3383         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
3384         .pcs_tbl                = msm8996_pcie_pcs_tbl,
3385         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
3386         .clk_list               = msm8996_phy_clk_l,
3387         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3388         .reset_list             = msm8996_pciephy_reset_l,
3389         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
3390         .vreg_list              = qmp_phy_vreg_l,
3391         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3392         .regs                   = pciephy_regs_layout,
3393
3394         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
3395         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3396         .mask_com_pcs_ready     = PCS_READY,
3397         .phy_status             = PHYSTATUS,
3398
3399         .has_phy_com_ctrl       = true,
3400         .has_lane_rst           = true,
3401         .has_pwrdn_delay        = true,
3402         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3403         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3404 };
3405
3406 static const struct qmp_phy_cfg msm8996_ufs_cfg = {
3407         .type                   = PHY_TYPE_UFS,
3408         .nlanes                 = 1,
3409
3410         .serdes_tbl             = msm8996_ufs_serdes_tbl,
3411         .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
3412         .tx_tbl                 = msm8996_ufs_tx_tbl,
3413         .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
3414         .rx_tbl                 = msm8996_ufs_rx_tbl,
3415         .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
3416
3417         .clk_list               = msm8996_ufs_phy_clk_l,
3418         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
3419
3420         .vreg_list              = qmp_phy_vreg_l,
3421         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3422
3423         .regs                   = msm8996_ufsphy_regs_layout,
3424
3425         .start_ctrl             = SERDES_START,
3426         .pwrdn_ctrl             = SW_PWRDN,
3427         .phy_status             = PHYSTATUS,
3428
3429         .no_pcs_sw_reset        = true,
3430 };
3431
3432 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
3433         .type                   = PHY_TYPE_USB3,
3434         .nlanes                 = 1,
3435
3436         .serdes_tbl             = msm8996_usb3_serdes_tbl,
3437         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
3438         .tx_tbl                 = msm8996_usb3_tx_tbl,
3439         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3440         .rx_tbl                 = msm8996_usb3_rx_tbl,
3441         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
3442         .pcs_tbl                = msm8996_usb3_pcs_tbl,
3443         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
3444         .clk_list               = msm8996_phy_clk_l,
3445         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3446         .reset_list             = msm8996_usb3phy_reset_l,
3447         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3448         .vreg_list              = qmp_phy_vreg_l,
3449         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3450         .regs                   = usb3phy_regs_layout,
3451
3452         .start_ctrl             = SERDES_START | PCS_START,
3453         .pwrdn_ctrl             = SW_PWRDN,
3454         .phy_status             = PHYSTATUS,
3455 };
3456
3457 static const char * const ipq8074_pciephy_clk_l[] = {
3458         "aux", "cfg_ahb",
3459 };
3460 /* list of resets */
3461 static const char * const ipq8074_pciephy_reset_l[] = {
3462         "phy", "common",
3463 };
3464
3465 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3466         .type                   = PHY_TYPE_PCIE,
3467         .nlanes                 = 1,
3468
3469         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
3470         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3471         .tx_tbl                 = ipq8074_pcie_tx_tbl,
3472         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3473         .rx_tbl                 = ipq8074_pcie_rx_tbl,
3474         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3475         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
3476         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3477         .clk_list               = ipq8074_pciephy_clk_l,
3478         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3479         .reset_list             = ipq8074_pciephy_reset_l,
3480         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3481         .vreg_list              = NULL,
3482         .num_vregs              = 0,
3483         .regs                   = pciephy_regs_layout,
3484
3485         .start_ctrl             = SERDES_START | PCS_START,
3486         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3487         .phy_status             = PHYSTATUS,
3488
3489         .has_phy_com_ctrl       = false,
3490         .has_lane_rst           = false,
3491         .has_pwrdn_delay        = true,
3492         .pwrdn_delay_min        = 995,          /* us */
3493         .pwrdn_delay_max        = 1005,         /* us */
3494 };
3495
3496 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3497         .type                   = PHY_TYPE_PCIE,
3498         .nlanes                 = 1,
3499
3500         .serdes_tbl             = ipq6018_pcie_serdes_tbl,
3501         .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3502         .tx_tbl                 = ipq6018_pcie_tx_tbl,
3503         .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3504         .rx_tbl                 = ipq6018_pcie_rx_tbl,
3505         .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3506         .pcs_tbl                = ipq6018_pcie_pcs_tbl,
3507         .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3508         .clk_list               = ipq8074_pciephy_clk_l,
3509         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3510         .reset_list             = ipq8074_pciephy_reset_l,
3511         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3512         .vreg_list              = NULL,
3513         .num_vregs              = 0,
3514         .regs                   = ipq_pciephy_gen3_regs_layout,
3515
3516         .start_ctrl             = SERDES_START | PCS_START,
3517         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3518
3519         .has_phy_com_ctrl       = false,
3520         .has_lane_rst           = false,
3521         .has_pwrdn_delay        = true,
3522         .pwrdn_delay_min        = 995,          /* us */
3523         .pwrdn_delay_max        = 1005,         /* us */
3524 };
3525
3526 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3527         .type = PHY_TYPE_PCIE,
3528         .nlanes = 1,
3529
3530         .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
3531         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3532         .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
3533         .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3534         .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
3535         .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3536         .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
3537         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3538         .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
3539         .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3540         .clk_list               = sdm845_pciephy_clk_l,
3541         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3542         .reset_list             = sdm845_pciephy_reset_l,
3543         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3544         .vreg_list              = qmp_phy_vreg_l,
3545         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3546         .regs                   = sdm845_qmp_pciephy_regs_layout,
3547
3548         .start_ctrl             = PCS_START | SERDES_START,
3549         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3550         .phy_status             = PHYSTATUS,
3551
3552         .has_pwrdn_delay        = true,
3553         .pwrdn_delay_min        = 995,          /* us */
3554         .pwrdn_delay_max        = 1005,         /* us */
3555 };
3556
3557 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3558         .type = PHY_TYPE_PCIE,
3559         .nlanes = 1,
3560
3561         .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
3562         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3563         .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
3564         .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3565         .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
3566         .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3567         .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
3568         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3569         .clk_list               = sdm845_pciephy_clk_l,
3570         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3571         .reset_list             = sdm845_pciephy_reset_l,
3572         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3573         .vreg_list              = qmp_phy_vreg_l,
3574         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3575         .regs                   = sdm845_qhp_pciephy_regs_layout,
3576
3577         .start_ctrl             = PCS_START | SERDES_START,
3578         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3579         .phy_status             = PHYSTATUS,
3580
3581         .has_pwrdn_delay        = true,
3582         .pwrdn_delay_min        = 995,          /* us */
3583         .pwrdn_delay_max        = 1005,         /* us */
3584 };
3585
3586 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3587         .type = PHY_TYPE_PCIE,
3588         .nlanes = 1,
3589
3590         .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3591         .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3592         .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3593         .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3594         .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3595         .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3596         .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3597         .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3598         .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
3599         .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3600         .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3601         .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3602         .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3603         .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3604         .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3605         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3606         .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3607         .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3608         .clk_list               = sdm845_pciephy_clk_l,
3609         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3610         .reset_list             = sdm845_pciephy_reset_l,
3611         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3612         .vreg_list              = qmp_phy_vreg_l,
3613         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3614         .regs                   = sm8250_pcie_regs_layout,
3615
3616         .start_ctrl             = PCS_START | SERDES_START,
3617         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3618         .phy_status             = PHYSTATUS,
3619
3620         .has_pwrdn_delay        = true,
3621         .pwrdn_delay_min        = 995,          /* us */
3622         .pwrdn_delay_max        = 1005,         /* us */
3623 };
3624
3625 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3626         .type = PHY_TYPE_PCIE,
3627         .nlanes = 2,
3628
3629         .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3630         .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3631         .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3632         .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3633         .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
3634         .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3635         .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3636         .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3637         .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
3638         .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3639         .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3640         .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3641         .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3642         .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3643         .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3644         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3645         .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3646         .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3647         .clk_list               = sdm845_pciephy_clk_l,
3648         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3649         .reset_list             = sdm845_pciephy_reset_l,
3650         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3651         .vreg_list              = qmp_phy_vreg_l,
3652         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3653         .regs                   = sm8250_pcie_regs_layout,
3654
3655         .start_ctrl             = PCS_START | SERDES_START,
3656         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3657         .phy_status             = PHYSTATUS,
3658
3659         .is_dual_lane_phy       = true,
3660         .has_pwrdn_delay        = true,
3661         .pwrdn_delay_min        = 995,          /* us */
3662         .pwrdn_delay_max        = 1005,         /* us */
3663 };
3664
3665 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3666         .type                   = PHY_TYPE_USB3,
3667         .nlanes                 = 1,
3668
3669         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3670         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3671         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3672         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3673         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3674         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3675         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3676         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3677         .clk_list               = qmp_v3_phy_clk_l,
3678         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3679         .reset_list             = msm8996_usb3phy_reset_l,
3680         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3681         .vreg_list              = qmp_phy_vreg_l,
3682         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3683         .regs                   = qmp_v3_usb3phy_regs_layout,
3684
3685         .start_ctrl             = SERDES_START | PCS_START,
3686         .pwrdn_ctrl             = SW_PWRDN,
3687         .phy_status             = PHYSTATUS,
3688
3689         .has_pwrdn_delay        = true,
3690         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3691         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3692
3693         .has_phy_dp_com_ctrl    = true,
3694         .is_dual_lane_phy       = true,
3695 };
3696
3697 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3698         .type                   = PHY_TYPE_USB3,
3699         .nlanes                 = 1,
3700
3701         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3702         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3703         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3704         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3705         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3706         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3707         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3708         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3709         .clk_list               = qmp_v3_phy_clk_l,
3710         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3711         .reset_list             = sc7180_usb3phy_reset_l,
3712         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3713         .vreg_list              = qmp_phy_vreg_l,
3714         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3715         .regs                   = qmp_v3_usb3phy_regs_layout,
3716
3717         .start_ctrl             = SERDES_START | PCS_START,
3718         .pwrdn_ctrl             = SW_PWRDN,
3719         .phy_status             = PHYSTATUS,
3720
3721         .has_pwrdn_delay        = true,
3722         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3723         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3724
3725         .has_phy_dp_com_ctrl    = true,
3726         .is_dual_lane_phy       = true,
3727 };
3728
3729 static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3730         .type                   = PHY_TYPE_DP,
3731         .nlanes                 = 1,
3732
3733         .serdes_tbl             = qmp_v3_dp_serdes_tbl,
3734         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3735         .tx_tbl                 = qmp_v3_dp_tx_tbl,
3736         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3737
3738         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
3739         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3740         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
3741         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3742         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
3743         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3744         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
3745         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3746
3747         .clk_list               = qmp_v3_phy_clk_l,
3748         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3749         .reset_list             = sc7180_usb3phy_reset_l,
3750         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3751         .vreg_list              = qmp_phy_vreg_l,
3752         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3753         .regs                   = qmp_v3_usb3phy_regs_layout,
3754
3755         .has_phy_dp_com_ctrl    = true,
3756         .is_dual_lane_phy       = true,
3757
3758         .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3759         .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3760         .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3761         .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
3762 };
3763
3764 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3765         .usb_cfg                = &sc7180_usb3phy_cfg,
3766         .dp_cfg                 = &sc7180_dpphy_cfg,
3767 };
3768
3769 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3770         .type                   = PHY_TYPE_USB3,
3771         .nlanes                 = 1,
3772
3773         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
3774         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3775         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
3776         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3777         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
3778         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3779         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
3780         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3781         .clk_list               = qmp_v3_phy_clk_l,
3782         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3783         .reset_list             = msm8996_usb3phy_reset_l,
3784         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3785         .vreg_list              = qmp_phy_vreg_l,
3786         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3787         .regs                   = qmp_v3_usb3phy_regs_layout,
3788
3789         .start_ctrl             = SERDES_START | PCS_START,
3790         .pwrdn_ctrl             = SW_PWRDN,
3791         .phy_status             = PHYSTATUS,
3792
3793         .has_pwrdn_delay        = true,
3794         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3795         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3796 };
3797
3798 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3799         .type                   = PHY_TYPE_UFS,
3800         .nlanes                 = 2,
3801
3802         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
3803         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3804         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
3805         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3806         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
3807         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3808         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
3809         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3810         .clk_list               = sdm845_ufs_phy_clk_l,
3811         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3812         .vreg_list              = qmp_phy_vreg_l,
3813         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3814         .regs                   = sdm845_ufsphy_regs_layout,
3815
3816         .start_ctrl             = SERDES_START,
3817         .pwrdn_ctrl             = SW_PWRDN,
3818         .phy_status             = PHYSTATUS,
3819
3820         .is_dual_lane_phy       = true,
3821         .no_pcs_sw_reset        = true,
3822 };
3823
3824 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3825         .type                   = PHY_TYPE_UFS,
3826         .nlanes                 = 1,
3827
3828         .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
3829         .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3830         .tx_tbl                 = sm6115_ufsphy_tx_tbl,
3831         .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3832         .rx_tbl                 = sm6115_ufsphy_rx_tbl,
3833         .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3834         .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
3835         .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3836         .clk_list               = sdm845_ufs_phy_clk_l,
3837         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3838         .vreg_list              = qmp_phy_vreg_l,
3839         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3840         .regs                   = sm6115_ufsphy_regs_layout,
3841
3842         .start_ctrl             = SERDES_START,
3843         .pwrdn_ctrl             = SW_PWRDN,
3844
3845         .is_dual_lane_phy       = false,
3846         .no_pcs_sw_reset        = true,
3847 };
3848
3849 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3850         .type                   = PHY_TYPE_PCIE,
3851         .nlanes                 = 1,
3852
3853         .serdes_tbl             = msm8998_pcie_serdes_tbl,
3854         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3855         .tx_tbl                 = msm8998_pcie_tx_tbl,
3856         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3857         .rx_tbl                 = msm8998_pcie_rx_tbl,
3858         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3859         .pcs_tbl                = msm8998_pcie_pcs_tbl,
3860         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3861         .clk_list               = msm8996_phy_clk_l,
3862         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3863         .reset_list             = ipq8074_pciephy_reset_l,
3864         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3865         .vreg_list              = qmp_phy_vreg_l,
3866         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3867         .regs                   = pciephy_regs_layout,
3868
3869         .start_ctrl             = SERDES_START | PCS_START,
3870         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3871         .phy_status             = PHYSTATUS,
3872 };
3873
3874 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3875         .type                   = PHY_TYPE_USB3,
3876         .nlanes                 = 1,
3877
3878         .serdes_tbl             = msm8998_usb3_serdes_tbl,
3879         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3880         .tx_tbl                 = msm8998_usb3_tx_tbl,
3881         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3882         .rx_tbl                 = msm8998_usb3_rx_tbl,
3883         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3884         .pcs_tbl                = msm8998_usb3_pcs_tbl,
3885         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3886         .clk_list               = msm8996_phy_clk_l,
3887         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3888         .reset_list             = msm8996_usb3phy_reset_l,
3889         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3890         .vreg_list              = qmp_phy_vreg_l,
3891         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3892         .regs                   = qmp_v3_usb3phy_regs_layout,
3893
3894         .start_ctrl             = SERDES_START | PCS_START,
3895         .pwrdn_ctrl             = SW_PWRDN,
3896         .phy_status             = PHYSTATUS,
3897
3898         .is_dual_lane_phy       = true,
3899 };
3900
3901 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3902         .type                   = PHY_TYPE_UFS,
3903         .nlanes                 = 2,
3904
3905         .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
3906         .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3907         .tx_tbl                 = sm8150_ufsphy_tx_tbl,
3908         .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3909         .rx_tbl                 = sm8150_ufsphy_rx_tbl,
3910         .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3911         .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
3912         .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3913         .clk_list               = sdm845_ufs_phy_clk_l,
3914         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3915         .vreg_list              = qmp_phy_vreg_l,
3916         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3917         .regs                   = sm8150_ufsphy_regs_layout,
3918
3919         .start_ctrl             = SERDES_START,
3920         .pwrdn_ctrl             = SW_PWRDN,
3921         .phy_status             = PHYSTATUS,
3922
3923         .is_dual_lane_phy       = true,
3924 };
3925
3926 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3927         .type                   = PHY_TYPE_USB3,
3928         .nlanes                 = 1,
3929
3930         .serdes_tbl             = sm8150_usb3_serdes_tbl,
3931         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3932         .tx_tbl                 = sm8150_usb3_tx_tbl,
3933         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3934         .rx_tbl                 = sm8150_usb3_rx_tbl,
3935         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3936         .pcs_tbl                = sm8150_usb3_pcs_tbl,
3937         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3938         .clk_list               = qmp_v4_phy_clk_l,
3939         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3940         .reset_list             = msm8996_usb3phy_reset_l,
3941         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3942         .vreg_list              = qmp_phy_vreg_l,
3943         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3944         .regs                   = qmp_v4_usb3phy_regs_layout,
3945
3946         .start_ctrl             = SERDES_START | PCS_START,
3947         .pwrdn_ctrl             = SW_PWRDN,
3948         .phy_status             = PHYSTATUS,
3949
3950
3951         .has_pwrdn_delay        = true,
3952         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3953         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3954
3955         .has_phy_dp_com_ctrl    = true,
3956         .is_dual_lane_phy       = true,
3957 };
3958
3959 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3960         .type = PHY_TYPE_PCIE,
3961         .nlanes = 1,
3962
3963         .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
3964         .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
3965         .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
3966         .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3967         .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
3968         .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3969         .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
3970         .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3971         .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
3972         .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3973         .clk_list               = sdm845_pciephy_clk_l,
3974         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3975         .reset_list             = sdm845_pciephy_reset_l,
3976         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3977         .vreg_list              = qmp_phy_vreg_l,
3978         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3979         .regs                   = sm8250_pcie_regs_layout,
3980
3981         .start_ctrl             = PCS_START | SERDES_START,
3982         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3983
3984         .has_pwrdn_delay        = true,
3985         .pwrdn_delay_min        = 995,          /* us */
3986         .pwrdn_delay_max        = 1005,         /* us */
3987 };
3988
3989 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
3990         .type                   = PHY_TYPE_DP,
3991         .nlanes                 = 1,
3992
3993         .serdes_tbl             = qmp_v4_dp_serdes_tbl,
3994         .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3995         .tx_tbl                 = qmp_v4_dp_tx_tbl,
3996         .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3997
3998         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
3999         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
4000         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
4001         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
4002         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
4003         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
4004         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
4005         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
4006
4007         .clk_list               = qmp_v3_phy_clk_l,
4008         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
4009         .reset_list             = sc7180_usb3phy_reset_l,
4010         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
4011         .vreg_list              = qmp_phy_vreg_l,
4012         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4013         .regs                   = qmp_v3_usb3phy_regs_layout,
4014
4015         .has_phy_dp_com_ctrl    = true,
4016         .is_dual_lane_phy       = true,
4017
4018         .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
4019         .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
4020         .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
4021         .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
4022 };
4023
4024 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
4025         .usb_cfg                = &sm8150_usb3phy_cfg,
4026         .dp_cfg                 = &sc8180x_dpphy_cfg,
4027 };
4028
4029 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
4030         .type                   = PHY_TYPE_USB3,
4031         .nlanes                 = 1,
4032
4033         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4034         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4035         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
4036         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
4037         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
4038         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
4039         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
4040         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
4041         .clk_list               = qmp_v4_phy_clk_l,
4042         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4043         .reset_list             = msm8996_usb3phy_reset_l,
4044         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4045         .vreg_list              = qmp_phy_vreg_l,
4046         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4047         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4048
4049         .start_ctrl             = SERDES_START | PCS_START,
4050         .pwrdn_ctrl             = SW_PWRDN,
4051         .phy_status             = PHYSTATUS,
4052
4053         .has_pwrdn_delay        = true,
4054         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4055         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4056 };
4057
4058 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
4059         .type                   = PHY_TYPE_USB3,
4060         .nlanes                 = 1,
4061
4062         .serdes_tbl             = sm8150_usb3_serdes_tbl,
4063         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4064         .tx_tbl                 = sm8250_usb3_tx_tbl,
4065         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
4066         .rx_tbl                 = sm8250_usb3_rx_tbl,
4067         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
4068         .pcs_tbl                = sm8250_usb3_pcs_tbl,
4069         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
4070         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
4071         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4072         .reset_list             = msm8996_usb3phy_reset_l,
4073         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4074         .vreg_list              = qmp_phy_vreg_l,
4075         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4076         .regs                   = qmp_v4_usb3phy_regs_layout,
4077
4078         .start_ctrl             = SERDES_START | PCS_START,
4079         .pwrdn_ctrl             = SW_PWRDN,
4080         .phy_status             = PHYSTATUS,
4081
4082         .has_pwrdn_delay        = true,
4083         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4084         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4085
4086         .has_phy_dp_com_ctrl    = true,
4087         .is_dual_lane_phy       = true,
4088 };
4089
4090 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
4091         .type                   = PHY_TYPE_USB3,
4092         .nlanes                 = 1,
4093
4094         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4095         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4096         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
4097         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
4098         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
4099         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
4100         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
4101         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
4102         .clk_list               = qmp_v4_phy_clk_l,
4103         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4104         .reset_list             = msm8996_usb3phy_reset_l,
4105         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4106         .vreg_list              = qmp_phy_vreg_l,
4107         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4108         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4109
4110         .start_ctrl             = SERDES_START | PCS_START,
4111         .pwrdn_ctrl             = SW_PWRDN,
4112         .phy_status             = PHYSTATUS,
4113
4114         .has_pwrdn_delay        = true,
4115         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4116         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4117 };
4118
4119 static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
4120         .type                   = PHY_TYPE_DP,
4121         .nlanes                 = 1,
4122
4123         .serdes_tbl             = qmp_v4_dp_serdes_tbl,
4124         .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
4125         .tx_tbl                 = qmp_v4_dp_tx_tbl,
4126         .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
4127
4128         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
4129         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
4130         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
4131         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
4132         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
4133         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
4134         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
4135         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
4136
4137         .clk_list               = qmp_v4_phy_clk_l,
4138         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4139         .reset_list             = msm8996_usb3phy_reset_l,
4140         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4141         .vreg_list              = qmp_phy_vreg_l,
4142         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4143         .regs                   = qmp_v4_usb3phy_regs_layout,
4144
4145         .has_phy_dp_com_ctrl    = true,
4146         .is_dual_lane_phy       = true,
4147
4148         .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
4149         .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
4150         .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
4151         .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
4152 };
4153
4154 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
4155         .usb_cfg                = &sm8250_usb3phy_cfg,
4156         .dp_cfg                 = &sm8250_dpphy_cfg,
4157 };
4158
4159 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
4160         .type                   = PHY_TYPE_USB3,
4161         .nlanes                 = 1,
4162
4163         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4164         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4165         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
4166         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
4167         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
4168         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
4169         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
4170         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
4171         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
4172         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
4173         .reset_list             = msm8996_usb3phy_reset_l,
4174         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4175         .vreg_list              = qmp_phy_vreg_l,
4176         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4177         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
4178
4179         .start_ctrl             = SERDES_START | PCS_START,
4180         .pwrdn_ctrl             = SW_PWRDN,
4181         .phy_status             = PHYSTATUS,
4182
4183         .has_pwrdn_delay        = true,
4184         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4185         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4186 };
4187
4188 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
4189         .type = PHY_TYPE_PCIE,
4190         .nlanes = 2,
4191
4192         .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
4193         .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
4194         .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
4195         .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
4196         .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
4197         .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
4198         .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
4199         .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
4200         .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
4201         .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
4202         .clk_list               = sdm845_pciephy_clk_l,
4203         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4204         .reset_list             = sdm845_pciephy_reset_l,
4205         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4206         .vreg_list              = qmp_phy_vreg_l,
4207         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4208         .regs                   = sm8250_pcie_regs_layout,
4209
4210         .start_ctrl             = PCS_START | SERDES_START,
4211         .pwrdn_ctrl             = SW_PWRDN,
4212         .phy_status             = PHYSTATUS_4_20,
4213
4214         .is_dual_lane_phy       = true,
4215         .has_pwrdn_delay        = true,
4216         .pwrdn_delay_min        = 995,          /* us */
4217         .pwrdn_delay_max        = 1005,         /* us */
4218 };
4219
4220 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
4221         .type                   = PHY_TYPE_UFS,
4222         .nlanes                 = 2,
4223
4224         .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
4225         .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4226         .tx_tbl                 = sm8350_ufsphy_tx_tbl,
4227         .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4228         .rx_tbl                 = sm8350_ufsphy_rx_tbl,
4229         .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4230         .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
4231         .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4232         .clk_list               = sdm845_ufs_phy_clk_l,
4233         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
4234         .vreg_list              = qmp_phy_vreg_l,
4235         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4236         .regs                   = sm8150_ufsphy_regs_layout,
4237
4238         .start_ctrl             = SERDES_START,
4239         .pwrdn_ctrl             = SW_PWRDN,
4240         .phy_status             = PHYSTATUS,
4241
4242         .is_dual_lane_phy       = true,
4243 };
4244
4245 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
4246         .type                   = PHY_TYPE_USB3,
4247         .nlanes                 = 1,
4248
4249         .serdes_tbl             = sm8150_usb3_serdes_tbl,
4250         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4251         .tx_tbl                 = sm8350_usb3_tx_tbl,
4252         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
4253         .rx_tbl                 = sm8350_usb3_rx_tbl,
4254         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
4255         .pcs_tbl                = sm8350_usb3_pcs_tbl,
4256         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
4257         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
4258         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4259         .reset_list             = msm8996_usb3phy_reset_l,
4260         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4261         .vreg_list              = qmp_phy_vreg_l,
4262         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4263         .regs                   = qmp_v4_usb3phy_regs_layout,
4264
4265         .start_ctrl             = SERDES_START | PCS_START,
4266         .pwrdn_ctrl             = SW_PWRDN,
4267         .phy_status             = PHYSTATUS,
4268
4269         .has_pwrdn_delay        = true,
4270         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4271         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4272
4273         .has_phy_dp_com_ctrl    = true,
4274         .is_dual_lane_phy       = true,
4275 };
4276
4277 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
4278         .type                   = PHY_TYPE_USB3,
4279         .nlanes                 = 1,
4280
4281         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4282         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4283         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
4284         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
4285         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
4286         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
4287         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
4288         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
4289         .clk_list               = qmp_v4_phy_clk_l,
4290         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4291         .reset_list             = msm8996_usb3phy_reset_l,
4292         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4293         .vreg_list              = qmp_phy_vreg_l,
4294         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4295         .regs                   = sm8350_usb3_uniphy_regs_layout,
4296
4297         .start_ctrl             = SERDES_START | PCS_START,
4298         .pwrdn_ctrl             = SW_PWRDN,
4299         .phy_status             = PHYSTATUS,
4300
4301         .has_pwrdn_delay        = true,
4302         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4303         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4304 };
4305
4306 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
4307         .type                   = PHY_TYPE_UFS,
4308         .nlanes                 = 2,
4309
4310         .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
4311         .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4312         .tx_tbl                 = sm8350_ufsphy_tx_tbl,
4313         .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4314         .rx_tbl                 = sm8350_ufsphy_rx_tbl,
4315         .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4316         .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
4317         .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4318         .clk_list               = sm8450_ufs_phy_clk_l,
4319         .num_clks               = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
4320         .vreg_list              = qmp_phy_vreg_l,
4321         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4322         .regs                   = sm8150_ufsphy_regs_layout,
4323
4324         .start_ctrl             = SERDES_START,
4325         .pwrdn_ctrl             = SW_PWRDN,
4326         .phy_status             = PHYSTATUS,
4327
4328         .is_dual_lane_phy       = true,
4329 };
4330
4331 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
4332         .type = PHY_TYPE_PCIE,
4333         .nlanes = 1,
4334
4335         .serdes_tbl             = sm8450_qmp_gen3x1_pcie_serdes_tbl,
4336         .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
4337         .tx_tbl                 = sm8450_qmp_gen3x1_pcie_tx_tbl,
4338         .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
4339         .rx_tbl                 = sm8450_qmp_gen3x1_pcie_rx_tbl,
4340         .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
4341         .pcs_tbl                = sm8450_qmp_gen3x1_pcie_pcs_tbl,
4342         .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
4343         .pcs_misc_tbl           = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
4344         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
4345         .clk_list               = sdm845_pciephy_clk_l,
4346         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4347         .reset_list             = sdm845_pciephy_reset_l,
4348         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4349         .vreg_list              = qmp_phy_vreg_l,
4350         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4351         .regs                   = sm8250_pcie_regs_layout,
4352
4353         .start_ctrl             = SERDES_START | PCS_START,
4354         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
4355         .phy_status             = PHYSTATUS,
4356
4357         .has_pwrdn_delay        = true,
4358         .pwrdn_delay_min        = 995,          /* us */
4359         .pwrdn_delay_max        = 1005,         /* us */
4360 };
4361
4362 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
4363         .type = PHY_TYPE_PCIE,
4364         .nlanes = 2,
4365
4366         .serdes_tbl             = sm8450_qmp_gen4x2_pcie_serdes_tbl,
4367         .serdes_tbl_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
4368         .tx_tbl                 = sm8450_qmp_gen4x2_pcie_tx_tbl,
4369         .tx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
4370         .rx_tbl                 = sm8450_qmp_gen4x2_pcie_rx_tbl,
4371         .rx_tbl_num             = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
4372         .pcs_tbl                = sm8450_qmp_gen4x2_pcie_pcs_tbl,
4373         .pcs_tbl_num            = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
4374         .pcs_misc_tbl           = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
4375         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
4376         .clk_list               = sdm845_pciephy_clk_l,
4377         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
4378         .reset_list             = sdm845_pciephy_reset_l,
4379         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
4380         .vreg_list              = qmp_phy_vreg_l,
4381         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4382         .regs                   = sm8250_pcie_regs_layout,
4383
4384         .start_ctrl             = SERDES_START | PCS_START,
4385         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
4386         .phy_status             = PHYSTATUS_4_20,
4387
4388         .is_dual_lane_phy       = true,
4389         .has_pwrdn_delay        = true,
4390         .pwrdn_delay_min        = 995,          /* us */
4391         .pwrdn_delay_max        = 1005,         /* us */
4392 };
4393
4394 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
4395         .type                   = PHY_TYPE_USB3,
4396         .nlanes                 = 1,
4397
4398         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
4399         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
4400         .tx_tbl                 = qcm2290_usb3_tx_tbl,
4401         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
4402         .rx_tbl                 = qcm2290_usb3_rx_tbl,
4403         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
4404         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
4405         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
4406         .clk_list               = qcm2290_usb3phy_clk_l,
4407         .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
4408         .reset_list             = qcm2290_usb3phy_reset_l,
4409         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
4410         .vreg_list              = qmp_phy_vreg_l,
4411         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4412         .regs                   = qcm2290_usb3phy_regs_layout,
4413
4414         .start_ctrl             = SERDES_START | PCS_START,
4415         .pwrdn_ctrl             = SW_PWRDN,
4416         .phy_status             = PHYSTATUS,
4417
4418         .is_dual_lane_phy       = true,
4419 };
4420
4421 static void qcom_qmp_phy_configure_lane(void __iomem *base,
4422                                         const unsigned int *regs,
4423                                         const struct qmp_phy_init_tbl tbl[],
4424                                         int num,
4425                                         u8 lane_mask)
4426 {
4427         int i;
4428         const struct qmp_phy_init_tbl *t = tbl;
4429
4430         if (!t)
4431                 return;
4432
4433         for (i = 0; i < num; i++, t++) {
4434                 if (!(t->lane_mask & lane_mask))
4435                         continue;
4436
4437                 if (t->in_layout)
4438                         writel(t->val, base + regs[t->offset]);
4439                 else
4440                         writel(t->val, base + t->offset);
4441         }
4442 }
4443
4444 static void qcom_qmp_phy_configure(void __iomem *base,
4445                                    const unsigned int *regs,
4446                                    const struct qmp_phy_init_tbl tbl[],
4447                                    int num)
4448 {
4449         qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
4450 }
4451
4452 static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
4453 {
4454         struct qcom_qmp *qmp = qphy->qmp;
4455         const struct qmp_phy_cfg *cfg = qphy->cfg;
4456         void __iomem *serdes = qphy->serdes;
4457         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4458         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
4459         int serdes_tbl_num = cfg->serdes_tbl_num;
4460         int ret;
4461
4462         qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
4463         if (cfg->serdes_tbl_sec)
4464                 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
4465                                        cfg->serdes_tbl_num_sec);
4466
4467         if (cfg->type == PHY_TYPE_DP) {
4468                 switch (dp_opts->link_rate) {
4469                 case 1620:
4470                         qcom_qmp_phy_configure(serdes, cfg->regs,
4471                                                cfg->serdes_tbl_rbr,
4472                                                cfg->serdes_tbl_rbr_num);
4473                         break;
4474                 case 2700:
4475                         qcom_qmp_phy_configure(serdes, cfg->regs,
4476                                                cfg->serdes_tbl_hbr,
4477                                                cfg->serdes_tbl_hbr_num);
4478                         break;
4479                 case 5400:
4480                         qcom_qmp_phy_configure(serdes, cfg->regs,
4481                                                cfg->serdes_tbl_hbr2,
4482                                                cfg->serdes_tbl_hbr2_num);
4483                         break;
4484                 case 8100:
4485                         qcom_qmp_phy_configure(serdes, cfg->regs,
4486                                                cfg->serdes_tbl_hbr3,
4487                                                cfg->serdes_tbl_hbr3_num);
4488                         break;
4489                 default:
4490                         /* Other link rates aren't supported */
4491                         return -EINVAL;
4492                 }
4493         }
4494
4495
4496         if (cfg->has_phy_com_ctrl) {
4497                 void __iomem *status;
4498                 unsigned int mask, val;
4499
4500                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
4501                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4502                              SERDES_START | PCS_START);
4503
4504                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
4505                 mask = cfg->mask_com_pcs_ready;
4506
4507                 ret = readl_poll_timeout(status, val, (val & mask), 10,
4508                                          PHY_INIT_COMPLETE_TIMEOUT);
4509                 if (ret) {
4510                         dev_err(qmp->dev,
4511                                 "phy common block init timed-out\n");
4512                         return ret;
4513                 }
4514         }
4515
4516         return 0;
4517 }
4518
4519 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
4520 {
4521         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4522                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4523                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4524
4525         /* Turn on BIAS current for PHY/PLL */
4526         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
4527                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
4528                qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4529
4530         writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4531
4532         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4533                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
4534                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
4535                DP_PHY_PD_CTL_DP_CLAMP_EN,
4536                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4537
4538         writel(QSERDES_V3_COM_BIAS_EN |
4539                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
4540                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
4541                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
4542                qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4543
4544         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4545         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4546         writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4547         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4548         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4549         writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4550         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4551         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4552         writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4553         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4554         qphy->dp_aux_cfg = 0;
4555
4556         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4557                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4558                PHY_AUX_REQ_ERR_MASK,
4559                qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
4560 }
4561
4562 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
4563         { 0x00, 0x0c, 0x15, 0x1a },
4564         { 0x02, 0x0e, 0x16, 0xff },
4565         { 0x02, 0x11, 0xff, 0xff },
4566         { 0x04, 0xff, 0xff, 0xff }
4567 };
4568
4569 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
4570         { 0x02, 0x12, 0x16, 0x1a },
4571         { 0x09, 0x19, 0x1f, 0xff },
4572         { 0x10, 0x1f, 0xff, 0xff },
4573         { 0x1f, 0xff, 0xff, 0xff }
4574 };
4575
4576 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
4577         { 0x00, 0x0c, 0x14, 0x19 },
4578         { 0x00, 0x0b, 0x12, 0xff },
4579         { 0x00, 0x0b, 0xff, 0xff },
4580         { 0x04, 0xff, 0xff, 0xff }
4581 };
4582
4583 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
4584         { 0x08, 0x0f, 0x16, 0x1f },
4585         { 0x11, 0x1e, 0x1f, 0xff },
4586         { 0x19, 0x1f, 0xff, 0xff },
4587         { 0x1f, 0xff, 0xff, 0xff }
4588 };
4589
4590 static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
4591                 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
4592 {
4593         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4594         unsigned int v_level = 0, p_level = 0;
4595         u8 voltage_swing_cfg, pre_emphasis_cfg;
4596         int i;
4597
4598         for (i = 0; i < dp_opts->lanes; i++) {
4599                 v_level = max(v_level, dp_opts->voltage[i]);
4600                 p_level = max(p_level, dp_opts->pre[i]);
4601         }
4602
4603         if (dp_opts->link_rate <= 2700) {
4604                 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
4605                 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
4606         } else {
4607                 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
4608                 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
4609         }
4610
4611         /* TODO: Move check to config check */
4612         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
4613                 return -EINVAL;
4614
4615         /* Enable MUX to use Cursor values from these registers */
4616         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
4617         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
4618
4619         writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
4620         writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
4621         writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
4622         writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
4623
4624         return 0;
4625 }
4626
4627 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
4628 {
4629         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4630         u32 bias_en, drvr_en;
4631
4632         if (qcom_qmp_phy_configure_dp_swing(qphy,
4633                                 QSERDES_V3_TX_TX_DRV_LVL,
4634                                 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
4635                 return;
4636
4637         if (dp_opts->lanes == 1) {
4638                 bias_en = 0x3e;
4639                 drvr_en = 0x13;
4640         } else {
4641                 bias_en = 0x3f;
4642                 drvr_en = 0x10;
4643         }
4644
4645         writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4646         writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4647         writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4648         writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4649 }
4650
4651 static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
4652 {
4653         u32 val;
4654         bool reverse = false;
4655
4656         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4657               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
4658
4659         /*
4660          * TODO: Assume orientation is CC1 for now and two lanes, need to
4661          * use type-c connector to understand orientation and lanes.
4662          *
4663          * Otherwise val changes to be like below if this code understood
4664          * the orientation of the type-c cable.
4665          *
4666          * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
4667          *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
4668          * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
4669          *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4670          * if (orientation == ORIENTATION_CC2)
4671          *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
4672          */
4673         val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4674         writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4675
4676         writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
4677
4678         return reverse;
4679 }
4680
4681 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
4682 {
4683         const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4684         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4685         u32 phy_vco_div, status;
4686         unsigned long pixel_freq;
4687
4688         qcom_qmp_phy_configure_dp_mode(qphy);
4689
4690         writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
4691         writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
4692
4693         switch (dp_opts->link_rate) {
4694         case 1620:
4695                 phy_vco_div = 0x1;
4696                 pixel_freq = 1620000000UL / 2;
4697                 break;
4698         case 2700:
4699                 phy_vco_div = 0x1;
4700                 pixel_freq = 2700000000UL / 2;
4701                 break;
4702         case 5400:
4703                 phy_vco_div = 0x2;
4704                 pixel_freq = 5400000000UL / 4;
4705                 break;
4706         case 8100:
4707                 phy_vco_div = 0x0;
4708                 pixel_freq = 8100000000UL / 6;
4709                 break;
4710         default:
4711                 /* Other link rates aren't supported */
4712                 return -EINVAL;
4713         }
4714         writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
4715
4716         clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4717         clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4718
4719         writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4720         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4721         writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4722         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4723         writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4724
4725         writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
4726
4727         if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
4728                         status,
4729                         ((status & BIT(0)) > 0),
4730                         500,
4731                         10000))
4732                 return -ETIMEDOUT;
4733
4734         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4735
4736         if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4737                         status,
4738                         ((status & BIT(1)) > 0),
4739                         500,
4740                         10000))
4741                 return -ETIMEDOUT;
4742
4743         writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4744         udelay(2000);
4745         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4746
4747         return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4748                         status,
4749                         ((status & BIT(1)) > 0),
4750                         500,
4751                         10000);
4752 }
4753
4754 /*
4755  * We need to calibrate the aux setting here as many times
4756  * as the caller tries
4757  */
4758 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
4759 {
4760         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
4761         u8 val;
4762
4763         qphy->dp_aux_cfg++;
4764         qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4765         val = cfg1_settings[qphy->dp_aux_cfg];
4766
4767         writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4768
4769         return 0;
4770 }
4771
4772 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4773 {
4774         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4775                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4776                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4777
4778         /* Turn on BIAS current for PHY/PLL */
4779         writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4780
4781         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4782         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4783         writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4784         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4785         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4786         writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4787         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4788         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4789         writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4790         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4791         qphy->dp_aux_cfg = 0;
4792
4793         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4794                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4795                PHY_AUX_REQ_ERR_MASK,
4796                qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4797 }
4798
4799 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4800 {
4801         /* Program default values before writing proper values */
4802         writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4803         writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4804
4805         writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4806         writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4807
4808         qcom_qmp_phy_configure_dp_swing(qphy,
4809                         QSERDES_V4_TX_TX_DRV_LVL,
4810                         QSERDES_V4_TX_TX_EMP_POST1_LVL);
4811 }
4812
4813 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4814 {
4815         const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4816         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4817         u32 phy_vco_div, status;
4818         unsigned long pixel_freq;
4819         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4820         bool reverse;
4821
4822         writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4823
4824         reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4825
4826         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4827         writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4828
4829         writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4830         writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4831
4832         switch (dp_opts->link_rate) {
4833         case 1620:
4834                 phy_vco_div = 0x1;
4835                 pixel_freq = 1620000000UL / 2;
4836                 break;
4837         case 2700:
4838                 phy_vco_div = 0x1;
4839                 pixel_freq = 2700000000UL / 2;
4840                 break;
4841         case 5400:
4842                 phy_vco_div = 0x2;
4843                 pixel_freq = 5400000000UL / 4;
4844                 break;
4845         case 8100:
4846                 phy_vco_div = 0x0;
4847                 pixel_freq = 8100000000UL / 6;
4848                 break;
4849         default:
4850                 /* Other link rates aren't supported */
4851                 return -EINVAL;
4852         }
4853         writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4854
4855         clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4856         clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4857
4858         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4859         writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4860         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4861         writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4862
4863         writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4864
4865         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4866                         status,
4867                         ((status & BIT(0)) > 0),
4868                         500,
4869                         10000))
4870                 return -ETIMEDOUT;
4871
4872         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4873                         status,
4874                         ((status & BIT(0)) > 0),
4875                         500,
4876                         10000))
4877                 return -ETIMEDOUT;
4878
4879         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4880                         status,
4881                         ((status & BIT(1)) > 0),
4882                         500,
4883                         10000))
4884                 return -ETIMEDOUT;
4885
4886         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4887
4888         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4889                         status,
4890                         ((status & BIT(0)) > 0),
4891                         500,
4892                         10000))
4893                 return -ETIMEDOUT;
4894
4895         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4896                         status,
4897                         ((status & BIT(1)) > 0),
4898                         500,
4899                         10000))
4900                 return -ETIMEDOUT;
4901
4902         /*
4903          * At least for 7nm DP PHY this has to be done after enabling link
4904          * clock.
4905          */
4906
4907         if (dp_opts->lanes == 1) {
4908                 bias0_en = reverse ? 0x3e : 0x15;
4909                 bias1_en = reverse ? 0x15 : 0x3e;
4910                 drvr0_en = reverse ? 0x13 : 0x10;
4911                 drvr1_en = reverse ? 0x10 : 0x13;
4912         } else if (dp_opts->lanes == 2) {
4913                 bias0_en = reverse ? 0x3f : 0x15;
4914                 bias1_en = reverse ? 0x15 : 0x3f;
4915                 drvr0_en = 0x10;
4916                 drvr1_en = 0x10;
4917         } else {
4918                 bias0_en = 0x3f;
4919                 bias1_en = 0x3f;
4920                 drvr0_en = 0x10;
4921                 drvr1_en = 0x10;
4922         }
4923
4924         writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4925         writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4926         writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4927         writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4928
4929         writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4930         udelay(2000);
4931         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4932
4933         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4934                         status,
4935                         ((status & BIT(1)) > 0),
4936                         500,
4937                         10000))
4938                 return -ETIMEDOUT;
4939
4940         writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
4941         writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
4942
4943         writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4944         writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4945
4946         writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4947         writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4948
4949         return 0;
4950 }
4951
4952 /*
4953  * We need to calibrate the aux setting here as many times
4954  * as the caller tries
4955  */
4956 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
4957 {
4958         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
4959         u8 val;
4960
4961         qphy->dp_aux_cfg++;
4962         qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4963         val = cfg1_settings[qphy->dp_aux_cfg];
4964
4965         writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4966
4967         return 0;
4968 }
4969
4970 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
4971 {
4972         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
4973         struct qmp_phy *qphy = phy_get_drvdata(phy);
4974         const struct qmp_phy_cfg *cfg = qphy->cfg;
4975
4976         memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
4977         if (qphy->dp_opts.set_voltages) {
4978                 cfg->configure_dp_tx(qphy);
4979                 qphy->dp_opts.set_voltages = 0;
4980         }
4981
4982         return 0;
4983 }
4984
4985 static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
4986 {
4987         struct qmp_phy *qphy = phy_get_drvdata(phy);
4988         const struct qmp_phy_cfg *cfg = qphy->cfg;
4989
4990         if (cfg->calibrate_dp_phy)
4991                 return cfg->calibrate_dp_phy(qphy);
4992
4993         return 0;
4994 }
4995
4996 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
4997 {
4998         struct qcom_qmp *qmp = qphy->qmp;
4999         const struct qmp_phy_cfg *cfg = qphy->cfg;
5000         void __iomem *serdes = qphy->serdes;
5001         void __iomem *pcs = qphy->pcs;
5002         void __iomem *dp_com = qmp->dp_com;
5003         int ret, i;
5004
5005         mutex_lock(&qmp->phy_mutex);
5006         if (qmp->init_count++) {
5007                 mutex_unlock(&qmp->phy_mutex);
5008                 return 0;
5009         }
5010
5011         /* turn on regulator supplies */
5012         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
5013         if (ret) {
5014                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
5015                 goto err_reg_enable;
5016         }
5017
5018         for (i = 0; i < cfg->num_resets; i++) {
5019                 ret = reset_control_assert(qmp->resets[i]);
5020                 if (ret) {
5021                         dev_err(qmp->dev, "%s reset assert failed\n",
5022                                 cfg->reset_list[i]);
5023                         goto err_rst_assert;
5024                 }
5025         }
5026
5027         for (i = cfg->num_resets - 1; i >= 0; i--) {
5028                 ret = reset_control_deassert(qmp->resets[i]);
5029                 if (ret) {
5030                         dev_err(qmp->dev, "%s reset deassert failed\n",
5031                                 qphy->cfg->reset_list[i]);
5032                         goto err_rst;
5033                 }
5034         }
5035
5036         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5037         if (ret)
5038                 goto err_rst;
5039
5040         if (cfg->has_phy_dp_com_ctrl) {
5041                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
5042                              SW_PWRDN);
5043                 /* override hardware control for reset of qmp phy */
5044                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
5045                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
5046                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
5047
5048                 /* Default type-c orientation, i.e CC1 */
5049                 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
5050
5051                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
5052                              USB3_MODE | DP_MODE);
5053
5054                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
5055                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
5056                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
5057                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
5058
5059                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
5060                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
5061         }
5062
5063         if (cfg->has_phy_com_ctrl) {
5064                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
5065                              SW_PWRDN);
5066         } else {
5067                 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
5068                         qphy_setbits(pcs,
5069                                         cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5070                                         cfg->pwrdn_ctrl);
5071                 else
5072                         qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
5073                                         cfg->pwrdn_ctrl);
5074         }
5075
5076         mutex_unlock(&qmp->phy_mutex);
5077
5078         return 0;
5079
5080 err_rst:
5081         while (++i < cfg->num_resets)
5082                 reset_control_assert(qmp->resets[i]);
5083 err_rst_assert:
5084         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
5085 err_reg_enable:
5086         mutex_unlock(&qmp->phy_mutex);
5087
5088         return ret;
5089 }
5090
5091 static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
5092 {
5093         struct qcom_qmp *qmp = qphy->qmp;
5094         const struct qmp_phy_cfg *cfg = qphy->cfg;
5095         void __iomem *serdes = qphy->serdes;
5096         int i = cfg->num_resets;
5097
5098         mutex_lock(&qmp->phy_mutex);
5099         if (--qmp->init_count) {
5100                 mutex_unlock(&qmp->phy_mutex);
5101                 return 0;
5102         }
5103
5104         reset_control_assert(qmp->ufs_reset);
5105         if (cfg->has_phy_com_ctrl) {
5106                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
5107                              SERDES_START | PCS_START);
5108                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
5109                              SW_RESET);
5110                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
5111                              SW_PWRDN);
5112         }
5113
5114         while (--i >= 0)
5115                 reset_control_assert(qmp->resets[i]);
5116
5117         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5118
5119         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
5120
5121         mutex_unlock(&qmp->phy_mutex);
5122
5123         return 0;
5124 }
5125
5126 static int qcom_qmp_phy_init(struct phy *phy)
5127 {
5128         struct qmp_phy *qphy = phy_get_drvdata(phy);
5129         struct qcom_qmp *qmp = qphy->qmp;
5130         const struct qmp_phy_cfg *cfg = qphy->cfg;
5131         int ret;
5132         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
5133
5134         if (cfg->no_pcs_sw_reset) {
5135                 /*
5136                  * Get UFS reset, which is delayed until now to avoid a
5137                  * circular dependency where UFS needs its PHY, but the PHY
5138                  * needs this UFS reset.
5139                  */
5140                 if (!qmp->ufs_reset) {
5141                         qmp->ufs_reset =
5142                                 devm_reset_control_get_exclusive(qmp->dev,
5143                                                                  "ufsphy");
5144
5145                         if (IS_ERR(qmp->ufs_reset)) {
5146                                 ret = PTR_ERR(qmp->ufs_reset);
5147                                 dev_err(qmp->dev,
5148                                         "failed to get UFS reset: %d\n",
5149                                         ret);
5150
5151                                 qmp->ufs_reset = NULL;
5152                                 return ret;
5153                         }
5154                 }
5155
5156                 ret = reset_control_assert(qmp->ufs_reset);
5157                 if (ret)
5158                         return ret;
5159         }
5160
5161         ret = qcom_qmp_phy_com_init(qphy);
5162         if (ret)
5163                 return ret;
5164
5165         if (cfg->type == PHY_TYPE_DP)
5166                 cfg->dp_aux_init(qphy);
5167
5168         return 0;
5169 }
5170
5171 static int qcom_qmp_phy_power_on(struct phy *phy)
5172 {
5173         struct qmp_phy *qphy = phy_get_drvdata(phy);
5174         struct qcom_qmp *qmp = qphy->qmp;
5175         const struct qmp_phy_cfg *cfg = qphy->cfg;
5176         void __iomem *tx = qphy->tx;
5177         void __iomem *rx = qphy->rx;
5178         void __iomem *pcs = qphy->pcs;
5179         void __iomem *pcs_misc = qphy->pcs_misc;
5180         void __iomem *status;
5181         unsigned int mask, val, ready;
5182         int ret;
5183
5184         qcom_qmp_phy_serdes_init(qphy);
5185
5186         if (cfg->has_lane_rst) {
5187                 ret = reset_control_deassert(qphy->lane_rst);
5188                 if (ret) {
5189                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
5190                                 qphy->index);
5191                         goto err_lane_rst;
5192                 }
5193         }
5194
5195         ret = clk_prepare_enable(qphy->pipe_clk);
5196         if (ret) {
5197                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
5198                 goto err_clk_enable;
5199         }
5200
5201         /* Tx, Rx, and PCS configurations */
5202         qcom_qmp_phy_configure_lane(tx, cfg->regs,
5203                                     cfg->tx_tbl, cfg->tx_tbl_num, 1);
5204         if (cfg->tx_tbl_sec)
5205                 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
5206                                             cfg->tx_tbl_num_sec, 1);
5207
5208         /* Configuration for other LANE for USB-DP combo PHY */
5209         if (cfg->is_dual_lane_phy) {
5210                 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
5211                                             cfg->tx_tbl, cfg->tx_tbl_num, 2);
5212                 if (cfg->tx_tbl_sec)
5213                         qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
5214                                                     cfg->tx_tbl_sec,
5215                                                     cfg->tx_tbl_num_sec, 2);
5216         }
5217
5218         /* Configure special DP tx tunings */
5219         if (cfg->type == PHY_TYPE_DP)
5220                 cfg->configure_dp_tx(qphy);
5221
5222         qcom_qmp_phy_configure_lane(rx, cfg->regs,
5223                                     cfg->rx_tbl, cfg->rx_tbl_num, 1);
5224         if (cfg->rx_tbl_sec)
5225                 qcom_qmp_phy_configure_lane(rx, cfg->regs,
5226                                             cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
5227
5228         if (cfg->is_dual_lane_phy) {
5229                 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
5230                                             cfg->rx_tbl, cfg->rx_tbl_num, 2);
5231                 if (cfg->rx_tbl_sec)
5232                         qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
5233                                                     cfg->rx_tbl_sec,
5234                                                     cfg->rx_tbl_num_sec, 2);
5235         }
5236
5237         /* Configure link rate, swing, etc. */
5238         if (cfg->type == PHY_TYPE_DP) {
5239                 cfg->configure_dp_phy(qphy);
5240         } else {
5241                 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
5242                 if (cfg->pcs_tbl_sec)
5243                         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
5244                                                cfg->pcs_tbl_num_sec);
5245         }
5246
5247         ret = reset_control_deassert(qmp->ufs_reset);
5248         if (ret)
5249                 goto err_lane_rst;
5250
5251         qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
5252                                cfg->pcs_misc_tbl_num);
5253         if (cfg->pcs_misc_tbl_sec)
5254                 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
5255                                        cfg->pcs_misc_tbl_num_sec);
5256
5257         /*
5258          * Pull out PHY from POWER DOWN state.
5259          * This is active low enable signal to power-down PHY.
5260          */
5261         if(cfg->type == PHY_TYPE_PCIE)
5262                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
5263
5264         if (cfg->has_pwrdn_delay)
5265                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
5266
5267         if (cfg->type != PHY_TYPE_DP) {
5268                 /* Pull PHY out of reset state */
5269                 if (!cfg->no_pcs_sw_reset)
5270                         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5271                 /* start SerDes and Phy-Coding-Sublayer */
5272                 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5273
5274                 if (cfg->type == PHY_TYPE_UFS) {
5275                         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
5276                         mask = PCS_READY;
5277                         ready = PCS_READY;
5278                 } else {
5279                         status = pcs + cfg->regs[QPHY_PCS_STATUS];
5280                         mask = cfg->phy_status;
5281                         ready = 0;
5282                 }
5283
5284                 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
5285                                          PHY_INIT_COMPLETE_TIMEOUT);
5286                 if (ret) {
5287                         dev_err(qmp->dev, "phy initialization timed-out\n");
5288                         goto err_pcs_ready;
5289                 }
5290         }
5291         return 0;
5292
5293 err_pcs_ready:
5294         clk_disable_unprepare(qphy->pipe_clk);
5295 err_clk_enable:
5296         if (cfg->has_lane_rst)
5297                 reset_control_assert(qphy->lane_rst);
5298 err_lane_rst:
5299         return ret;
5300 }
5301
5302 static int qcom_qmp_phy_power_off(struct phy *phy)
5303 {
5304         struct qmp_phy *qphy = phy_get_drvdata(phy);
5305         const struct qmp_phy_cfg *cfg = qphy->cfg;
5306
5307         clk_disable_unprepare(qphy->pipe_clk);
5308
5309         if (cfg->type == PHY_TYPE_DP) {
5310                 /* Assert DP PHY power down */
5311                 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
5312         } else {
5313                 /* PHY reset */
5314                 if (!cfg->no_pcs_sw_reset)
5315                         qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5316
5317                 /* stop SerDes and Phy-Coding-Sublayer */
5318                 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5319
5320                 /* Put PHY into POWER DOWN state: active low */
5321                 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
5322                         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5323                                      cfg->pwrdn_ctrl);
5324                 } else {
5325                         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
5326                                         cfg->pwrdn_ctrl);
5327                 }
5328         }
5329
5330         return 0;
5331 }
5332
5333 static int qcom_qmp_phy_exit(struct phy *phy)
5334 {
5335         struct qmp_phy *qphy = phy_get_drvdata(phy);
5336         const struct qmp_phy_cfg *cfg = qphy->cfg;
5337
5338         if (cfg->has_lane_rst)
5339                 reset_control_assert(qphy->lane_rst);
5340
5341         qcom_qmp_phy_com_exit(qphy);
5342
5343         return 0;
5344 }
5345
5346 static int qcom_qmp_phy_enable(struct phy *phy)
5347 {
5348         int ret;
5349
5350         ret = qcom_qmp_phy_init(phy);
5351         if (ret)
5352                 return ret;
5353
5354         ret = qcom_qmp_phy_power_on(phy);
5355         if (ret)
5356                 qcom_qmp_phy_exit(phy);
5357
5358         return ret;
5359 }
5360
5361 static int qcom_qmp_phy_disable(struct phy *phy)
5362 {
5363         int ret;
5364
5365         ret = qcom_qmp_phy_power_off(phy);
5366         if (ret)
5367                 return ret;
5368         return qcom_qmp_phy_exit(phy);
5369 }
5370
5371 static int qcom_qmp_phy_set_mode(struct phy *phy,
5372                                  enum phy_mode mode, int submode)
5373 {
5374         struct qmp_phy *qphy = phy_get_drvdata(phy);
5375
5376         qphy->mode = mode;
5377
5378         return 0;
5379 }
5380
5381 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
5382 {
5383         const struct qmp_phy_cfg *cfg = qphy->cfg;
5384         void __iomem *pcs = qphy->pcs;
5385         void __iomem *pcs_misc = qphy->pcs_misc;
5386         u32 intr_mask;
5387
5388         if (qphy->mode == PHY_MODE_USB_HOST_SS ||
5389             qphy->mode == PHY_MODE_USB_DEVICE_SS)
5390                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
5391         else
5392                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
5393
5394         /* Clear any pending interrupts status */
5395         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5396         /* Writing 1 followed by 0 clears the interrupt */
5397         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5398
5399         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5400                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
5401
5402         /* Enable required PHY autonomous mode interrupts */
5403         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
5404
5405         /* Enable i/o clamp_n for autonomous mode */
5406         if (pcs_misc)
5407                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5408 }
5409
5410 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
5411 {
5412         const struct qmp_phy_cfg *cfg = qphy->cfg;
5413         void __iomem *pcs = qphy->pcs;
5414         void __iomem *pcs_misc = qphy->pcs_misc;
5415
5416         /* Disable i/o clamp_n on resume for normal mode */
5417         if (pcs_misc)
5418                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5419
5420         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5421                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
5422
5423         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5424         /* Writing 1 followed by 0 clears the interrupt */
5425         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5426 }
5427
5428 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
5429 {
5430         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5431         struct qmp_phy *qphy = qmp->phys[0];
5432         const struct qmp_phy_cfg *cfg = qphy->cfg;
5433
5434         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
5435
5436         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5437         if (cfg->type != PHY_TYPE_USB3)
5438                 return 0;
5439
5440         if (!qmp->init_count) {
5441                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5442                 return 0;
5443         }
5444
5445         qcom_qmp_phy_enable_autonomous_mode(qphy);
5446
5447         clk_disable_unprepare(qphy->pipe_clk);
5448         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5449
5450         return 0;
5451 }
5452
5453 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
5454 {
5455         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5456         struct qmp_phy *qphy = qmp->phys[0];
5457         const struct qmp_phy_cfg *cfg = qphy->cfg;
5458         int ret = 0;
5459
5460         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
5461
5462         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5463         if (cfg->type != PHY_TYPE_USB3)
5464                 return 0;
5465
5466         if (!qmp->init_count) {
5467                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5468                 return 0;
5469         }
5470
5471         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5472         if (ret)
5473                 return ret;
5474
5475         ret = clk_prepare_enable(qphy->pipe_clk);
5476         if (ret) {
5477                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
5478                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5479                 return ret;
5480         }
5481
5482         qcom_qmp_phy_disable_autonomous_mode(qphy);
5483
5484         return 0;
5485 }
5486
5487 static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5488 {
5489         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5490         int num = cfg->num_vregs;
5491         int i;
5492
5493         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
5494         if (!qmp->vregs)
5495                 return -ENOMEM;
5496
5497         for (i = 0; i < num; i++)
5498                 qmp->vregs[i].supply = cfg->vreg_list[i];
5499
5500         return devm_regulator_bulk_get(dev, num, qmp->vregs);
5501 }
5502
5503 static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5504 {
5505         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5506         int i;
5507
5508         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
5509                                    sizeof(*qmp->resets), GFP_KERNEL);
5510         if (!qmp->resets)
5511                 return -ENOMEM;
5512
5513         for (i = 0; i < cfg->num_resets; i++) {
5514                 struct reset_control *rst;
5515                 const char *name = cfg->reset_list[i];
5516
5517                 rst = devm_reset_control_get(dev, name);
5518                 if (IS_ERR(rst)) {
5519                         dev_err(dev, "failed to get %s reset\n", name);
5520                         return PTR_ERR(rst);
5521                 }
5522                 qmp->resets[i] = rst;
5523         }
5524
5525         return 0;
5526 }
5527
5528 static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5529 {
5530         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5531         int num = cfg->num_clks;
5532         int i;
5533
5534         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
5535         if (!qmp->clks)
5536                 return -ENOMEM;
5537
5538         for (i = 0; i < num; i++)
5539                 qmp->clks[i].id = cfg->clk_list[i];
5540
5541         return devm_clk_bulk_get(dev, num, qmp->clks);
5542 }
5543
5544 static void phy_clk_release_provider(void *res)
5545 {
5546         of_clk_del_provider(res);
5547 }
5548
5549 /*
5550  * Register a fixed rate pipe clock.
5551  *
5552  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
5553  * controls it. The <s>_pipe_clk coming out of the GCC is requested
5554  * by the PHY driver for its operations.
5555  * We register the <s>_pipe_clksrc here. The gcc driver takes care
5556  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
5557  * Below picture shows this relationship.
5558  *
5559  *         +---------------+
5560  *         |   PHY block   |<<---------------------------------------+
5561  *         |               |                                         |
5562  *         |   +-------+   |                   +-----+               |
5563  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
5564  *    clk  |   +-------+   |                   +-----+
5565  *         +---------------+
5566  */
5567 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
5568 {
5569         struct clk_fixed_rate *fixed;
5570         struct clk_init_data init = { };
5571         int ret;
5572
5573         ret = of_property_read_string(np, "clock-output-names", &init.name);
5574         if (ret) {
5575                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
5576                 return ret;
5577         }
5578
5579         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
5580         if (!fixed)
5581                 return -ENOMEM;
5582
5583         init.ops = &clk_fixed_rate_ops;
5584
5585         /* controllers using QMP phys use 125MHz pipe clock interface */
5586         fixed->fixed_rate = 125000000;
5587         fixed->hw.init = &init;
5588
5589         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
5590         if (ret)
5591                 return ret;
5592
5593         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
5594         if (ret)
5595                 return ret;
5596
5597         /*
5598          * Roll a devm action because the clock provider is the child node, but
5599          * the child node is not actually a device.
5600          */
5601         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5602 }
5603
5604 /*
5605  * Display Port PLL driver block diagram for branch clocks
5606  *
5607  *              +------------------------------+
5608  *              |         DP_VCO_CLK           |
5609  *              |                              |
5610  *              |    +-------------------+     |
5611  *              |    |   (DP PLL/VCO)    |     |
5612  *              |    +---------+---------+     |
5613  *              |              v               |
5614  *              |   +----------+-----------+   |
5615  *              |   | hsclk_divsel_clk_src |   |
5616  *              |   +----------+-----------+   |
5617  *              +------------------------------+
5618  *                              |
5619  *          +---------<---------v------------>----------+
5620  *          |                                           |
5621  * +--------v----------------+                          |
5622  * |    dp_phy_pll_link_clk  |                          |
5623  * |     link_clk            |                          |
5624  * +--------+----------------+                          |
5625  *          |                                           |
5626  *          |                                           |
5627  *          v                                           v
5628  * Input to DISPCC block                                |
5629  * for link clk, crypto clk                             |
5630  * and interface clock                                  |
5631  *                                                      |
5632  *                                                      |
5633  *      +--------<------------+-----------------+---<---+
5634  *      |                     |                 |
5635  * +----v---------+  +--------v-----+  +--------v------+
5636  * | vco_divided  |  | vco_divided  |  | vco_divided   |
5637  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
5638  * |              |  |              |  |               |
5639  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
5640  * +-------+------+  +-----+--------+  +--------+------+
5641  *         |                 |                  |
5642  *         v---->----------v-------------<------v
5643  *                         |
5644  *              +----------+-----------------+
5645  *              |   dp_phy_pll_vco_div_clk   |
5646  *              +---------+------------------+
5647  *                        |
5648  *                        v
5649  *              Input to DISPCC block
5650  *              for DP pixel clock
5651  *
5652  */
5653 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
5654                                                 struct clk_rate_request *req)
5655 {
5656         switch (req->rate) {
5657         case 1620000000UL / 2:
5658         case 2700000000UL / 2:
5659         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
5660                 return 0;
5661         default:
5662                 return -EINVAL;
5663         }
5664 }
5665
5666 static unsigned long
5667 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5668 {
5669         const struct qmp_phy_dp_clks *dp_clks;
5670         const struct qmp_phy *qphy;
5671         const struct phy_configure_opts_dp *dp_opts;
5672
5673         dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
5674         qphy = dp_clks->qphy;
5675         dp_opts = &qphy->dp_opts;
5676
5677         switch (dp_opts->link_rate) {
5678         case 1620:
5679                 return 1620000000UL / 2;
5680         case 2700:
5681                 return 2700000000UL / 2;
5682         case 5400:
5683                 return 5400000000UL / 4;
5684         case 8100:
5685                 return 8100000000UL / 6;
5686         default:
5687                 return 0;
5688         }
5689 }
5690
5691 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
5692         .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
5693         .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
5694 };
5695
5696 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
5697                                                struct clk_rate_request *req)
5698 {
5699         switch (req->rate) {
5700         case 162000000:
5701         case 270000000:
5702         case 540000000:
5703         case 810000000:
5704                 return 0;
5705         default:
5706                 return -EINVAL;
5707         }
5708 }
5709
5710 static unsigned long
5711 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5712 {
5713         const struct qmp_phy_dp_clks *dp_clks;
5714         const struct qmp_phy *qphy;
5715         const struct phy_configure_opts_dp *dp_opts;
5716
5717         dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
5718         qphy = dp_clks->qphy;
5719         dp_opts = &qphy->dp_opts;
5720
5721         switch (dp_opts->link_rate) {
5722         case 1620:
5723         case 2700:
5724         case 5400:
5725         case 8100:
5726                 return dp_opts->link_rate * 100000;
5727         default:
5728                 return 0;
5729         }
5730 }
5731
5732 static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
5733         .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
5734         .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
5735 };
5736
5737 static struct clk_hw *
5738 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5739 {
5740         struct qmp_phy_dp_clks *dp_clks = data;
5741         unsigned int idx = clkspec->args[0];
5742
5743         if (idx >= 2) {
5744                 pr_err("%s: invalid index %u\n", __func__, idx);
5745                 return ERR_PTR(-EINVAL);
5746         }
5747
5748         if (idx == 0)
5749                 return &dp_clks->dp_link_hw;
5750
5751         return &dp_clks->dp_pixel_hw;
5752 }
5753
5754 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5755                                 struct device_node *np)
5756 {
5757         struct clk_init_data init = { };
5758         struct qmp_phy_dp_clks *dp_clks;
5759         char name[64];
5760         int ret;
5761
5762         dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5763         if (!dp_clks)
5764                 return -ENOMEM;
5765
5766         dp_clks->qphy = qphy;
5767         qphy->dp_clks = dp_clks;
5768
5769         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
5770         init.ops = &qcom_qmp_dp_link_clk_ops;
5771         init.name = name;
5772         dp_clks->dp_link_hw.init = &init;
5773         ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5774         if (ret)
5775                 return ret;
5776
5777         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
5778         init.ops = &qcom_qmp_dp_pixel_clk_ops;
5779         init.name = name;
5780         dp_clks->dp_pixel_hw.init = &init;
5781         ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5782         if (ret)
5783                 return ret;
5784
5785         ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5786         if (ret)
5787                 return ret;
5788
5789         /*
5790          * Roll a devm action because the clock provider is the child node, but
5791          * the child node is not actually a device.
5792          */
5793         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5794 }
5795
5796 static const struct phy_ops qcom_qmp_phy_gen_ops = {
5797         .init           = qcom_qmp_phy_enable,
5798         .exit           = qcom_qmp_phy_disable,
5799         .set_mode       = qcom_qmp_phy_set_mode,
5800         .owner          = THIS_MODULE,
5801 };
5802
5803 static const struct phy_ops qcom_qmp_phy_dp_ops = {
5804         .init           = qcom_qmp_phy_init,
5805         .configure      = qcom_qmp_dp_phy_configure,
5806         .power_on       = qcom_qmp_phy_power_on,
5807         .calibrate      = qcom_qmp_dp_phy_calibrate,
5808         .power_off      = qcom_qmp_phy_power_off,
5809         .exit           = qcom_qmp_phy_exit,
5810         .set_mode       = qcom_qmp_phy_set_mode,
5811         .owner          = THIS_MODULE,
5812 };
5813
5814 static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
5815         .power_on       = qcom_qmp_phy_enable,
5816         .power_off      = qcom_qmp_phy_disable,
5817         .set_mode       = qcom_qmp_phy_set_mode,
5818         .owner          = THIS_MODULE,
5819 };
5820
5821 static
5822 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5823                         void __iomem *serdes, const struct qmp_phy_cfg *cfg)
5824 {
5825         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5826         struct phy *generic_phy;
5827         struct qmp_phy *qphy;
5828         const struct phy_ops *ops;
5829         char prop_name[MAX_PROP_NAME];
5830         int ret;
5831
5832         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5833         if (!qphy)
5834                 return -ENOMEM;
5835
5836         qphy->cfg = cfg;
5837         qphy->serdes = serdes;
5838         /*
5839          * Get memory resources for each phy lane:
5840          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5841          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5842          * For single lane PHYs: pcs_misc (optional) -> 3.
5843          */
5844         qphy->tx = of_iomap(np, 0);
5845         if (!qphy->tx)
5846                 return -ENOMEM;
5847
5848         qphy->rx = of_iomap(np, 1);
5849         if (!qphy->rx)
5850                 return -ENOMEM;
5851
5852         qphy->pcs = of_iomap(np, 2);
5853         if (!qphy->pcs)
5854                 return -ENOMEM;
5855
5856         /*
5857          * If this is a dual-lane PHY, then there should be registers for the
5858          * second lane. Some old device trees did not specify this, so fall
5859          * back to old legacy behavior of assuming they can be reached at an
5860          * offset from the first lane.
5861          */
5862         if (cfg->is_dual_lane_phy) {
5863                 qphy->tx2 = of_iomap(np, 3);
5864                 qphy->rx2 = of_iomap(np, 4);
5865                 if (!qphy->tx2 || !qphy->rx2) {
5866                         dev_warn(dev,
5867                                  "Underspecified device tree, falling back to legacy register regions\n");
5868
5869                         /* In the old version, pcs_misc is at index 3. */
5870                         qphy->pcs_misc = qphy->tx2;
5871                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5872                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5873
5874                 } else {
5875                         qphy->pcs_misc = of_iomap(np, 5);
5876                 }
5877
5878         } else {
5879                 qphy->pcs_misc = of_iomap(np, 3);
5880         }
5881
5882         if (!qphy->pcs_misc)
5883                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5884
5885         /*
5886          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5887          * based phys, so they essentially have pipe clock. So,
5888          * we return error in case phy is USB3 or PIPE type.
5889          * Otherwise, we initialize pipe clock to NULL for
5890          * all phys that don't need this.
5891          */
5892         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5893         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
5894         if (IS_ERR(qphy->pipe_clk)) {
5895                 if (cfg->type == PHY_TYPE_PCIE ||
5896                     cfg->type == PHY_TYPE_USB3) {
5897                         ret = PTR_ERR(qphy->pipe_clk);
5898                         if (ret != -EPROBE_DEFER)
5899                                 dev_err(dev,
5900                                         "failed to get lane%d pipe_clk, %d\n",
5901                                         id, ret);
5902                         return ret;
5903                 }
5904                 qphy->pipe_clk = NULL;
5905         }
5906
5907         /* Get lane reset, if any */
5908         if (cfg->has_lane_rst) {
5909                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5910                 qphy->lane_rst = of_reset_control_get(np, prop_name);
5911                 if (IS_ERR(qphy->lane_rst)) {
5912                         dev_err(dev, "failed to get lane%d reset\n", id);
5913                         return PTR_ERR(qphy->lane_rst);
5914                 }
5915         }
5916
5917         if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
5918                 ops = &qcom_qmp_pcie_ufs_ops;
5919         else if (cfg->type == PHY_TYPE_DP)
5920                 ops = &qcom_qmp_phy_dp_ops;
5921         else
5922                 ops = &qcom_qmp_phy_gen_ops;
5923
5924         generic_phy = devm_phy_create(dev, np, ops);
5925         if (IS_ERR(generic_phy)) {
5926                 ret = PTR_ERR(generic_phy);
5927                 dev_err(dev, "failed to create qphy %d\n", ret);
5928                 return ret;
5929         }
5930
5931         qphy->phy = generic_phy;
5932         qphy->index = id;
5933         qphy->qmp = qmp;
5934         qmp->phys[id] = qphy;
5935         phy_set_drvdata(generic_phy, qphy);
5936
5937         return 0;
5938 }
5939
5940 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
5941         {
5942                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
5943                 .data = &ipq8074_usb3phy_cfg,
5944         }, {
5945                 .compatible = "qcom,msm8996-qmp-pcie-phy",
5946                 .data = &msm8996_pciephy_cfg,
5947         }, {
5948                 .compatible = "qcom,msm8996-qmp-ufs-phy",
5949                 .data = &msm8996_ufs_cfg,
5950         }, {
5951                 .compatible = "qcom,msm8996-qmp-usb3-phy",
5952                 .data = &msm8996_usb3phy_cfg,
5953         }, {
5954                 .compatible = "qcom,msm8998-qmp-pcie-phy",
5955                 .data = &msm8998_pciephy_cfg,
5956         }, {
5957                 .compatible = "qcom,msm8998-qmp-ufs-phy",
5958                 .data = &sdm845_ufsphy_cfg,
5959         }, {
5960                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5961                 .data = &ipq8074_pciephy_cfg,
5962         }, {
5963                 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5964                 .data = &ipq6018_pciephy_cfg,
5965         }, {
5966                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
5967                 .data = &ipq8074_usb3phy_cfg,
5968         }, {
5969                 .compatible = "qcom,sc7180-qmp-usb3-phy",
5970                 .data = &sc7180_usb3phy_cfg,
5971         }, {
5972                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5973                 /* It's a combo phy */
5974         }, {
5975                 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5976                 .data = &sc8180x_pciephy_cfg,
5977         }, {
5978                 .compatible = "qcom,sc8180x-qmp-ufs-phy",
5979                 .data = &sm8150_ufsphy_cfg,
5980         }, {
5981                 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
5982                 .data = &sm8350_ufsphy_cfg,
5983         }, {
5984                 .compatible = "qcom,sc8180x-qmp-usb3-phy",
5985                 .data = &sm8150_usb3phy_cfg,
5986         }, {
5987                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5988                 /* It's a combo phy */
5989         }, {
5990                 .compatible = "qcom,sdm845-qhp-pcie-phy",
5991                 .data = &sdm845_qhp_pciephy_cfg,
5992         }, {
5993                 .compatible = "qcom,sdm845-qmp-pcie-phy",
5994                 .data = &sdm845_qmp_pciephy_cfg,
5995         }, {
5996                 .compatible = "qcom,sdm845-qmp-usb3-phy",
5997                 .data = &qmp_v3_usb3phy_cfg,
5998         }, {
5999                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
6000                 .data = &qmp_v3_usb3_uniphy_cfg,
6001         }, {
6002                 .compatible = "qcom,sdm845-qmp-ufs-phy",
6003                 .data = &sdm845_ufsphy_cfg,
6004         }, {
6005                 .compatible = "qcom,msm8998-qmp-usb3-phy",
6006                 .data = &msm8998_usb3phy_cfg,
6007         }, {
6008                 .compatible = "qcom,sm6115-qmp-ufs-phy",
6009                 .data = &sm6115_ufsphy_cfg,
6010         }, {
6011                 .compatible = "qcom,sm8150-qmp-ufs-phy",
6012                 .data = &sm8150_ufsphy_cfg,
6013         }, {
6014                 .compatible = "qcom,sm8250-qmp-ufs-phy",
6015                 .data = &sm8150_ufsphy_cfg,
6016         }, {
6017                 .compatible = "qcom,sm8150-qmp-usb3-phy",
6018                 .data = &sm8150_usb3phy_cfg,
6019         }, {
6020                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
6021                 .data = &sm8150_usb3_uniphy_cfg,
6022         }, {
6023                 .compatible = "qcom,sm8250-qmp-usb3-phy",
6024                 .data = &sm8250_usb3phy_cfg,
6025         }, {
6026                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
6027                 /* It's a combo phy */
6028         }, {
6029                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
6030                 .data = &sm8250_usb3_uniphy_cfg,
6031         }, {
6032                 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
6033                 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
6034         }, {
6035                 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
6036                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
6037         }, {
6038                 .compatible = "qcom,sm8350-qmp-ufs-phy",
6039                 .data = &sm8350_ufsphy_cfg,
6040         }, {
6041                 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
6042                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
6043         }, {
6044                 .compatible = "qcom,sdx55-qmp-pcie-phy",
6045                 .data = &sdx55_qmp_pciephy_cfg,
6046         }, {
6047                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
6048                 .data = &sdx55_usb3_uniphy_cfg,
6049         }, {
6050                 .compatible = "qcom,sm8350-qmp-usb3-phy",
6051                 .data = &sm8350_usb3phy_cfg,
6052         }, {
6053                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
6054                 .data = &sm8350_usb3_uniphy_cfg,
6055         }, {
6056                 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
6057                 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
6058         }, {
6059                 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
6060                 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
6061         }, {
6062                 .compatible = "qcom,sm8450-qmp-ufs-phy",
6063                 .data = &sm8450_ufsphy_cfg,
6064         }, {
6065                 .compatible = "qcom,sm8450-qmp-usb3-phy",
6066                 .data = &sm8350_usb3phy_cfg,
6067         }, {
6068                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
6069                 .data = &qcm2290_usb3phy_cfg,
6070         },
6071         { },
6072 };
6073 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
6074
6075 static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
6076         {
6077                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
6078                 .data = &sc7180_usb3dpphy_cfg,
6079         },
6080         {
6081                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
6082                 .data = &sm8250_usb3dpphy_cfg,
6083         },
6084         {
6085                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
6086                 .data = &sc8180x_usb3dpphy_cfg,
6087         },
6088         { }
6089 };
6090
6091 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
6092         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
6093                            qcom_qmp_phy_runtime_resume, NULL)
6094 };
6095
6096 static int qcom_qmp_phy_probe(struct platform_device *pdev)
6097 {
6098         struct qcom_qmp *qmp;
6099         struct device *dev = &pdev->dev;
6100         struct device_node *child;
6101         struct phy_provider *phy_provider;
6102         void __iomem *serdes;
6103         void __iomem *usb_serdes;
6104         void __iomem *dp_serdes = NULL;
6105         const struct qmp_phy_combo_cfg *combo_cfg = NULL;
6106         const struct qmp_phy_cfg *cfg = NULL;
6107         const struct qmp_phy_cfg *usb_cfg = NULL;
6108         const struct qmp_phy_cfg *dp_cfg = NULL;
6109         int num, id, expected_phys;
6110         int ret;
6111
6112         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
6113         if (!qmp)
6114                 return -ENOMEM;
6115
6116         qmp->dev = dev;
6117         dev_set_drvdata(dev, qmp);
6118
6119         /* Get the specific init parameters of QMP phy */
6120         cfg = of_device_get_match_data(dev);
6121         if (!cfg) {
6122                 const struct of_device_id *match;
6123
6124                 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
6125                 if (!match)
6126                         return -EINVAL;
6127
6128                 combo_cfg = match->data;
6129                 if (!combo_cfg)
6130                         return -EINVAL;
6131
6132                 usb_cfg = combo_cfg->usb_cfg;
6133                 cfg = usb_cfg; /* Setup clks and regulators */
6134         }
6135
6136         /* per PHY serdes; usually located at base address */
6137         usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
6138         if (IS_ERR(serdes))
6139                 return PTR_ERR(serdes);
6140
6141         /* per PHY dp_com; if PHY has dp_com control block */
6142         if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
6143                 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
6144                 if (IS_ERR(qmp->dp_com))
6145                         return PTR_ERR(qmp->dp_com);
6146         }
6147
6148         if (combo_cfg) {
6149                 /* Only two serdes for combo PHY */
6150                 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
6151                 if (IS_ERR(dp_serdes))
6152                         return PTR_ERR(dp_serdes);
6153
6154                 dp_cfg = combo_cfg->dp_cfg;
6155                 expected_phys = 2;
6156         } else {
6157                 expected_phys = cfg->nlanes;
6158         }
6159
6160         mutex_init(&qmp->phy_mutex);
6161
6162         ret = qcom_qmp_phy_clk_init(dev, cfg);
6163         if (ret)
6164                 return ret;
6165
6166         ret = qcom_qmp_phy_reset_init(dev, cfg);
6167         if (ret)
6168                 return ret;
6169
6170         ret = qcom_qmp_phy_vreg_init(dev, cfg);
6171         if (ret) {
6172                 if (ret != -EPROBE_DEFER)
6173                         dev_err(dev, "failed to get regulator supplies: %d\n",
6174                                 ret);
6175                 return ret;
6176         }
6177
6178         num = of_get_available_child_count(dev->of_node);
6179         /* do we have a rogue child node ? */
6180         if (num > expected_phys)
6181                 return -EINVAL;
6182
6183         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
6184         if (!qmp->phys)
6185                 return -ENOMEM;
6186
6187         pm_runtime_set_active(dev);
6188         pm_runtime_enable(dev);
6189         /*
6190          * Prevent runtime pm from being ON by default. Users can enable
6191          * it using power/control in sysfs.
6192          */
6193         pm_runtime_forbid(dev);
6194
6195         id = 0;
6196         for_each_available_child_of_node(dev->of_node, child) {
6197                 if (of_node_name_eq(child, "dp-phy")) {
6198                         cfg = dp_cfg;
6199                         serdes = dp_serdes;
6200                 } else if (of_node_name_eq(child, "usb3-phy")) {
6201                         cfg = usb_cfg;
6202                         serdes = usb_serdes;
6203                 }
6204
6205                 /* Create per-lane phy */
6206                 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
6207                 if (ret) {
6208                         dev_err(dev, "failed to create lane%d phy, %d\n",
6209                                 id, ret);
6210                         goto err_node_put;
6211                 }
6212
6213                 /*
6214                  * Register the pipe clock provided by phy.
6215                  * See function description to see details of this pipe clock.
6216                  */
6217                 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
6218                         ret = phy_pipe_clk_register(qmp, child);
6219                         if (ret) {
6220                                 dev_err(qmp->dev,
6221                                         "failed to register pipe clock source\n");
6222                                 goto err_node_put;
6223                         }
6224                 } else if (cfg->type == PHY_TYPE_DP) {
6225                         ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
6226                         if (ret) {
6227                                 dev_err(qmp->dev,
6228                                         "failed to register DP clock source\n");
6229                                 goto err_node_put;
6230                         }
6231                 }
6232                 id++;
6233         }
6234
6235         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
6236         if (!IS_ERR(phy_provider))
6237                 dev_info(dev, "Registered Qcom-QMP phy\n");
6238         else
6239                 pm_runtime_disable(dev);
6240
6241         return PTR_ERR_OR_ZERO(phy_provider);
6242
6243 err_node_put:
6244         pm_runtime_disable(dev);
6245         of_node_put(child);
6246         return ret;
6247 }
6248
6249 static struct platform_driver qcom_qmp_phy_driver = {
6250         .probe          = qcom_qmp_phy_probe,
6251         .driver = {
6252                 .name   = "qcom-qmp-phy",
6253                 .pm     = &qcom_qmp_phy_pm_ops,
6254                 .of_match_table = qcom_qmp_phy_of_match_table,
6255         },
6256 };
6257
6258 module_platform_driver(qcom_qmp_phy_driver);
6259
6260 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
6261 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
6262 MODULE_LICENSE("GPL v2");