1 // SPDX-License-Identifier: GPL-2.0+
3 * drivers/net/phy/marvell.c
5 * Driver for Marvell PHYs
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
13 #include <linux/kernel.h>
14 #include <linux/string.h>
15 #include <linux/ctype.h>
16 #include <linux/errno.h>
17 #include <linux/unistd.h>
18 #include <linux/hwmon.h>
19 #include <linux/interrupt.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/spinlock.h>
27 #include <linux/module.h>
28 #include <linux/mii.h>
29 #include <linux/ethtool.h>
30 #include <linux/ethtool_netlink.h>
31 #include <linux/phy.h>
32 #include <linux/marvell_phy.h>
33 #include <linux/bitfield.h>
38 #include <linux/uaccess.h>
40 #define MII_MARVELL_PHY_PAGE 22
41 #define MII_MARVELL_COPPER_PAGE 0x00
42 #define MII_MARVELL_FIBER_PAGE 0x01
43 #define MII_MARVELL_MSCR_PAGE 0x02
44 #define MII_MARVELL_LED_PAGE 0x03
45 #define MII_MARVELL_VCT5_PAGE 0x05
46 #define MII_MARVELL_MISC_TEST_PAGE 0x06
47 #define MII_MARVELL_VCT7_PAGE 0x07
48 #define MII_MARVELL_WOL_PAGE 0x11
50 #define MII_M1011_IEVENT 0x13
51 #define MII_M1011_IEVENT_CLEAR 0x0000
53 #define MII_M1011_IMASK 0x12
54 #define MII_M1011_IMASK_INIT 0x6400
55 #define MII_M1011_IMASK_CLEAR 0x0000
57 #define MII_M1011_PHY_SCR 0x10
58 #define MII_M1011_PHY_SCR_DOWNSHIFT_EN BIT(11)
59 #define MII_M1011_PHY_SCR_DOWNSHIFT_MASK GENMASK(14, 12)
60 #define MII_M1011_PHY_SCR_DOWNSHIFT_MAX 8
61 #define MII_M1011_PHY_SCR_MDI (0x0 << 5)
62 #define MII_M1011_PHY_SCR_MDI_X (0x1 << 5)
63 #define MII_M1011_PHY_SCR_AUTO_CROSS (0x3 << 5)
65 #define MII_M1011_PHY_SSR 0x11
66 #define MII_M1011_PHY_SSR_DOWNSHIFT BIT(5)
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK GENMASK(11, 9)
73 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX 8
74 #define MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN BIT(8)
75 #define MII_M1111_RGMII_RX_DELAY BIT(7)
76 #define MII_M1111_RGMII_TX_DELAY BIT(1)
77 #define MII_M1111_PHY_EXT_SR 0x1b
79 #define MII_M1111_HWCFG_MODE_MASK 0xf
80 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
81 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
82 #define MII_M1111_HWCFG_MODE_RTBI 0x7
83 #define MII_M1111_HWCFG_MODE_COPPER_1000X_AN 0x8
84 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
85 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
86 #define MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN 0xc
87 #define MII_M1111_HWCFG_SERIAL_AN_BYPASS BIT(12)
88 #define MII_M1111_HWCFG_FIBER_COPPER_RES BIT(13)
89 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO BIT(15)
91 #define MII_88E1121_PHY_MSCR_REG 21
92 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
93 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
94 #define MII_88E1121_PHY_MSCR_DELAY_MASK (BIT(5) | BIT(4))
96 #define MII_88E1121_MISC_TEST 0x1a
97 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK 0x1f00
98 #define MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT 8
99 #define MII_88E1510_MISC_TEST_TEMP_IRQ_EN BIT(7)
100 #define MII_88E1510_MISC_TEST_TEMP_IRQ BIT(6)
101 #define MII_88E1121_MISC_TEST_TEMP_SENSOR_EN BIT(5)
102 #define MII_88E1121_MISC_TEST_TEMP_MASK 0x1f
104 #define MII_88E1510_TEMP_SENSOR 0x1b
105 #define MII_88E1510_TEMP_SENSOR_MASK 0xff
107 #define MII_88E1540_COPPER_CTRL3 0x1a
108 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK GENMASK(11, 10)
109 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS 0
110 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS 1
111 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS 2
112 #define MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS 3
113 #define MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN BIT(9)
115 #define MII_88E6390_MISC_TEST 0x1b
116 #define MII_88E6390_MISC_TEST_SAMPLE_1S 0
117 #define MII_88E6390_MISC_TEST_SAMPLE_10MS BIT(14)
118 #define MII_88E6390_MISC_TEST_SAMPLE_DISABLE BIT(15)
119 #define MII_88E6390_MISC_TEST_SAMPLE_ENABLE 0
120 #define MII_88E6390_MISC_TEST_SAMPLE_MASK (0x3 << 14)
122 #define MII_88E6390_TEMP_SENSOR 0x1c
123 #define MII_88E6390_TEMP_SENSOR_MASK 0xff
124 #define MII_88E6390_TEMP_SENSOR_SAMPLES 10
126 #define MII_88E1318S_PHY_MSCR1_REG 16
127 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
129 /* Copper Specific Interrupt Enable Register */
130 #define MII_88E1318S_PHY_CSIER 0x12
131 /* WOL Event Interrupt Enable */
132 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
134 /* LED Timer Control Register */
135 #define MII_88E1318S_PHY_LED_TCR 0x12
136 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
137 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
138 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
140 /* Magic Packet MAC address registers */
141 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
142 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
143 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
145 #define MII_88E1318S_PHY_WOL_CTRL 0x10
146 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
147 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
149 #define MII_PHY_LED_CTRL 16
150 #define MII_88E1121_PHY_LED_DEF 0x0030
151 #define MII_88E1510_PHY_LED_DEF 0x1177
152 #define MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE 0x1040
154 #define MII_M1011_PHY_STATUS 0x11
155 #define MII_M1011_PHY_STATUS_1000 0x8000
156 #define MII_M1011_PHY_STATUS_100 0x4000
157 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
158 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
159 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
160 #define MII_M1011_PHY_STATUS_LINK 0x0400
162 #define MII_88E3016_PHY_SPEC_CTRL 0x10
163 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
164 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
166 #define MII_88E1510_GEN_CTRL_REG_1 0x14
167 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
168 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
169 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
171 #define MII_VCT5_TX_RX_MDI0_COUPLING 0x10
172 #define MII_VCT5_TX_RX_MDI1_COUPLING 0x11
173 #define MII_VCT5_TX_RX_MDI2_COUPLING 0x12
174 #define MII_VCT5_TX_RX_MDI3_COUPLING 0x13
175 #define MII_VCT5_TX_RX_AMPLITUDE_MASK 0x7f00
176 #define MII_VCT5_TX_RX_AMPLITUDE_SHIFT 8
177 #define MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION BIT(15)
179 #define MII_VCT5_CTRL 0x17
180 #define MII_VCT5_CTRL_ENABLE BIT(15)
181 #define MII_VCT5_CTRL_COMPLETE BIT(14)
182 #define MII_VCT5_CTRL_TX_SAME_CHANNEL (0x0 << 11)
183 #define MII_VCT5_CTRL_TX0_CHANNEL (0x4 << 11)
184 #define MII_VCT5_CTRL_TX1_CHANNEL (0x5 << 11)
185 #define MII_VCT5_CTRL_TX2_CHANNEL (0x6 << 11)
186 #define MII_VCT5_CTRL_TX3_CHANNEL (0x7 << 11)
187 #define MII_VCT5_CTRL_SAMPLES_2 (0x0 << 8)
188 #define MII_VCT5_CTRL_SAMPLES_4 (0x1 << 8)
189 #define MII_VCT5_CTRL_SAMPLES_8 (0x2 << 8)
190 #define MII_VCT5_CTRL_SAMPLES_16 (0x3 << 8)
191 #define MII_VCT5_CTRL_SAMPLES_32 (0x4 << 8)
192 #define MII_VCT5_CTRL_SAMPLES_64 (0x5 << 8)
193 #define MII_VCT5_CTRL_SAMPLES_128 (0x6 << 8)
194 #define MII_VCT5_CTRL_SAMPLES_DEFAULT (0x6 << 8)
195 #define MII_VCT5_CTRL_SAMPLES_256 (0x7 << 8)
196 #define MII_VCT5_CTRL_SAMPLES_SHIFT 8
197 #define MII_VCT5_CTRL_MODE_MAXIMUM_PEEK (0x0 << 6)
198 #define MII_VCT5_CTRL_MODE_FIRST_LAST_PEEK (0x1 << 6)
199 #define MII_VCT5_CTRL_MODE_OFFSET (0x2 << 6)
200 #define MII_VCT5_CTRL_SAMPLE_POINT (0x3 << 6)
201 #define MII_VCT5_CTRL_PEEK_HYST_DEFAULT 3
203 #define MII_VCT5_SAMPLE_POINT_DISTANCE 0x18
204 #define MII_VCT5_SAMPLE_POINT_DISTANCE_MAX 511
205 #define MII_VCT5_TX_PULSE_CTRL 0x1c
206 #define MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN BIT(12)
207 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS (0x0 << 10)
208 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_96nS (0x1 << 10)
209 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_64nS (0x2 << 10)
210 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS (0x3 << 10)
211 #define MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_SHIFT 10
212 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_1000mV (0x0 << 8)
213 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_750mV (0x1 << 8)
214 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_500mV (0x2 << 8)
215 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_250mV (0x3 << 8)
216 #define MII_VCT5_TX_PULSE_CTRL_PULSE_AMPLITUDE_SHIFT 8
217 #define MII_VCT5_TX_PULSE_CTRL_MAX_AMP BIT(7)
218 #define MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV (0x6 << 0)
220 /* For TDR measurements less than 11 meters, a short pulse should be
223 #define TDR_SHORT_CABLE_LENGTH 11
225 #define MII_VCT7_PAIR_0_DISTANCE 0x10
226 #define MII_VCT7_PAIR_1_DISTANCE 0x11
227 #define MII_VCT7_PAIR_2_DISTANCE 0x12
228 #define MII_VCT7_PAIR_3_DISTANCE 0x13
230 #define MII_VCT7_RESULTS 0x14
231 #define MII_VCT7_RESULTS_PAIR3_MASK 0xf000
232 #define MII_VCT7_RESULTS_PAIR2_MASK 0x0f00
233 #define MII_VCT7_RESULTS_PAIR1_MASK 0x00f0
234 #define MII_VCT7_RESULTS_PAIR0_MASK 0x000f
235 #define MII_VCT7_RESULTS_PAIR3_SHIFT 12
236 #define MII_VCT7_RESULTS_PAIR2_SHIFT 8
237 #define MII_VCT7_RESULTS_PAIR1_SHIFT 4
238 #define MII_VCT7_RESULTS_PAIR0_SHIFT 0
239 #define MII_VCT7_RESULTS_INVALID 0
240 #define MII_VCT7_RESULTS_OK 1
241 #define MII_VCT7_RESULTS_OPEN 2
242 #define MII_VCT7_RESULTS_SAME_SHORT 3
243 #define MII_VCT7_RESULTS_CROSS_SHORT 4
244 #define MII_VCT7_RESULTS_BUSY 9
246 #define MII_VCT7_CTRL 0x15
247 #define MII_VCT7_CTRL_RUN_NOW BIT(15)
248 #define MII_VCT7_CTRL_RUN_ANEG BIT(14)
249 #define MII_VCT7_CTRL_DISABLE_CROSS BIT(13)
250 #define MII_VCT7_CTRL_RUN_AFTER_BREAK_LINK BIT(12)
251 #define MII_VCT7_CTRL_IN_PROGRESS BIT(11)
252 #define MII_VCT7_CTRL_METERS BIT(10)
253 #define MII_VCT7_CTRL_CENTIMETERS 0
255 #define LPA_PAUSE_FIBER 0x180
256 #define LPA_PAUSE_ASYM_FIBER 0x100
258 #define NB_FIBER_STATS 1
260 MODULE_DESCRIPTION("Marvell PHY driver");
261 MODULE_AUTHOR("Andy Fleming");
262 MODULE_LICENSE("GPL");
264 struct marvell_hw_stat {
271 static struct marvell_hw_stat marvell_hw_stats[] = {
272 { "phy_receive_errors_copper", 0, 21, 16},
273 { "phy_idle_errors", 0, 10, 8 },
274 { "phy_receive_errors_fiber", 1, 21, 16},
277 struct marvell_priv {
278 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
280 struct device *hwmon_dev;
288 static int marvell_read_page(struct phy_device *phydev)
290 return __phy_read(phydev, MII_MARVELL_PHY_PAGE);
293 static int marvell_write_page(struct phy_device *phydev, int page)
295 return __phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
298 static int marvell_set_page(struct phy_device *phydev, int page)
300 return phy_write(phydev, MII_MARVELL_PHY_PAGE, page);
303 static int marvell_ack_interrupt(struct phy_device *phydev)
307 /* Clear the interrupts by reading the reg */
308 err = phy_read(phydev, MII_M1011_IEVENT);
316 static int marvell_config_intr(struct phy_device *phydev)
320 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
321 err = marvell_ack_interrupt(phydev);
325 err = phy_write(phydev, MII_M1011_IMASK,
326 MII_M1011_IMASK_INIT);
328 err = phy_write(phydev, MII_M1011_IMASK,
329 MII_M1011_IMASK_CLEAR);
333 err = marvell_ack_interrupt(phydev);
339 static irqreturn_t marvell_handle_interrupt(struct phy_device *phydev)
343 irq_status = phy_read(phydev, MII_M1011_IEVENT);
344 if (irq_status < 0) {
349 if (!(irq_status & MII_M1011_IMASK_INIT))
352 phy_trigger_machine(phydev);
357 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
363 /* get the current settings */
364 reg = phy_read(phydev, MII_M1011_PHY_SCR);
369 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
372 val |= MII_M1011_PHY_SCR_MDI;
375 val |= MII_M1011_PHY_SCR_MDI_X;
377 case ETH_TP_MDI_AUTO:
378 case ETH_TP_MDI_INVALID:
380 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
385 /* Set the new polarity value in the register */
386 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
394 static int marvell_config_aneg(struct phy_device *phydev)
399 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
405 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
406 MII_M1111_PHY_LED_DIRECT);
410 err = genphy_config_aneg(phydev);
414 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
415 /* A write to speed/duplex bits (that is performed by
416 * genphy_config_aneg() call above) must be followed by
417 * a software reset. Otherwise, the write has no effect.
419 err = genphy_soft_reset(phydev);
427 static int m88e1101_config_aneg(struct phy_device *phydev)
431 /* This Marvell PHY has an errata which requires
432 * that certain registers get written in order
433 * to restart autonegotiation
435 err = genphy_soft_reset(phydev);
439 err = phy_write(phydev, 0x1d, 0x1f);
443 err = phy_write(phydev, 0x1e, 0x200c);
447 err = phy_write(phydev, 0x1d, 0x5);
451 err = phy_write(phydev, 0x1e, 0);
455 err = phy_write(phydev, 0x1e, 0x100);
459 return marvell_config_aneg(phydev);
462 #if IS_ENABLED(CONFIG_OF_MDIO)
463 /* Set and/or override some configuration registers based on the
464 * marvell,reg-init property stored in the of_node for the phydev.
466 * marvell,reg-init = <reg-page reg mask value>,...;
468 * There may be one or more sets of <reg-page reg mask value>:
470 * reg-page: which register bank to use.
472 * mask: if non-zero, ANDed with existing register value.
473 * value: ORed with the masked value and written to the regiser.
476 static int marvell_of_reg_init(struct phy_device *phydev)
479 int len, i, saved_page, current_page, ret = 0;
481 if (!phydev->mdio.dev.of_node)
484 paddr = of_get_property(phydev->mdio.dev.of_node,
485 "marvell,reg-init", &len);
486 if (!paddr || len < (4 * sizeof(*paddr)))
489 saved_page = phy_save_page(phydev);
492 current_page = saved_page;
494 len /= sizeof(*paddr);
495 for (i = 0; i < len - 3; i += 4) {
496 u16 page = be32_to_cpup(paddr + i);
497 u16 reg = be32_to_cpup(paddr + i + 1);
498 u16 mask = be32_to_cpup(paddr + i + 2);
499 u16 val_bits = be32_to_cpup(paddr + i + 3);
502 if (page != current_page) {
504 ret = marvell_write_page(phydev, page);
511 val = __phy_read(phydev, reg);
520 ret = __phy_write(phydev, reg, val);
525 return phy_restore_page(phydev, saved_page, ret);
528 static int marvell_of_reg_init(struct phy_device *phydev)
532 #endif /* CONFIG_OF_MDIO */
534 static int m88e1121_config_aneg_rgmii_delays(struct phy_device *phydev)
538 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
539 mscr = MII_88E1121_PHY_MSCR_RX_DELAY |
540 MII_88E1121_PHY_MSCR_TX_DELAY;
541 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
542 mscr = MII_88E1121_PHY_MSCR_RX_DELAY;
543 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
544 mscr = MII_88E1121_PHY_MSCR_TX_DELAY;
548 return phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
549 MII_88E1121_PHY_MSCR_REG,
550 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr);
553 static int m88e1121_config_aneg(struct phy_device *phydev)
558 if (phy_interface_is_rgmii(phydev)) {
559 err = m88e1121_config_aneg_rgmii_delays(phydev);
564 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
570 err = genphy_config_aneg(phydev);
574 if (phydev->autoneg != AUTONEG_ENABLE || changed) {
575 /* A software reset is used to ensure a "commit" of the
578 err = genphy_soft_reset(phydev);
586 static int m88e1318_config_aneg(struct phy_device *phydev)
590 err = phy_modify_paged(phydev, MII_MARVELL_MSCR_PAGE,
591 MII_88E1318S_PHY_MSCR1_REG,
592 0, MII_88E1318S_PHY_MSCR1_PAD_ODD);
596 return m88e1121_config_aneg(phydev);
600 * linkmode_adv_to_fiber_adv_t
601 * @advertise: the linkmode advertisement settings
603 * A small helper function that translates linkmode advertisement
604 * settings to phy autonegotiation advertisements for the MII_ADV
605 * register for fiber link.
607 static inline u32 linkmode_adv_to_fiber_adv_t(unsigned long *advertise)
611 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, advertise))
612 result |= ADVERTISE_1000XHALF;
613 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, advertise))
614 result |= ADVERTISE_1000XFULL;
616 if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertise) &&
617 linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
618 result |= ADVERTISE_1000XPSE_ASYM;
619 else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertise))
620 result |= ADVERTISE_1000XPAUSE;
626 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
627 * @phydev: target phy_device struct
629 * Description: If auto-negotiation is enabled, we configure the
630 * advertising, and then restart auto-negotiation. If it is not
631 * enabled, then we write the BMCR. Adapted for fiber link in
632 * some Marvell's devices.
634 static int marvell_config_aneg_fiber(struct phy_device *phydev)
640 if (phydev->autoneg != AUTONEG_ENABLE)
641 return genphy_setup_forced(phydev);
643 /* Only allow advertising what this PHY supports */
644 linkmode_and(phydev->advertising, phydev->advertising,
647 adv = linkmode_adv_to_fiber_adv_t(phydev->advertising);
649 /* Setup fiber advertisement */
650 err = phy_modify_changed(phydev, MII_ADVERTISE,
651 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL |
652 ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM,
659 return genphy_check_and_restart_aneg(phydev, changed);
662 static int m88e1111_config_aneg(struct phy_device *phydev)
664 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
670 /* If not using SGMII or copper 1000BaseX modes, use normal process.
671 * Steps below are only required for these modes.
673 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
674 (extsr & MII_M1111_HWCFG_MODE_MASK) !=
675 MII_M1111_HWCFG_MODE_COPPER_1000X_AN)
676 return marvell_config_aneg(phydev);
678 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
682 /* Configure the copper link first */
683 err = marvell_config_aneg(phydev);
687 /* Then the fiber link */
688 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
692 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
693 /* Do not touch the fiber advertisement if we're in copper->sgmii mode.
694 * Just ensure that SGMII-side autonegotiation is enabled.
695 * If we switched from some other mode to SGMII it may not be.
697 err = genphy_check_and_restart_aneg(phydev, false);
699 err = marvell_config_aneg_fiber(phydev);
703 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
706 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
710 static int m88e1510_config_aneg(struct phy_device *phydev)
714 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
718 /* Configure the copper link first */
719 err = m88e1318_config_aneg(phydev);
723 /* Do not touch the fiber page if we're in copper->sgmii mode */
724 if (phydev->interface == PHY_INTERFACE_MODE_SGMII)
727 /* Then the fiber link */
728 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
732 err = marvell_config_aneg_fiber(phydev);
736 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
739 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
743 static void marvell_config_led(struct phy_device *phydev)
748 switch (MARVELL_PHY_FAMILY_ID(phydev->phy_id)) {
749 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
750 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1121R):
751 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1318S):
752 def_config = MII_88E1121_PHY_LED_DEF;
754 /* Default PHY LED config:
755 * LED[0] .. 1000Mbps Link
756 * LED[1] .. 100Mbps Link
757 * LED[2] .. Blink, Activity
759 case MARVELL_PHY_FAMILY_ID(MARVELL_PHY_ID_88E1510):
760 if (phydev->dev_flags & MARVELL_PHY_LED0_LINK_LED1_ACTIVE)
761 def_config = MII_88E1510_PHY_LED0_LINK_LED1_ACTIVE;
763 def_config = MII_88E1510_PHY_LED_DEF;
769 err = phy_write_paged(phydev, MII_MARVELL_LED_PAGE, MII_PHY_LED_CTRL,
772 phydev_warn(phydev, "Fail to config marvell phy LED.\n");
775 static int marvell_config_init(struct phy_device *phydev)
777 /* Set default LED */
778 marvell_config_led(phydev);
780 /* Set registers from marvell,reg-init DT property */
781 return marvell_of_reg_init(phydev);
784 static int m88e3016_config_init(struct phy_device *phydev)
788 /* Enable Scrambler and Auto-Crossover */
789 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL,
790 MII_88E3016_DISABLE_SCRAMBLER,
791 MII_88E3016_AUTO_MDIX_CROSSOVER);
795 return marvell_config_init(phydev);
798 static int m88e1111_config_init_hwcfg_mode(struct phy_device *phydev,
800 int fibre_copper_auto)
802 if (fibre_copper_auto)
803 mode |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
805 return phy_modify(phydev, MII_M1111_PHY_EXT_SR,
806 MII_M1111_HWCFG_MODE_MASK |
807 MII_M1111_HWCFG_FIBER_COPPER_AUTO |
808 MII_M1111_HWCFG_FIBER_COPPER_RES,
812 static int m88e1111_config_init_rgmii_delays(struct phy_device *phydev)
816 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
817 delay = MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY;
818 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
819 delay = MII_M1111_RGMII_RX_DELAY;
820 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
821 delay = MII_M1111_RGMII_TX_DELAY;
826 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
827 MII_M1111_RGMII_RX_DELAY | MII_M1111_RGMII_TX_DELAY,
831 static int m88e1111_config_init_rgmii(struct phy_device *phydev)
836 err = m88e1111_config_init_rgmii_delays(phydev);
840 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
844 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
846 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
847 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
849 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
851 return phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
854 static int m88e1111_config_init_sgmii(struct phy_device *phydev)
858 err = m88e1111_config_init_hwcfg_mode(
860 MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
861 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
865 /* make sure copper is selected */
866 return marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
869 static int m88e1111_config_init_rtbi(struct phy_device *phydev)
873 err = m88e1111_config_init_rgmii_delays(phydev);
877 err = m88e1111_config_init_hwcfg_mode(
879 MII_M1111_HWCFG_MODE_RTBI,
880 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
885 err = genphy_soft_reset(phydev);
889 return m88e1111_config_init_hwcfg_mode(
891 MII_M1111_HWCFG_MODE_RTBI,
892 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
895 static int m88e1111_config_init_1000basex(struct phy_device *phydev)
897 int extsr = phy_read(phydev, MII_M1111_PHY_EXT_SR);
903 /* If using copper mode, ensure 1000BaseX auto-negotiation is enabled */
904 mode = extsr & MII_M1111_HWCFG_MODE_MASK;
905 if (mode == MII_M1111_HWCFG_MODE_COPPER_1000X_NOAN) {
906 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR,
907 MII_M1111_HWCFG_MODE_MASK |
908 MII_M1111_HWCFG_SERIAL_AN_BYPASS,
909 MII_M1111_HWCFG_MODE_COPPER_1000X_AN |
910 MII_M1111_HWCFG_SERIAL_AN_BYPASS);
917 static int m88e1111_config_init(struct phy_device *phydev)
921 if (phy_interface_is_rgmii(phydev)) {
922 err = m88e1111_config_init_rgmii(phydev);
927 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
928 err = m88e1111_config_init_sgmii(phydev);
933 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
934 err = m88e1111_config_init_rtbi(phydev);
939 if (phydev->interface == PHY_INTERFACE_MODE_1000BASEX) {
940 err = m88e1111_config_init_1000basex(phydev);
945 err = marvell_of_reg_init(phydev);
949 return genphy_soft_reset(phydev);
952 static int m88e1111_get_downshift(struct phy_device *phydev, u8 *data)
954 int val, cnt, enable;
956 val = phy_read(phydev, MII_M1111_PHY_EXT_CR);
960 enable = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN, val);
961 cnt = FIELD_GET(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, val) + 1;
963 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
968 static int m88e1111_set_downshift(struct phy_device *phydev, u8 cnt)
972 if (cnt > MII_M1111_PHY_EXT_CR_DOWNSHIFT_MAX)
976 return phy_clear_bits(phydev, MII_M1111_PHY_EXT_CR,
977 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN);
979 val = MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN;
980 val |= FIELD_PREP(MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK, cnt - 1);
982 return phy_modify(phydev, MII_M1111_PHY_EXT_CR,
983 MII_M1111_PHY_EXT_CR_DOWNSHIFT_EN |
984 MII_M1111_PHY_EXT_CR_DOWNSHIFT_MASK,
988 static int m88e1111_get_tunable(struct phy_device *phydev,
989 struct ethtool_tunable *tuna, void *data)
992 case ETHTOOL_PHY_DOWNSHIFT:
993 return m88e1111_get_downshift(phydev, data);
999 static int m88e1111_set_tunable(struct phy_device *phydev,
1000 struct ethtool_tunable *tuna, const void *data)
1003 case ETHTOOL_PHY_DOWNSHIFT:
1004 return m88e1111_set_downshift(phydev, *(const u8 *)data);
1010 static int m88e1011_get_downshift(struct phy_device *phydev, u8 *data)
1012 int val, cnt, enable;
1014 val = phy_read(phydev, MII_M1011_PHY_SCR);
1018 enable = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_EN, val);
1019 cnt = FIELD_GET(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, val) + 1;
1021 *data = enable ? cnt : DOWNSHIFT_DEV_DISABLE;
1026 static int m88e1011_set_downshift(struct phy_device *phydev, u8 cnt)
1030 if (cnt > MII_M1011_PHY_SCR_DOWNSHIFT_MAX)
1034 return phy_clear_bits(phydev, MII_M1011_PHY_SCR,
1035 MII_M1011_PHY_SCR_DOWNSHIFT_EN);
1037 val = MII_M1011_PHY_SCR_DOWNSHIFT_EN;
1038 val |= FIELD_PREP(MII_M1011_PHY_SCR_DOWNSHIFT_MASK, cnt - 1);
1040 return phy_modify(phydev, MII_M1011_PHY_SCR,
1041 MII_M1011_PHY_SCR_DOWNSHIFT_EN |
1042 MII_M1011_PHY_SCR_DOWNSHIFT_MASK,
1046 static int m88e1011_get_tunable(struct phy_device *phydev,
1047 struct ethtool_tunable *tuna, void *data)
1050 case ETHTOOL_PHY_DOWNSHIFT:
1051 return m88e1011_get_downshift(phydev, data);
1057 static int m88e1011_set_tunable(struct phy_device *phydev,
1058 struct ethtool_tunable *tuna, const void *data)
1061 case ETHTOOL_PHY_DOWNSHIFT:
1062 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1068 static int m88e1116r_config_init(struct phy_device *phydev)
1072 err = genphy_soft_reset(phydev);
1078 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1082 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1086 err = m88e1011_set_downshift(phydev, 8);
1090 if (phy_interface_is_rgmii(phydev)) {
1091 err = m88e1121_config_aneg_rgmii_delays(phydev);
1096 err = genphy_soft_reset(phydev);
1100 return marvell_config_init(phydev);
1103 static int m88e1318_config_init(struct phy_device *phydev)
1105 if (phy_interrupt_is_valid(phydev)) {
1106 int err = phy_modify_paged(
1107 phydev, MII_MARVELL_LED_PAGE,
1108 MII_88E1318S_PHY_LED_TCR,
1109 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1110 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1111 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1116 return marvell_config_init(phydev);
1119 static int m88e1510_config_init(struct phy_device *phydev)
1123 /* SGMII-to-Copper mode initialization */
1124 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1125 /* Select page 18 */
1126 err = marvell_set_page(phydev, 18);
1130 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
1131 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1,
1132 MII_88E1510_GEN_CTRL_REG_1_MODE_MASK,
1133 MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII);
1137 /* PHY reset is necessary after changing MODE[2:0] */
1138 err = phy_set_bits(phydev, MII_88E1510_GEN_CTRL_REG_1,
1139 MII_88E1510_GEN_CTRL_REG_1_RESET);
1143 /* Reset page selection */
1144 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1149 return m88e1318_config_init(phydev);
1152 static int m88e1118_config_aneg(struct phy_device *phydev)
1156 err = genphy_soft_reset(phydev);
1160 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
1164 err = genphy_config_aneg(phydev);
1168 static int m88e1118_config_init(struct phy_device *phydev)
1172 /* Change address */
1173 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1177 /* Enable 1000 Mbit */
1178 err = phy_write(phydev, 0x15, 0x1070);
1182 /* Change address */
1183 err = marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
1187 /* Adjust LED Control */
1188 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
1189 err = phy_write(phydev, 0x10, 0x1100);
1191 err = phy_write(phydev, 0x10, 0x021e);
1195 err = marvell_of_reg_init(phydev);
1200 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1204 return genphy_soft_reset(phydev);
1207 static int m88e1149_config_init(struct phy_device *phydev)
1211 /* Change address */
1212 err = marvell_set_page(phydev, MII_MARVELL_MSCR_PAGE);
1216 /* Enable 1000 Mbit */
1217 err = phy_write(phydev, 0x15, 0x1048);
1221 err = marvell_of_reg_init(phydev);
1226 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1230 return genphy_soft_reset(phydev);
1233 static int m88e1145_config_init_rgmii(struct phy_device *phydev)
1237 err = m88e1111_config_init_rgmii_delays(phydev);
1241 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
1242 err = phy_write(phydev, 0x1d, 0x0012);
1246 err = phy_modify(phydev, 0x1e, 0x0fc0,
1247 2 << 9 | /* 36 ohm */
1248 2 << 6); /* 39 ohm */
1252 err = phy_write(phydev, 0x1d, 0x3);
1256 err = phy_write(phydev, 0x1e, 0x8000);
1261 static int m88e1145_config_init_sgmii(struct phy_device *phydev)
1263 return m88e1111_config_init_hwcfg_mode(
1264 phydev, MII_M1111_HWCFG_MODE_SGMII_NO_CLK,
1265 MII_M1111_HWCFG_FIBER_COPPER_AUTO);
1268 static int m88e1145_config_init(struct phy_device *phydev)
1272 /* Take care of errata E0 & E1 */
1273 err = phy_write(phydev, 0x1d, 0x001b);
1277 err = phy_write(phydev, 0x1e, 0x418f);
1281 err = phy_write(phydev, 0x1d, 0x0016);
1285 err = phy_write(phydev, 0x1e, 0xa2da);
1289 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
1290 err = m88e1145_config_init_rgmii(phydev);
1295 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
1296 err = m88e1145_config_init_sgmii(phydev);
1301 err = marvell_of_reg_init(phydev);
1308 static int m88e1540_get_fld(struct phy_device *phydev, u8 *msecs)
1312 val = phy_read(phydev, MII_88E1540_COPPER_CTRL3);
1316 if (!(val & MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN)) {
1317 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
1321 val = FIELD_GET(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1324 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS:
1327 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS:
1330 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS:
1333 case MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS:
1343 static int m88e1540_set_fld(struct phy_device *phydev, const u8 *msecs)
1345 struct ethtool_eee eee;
1348 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
1349 return phy_clear_bits(phydev, MII_88E1540_COPPER_CTRL3,
1350 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1352 /* According to the Marvell data sheet EEE must be disabled for
1353 * Fast Link Down detection to work properly
1355 ret = phy_ethtool_get_eee(phydev, &eee);
1356 if (!ret && eee.eee_enabled) {
1357 phydev_warn(phydev, "Fast Link Down detection requires EEE to be disabled!\n");
1362 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_00MS;
1363 else if (*msecs <= 15)
1364 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_10MS;
1365 else if (*msecs <= 30)
1366 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_20MS;
1368 val = MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_40MS;
1370 val = FIELD_PREP(MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1372 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3,
1373 MII_88E1540_COPPER_CTRL3_LINK_DOWN_DELAY_MASK, val);
1377 return phy_set_bits(phydev, MII_88E1540_COPPER_CTRL3,
1378 MII_88E1540_COPPER_CTRL3_FAST_LINK_DOWN);
1381 static int m88e1540_get_tunable(struct phy_device *phydev,
1382 struct ethtool_tunable *tuna, void *data)
1385 case ETHTOOL_PHY_FAST_LINK_DOWN:
1386 return m88e1540_get_fld(phydev, data);
1387 case ETHTOOL_PHY_DOWNSHIFT:
1388 return m88e1011_get_downshift(phydev, data);
1394 static int m88e1540_set_tunable(struct phy_device *phydev,
1395 struct ethtool_tunable *tuna, const void *data)
1398 case ETHTOOL_PHY_FAST_LINK_DOWN:
1399 return m88e1540_set_fld(phydev, data);
1400 case ETHTOOL_PHY_DOWNSHIFT:
1401 return m88e1011_set_downshift(phydev, *(const u8 *)data);
1407 /* The VOD can be out of specification on link up. Poke an
1408 * undocumented register, in an undocumented page, with a magic value
1411 static int m88e6390_errata(struct phy_device *phydev)
1415 err = phy_write(phydev, MII_BMCR,
1416 BMCR_ANENABLE | BMCR_SPEED1000 | BMCR_FULLDPLX);
1420 usleep_range(300, 400);
1422 err = phy_write_paged(phydev, 0xf8, 0x08, 0x36);
1426 return genphy_soft_reset(phydev);
1429 static int m88e6390_config_aneg(struct phy_device *phydev)
1433 err = m88e6390_errata(phydev);
1437 return m88e1510_config_aneg(phydev);
1441 * fiber_lpa_mod_linkmode_lpa_t
1442 * @advertising: the linkmode advertisement settings
1443 * @lpa: value of the MII_LPA register for fiber link
1445 * A small helper function that translates MII_LPA bits to linkmode LP
1446 * advertisement settings. Other bits in advertising are left
1449 static void fiber_lpa_mod_linkmode_lpa_t(unsigned long *advertising, u32 lpa)
1451 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1452 advertising, lpa & LPA_1000XHALF);
1454 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1455 advertising, lpa & LPA_1000XFULL);
1458 static int marvell_read_status_page_an(struct phy_device *phydev,
1459 int fiber, int status)
1464 if (!(status & MII_M1011_PHY_STATUS_RESOLVED)) {
1469 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1470 phydev->duplex = DUPLEX_FULL;
1472 phydev->duplex = DUPLEX_HALF;
1474 switch (status & MII_M1011_PHY_STATUS_SPD_MASK) {
1475 case MII_M1011_PHY_STATUS_1000:
1476 phydev->speed = SPEED_1000;
1479 case MII_M1011_PHY_STATUS_100:
1480 phydev->speed = SPEED_100;
1484 phydev->speed = SPEED_10;
1489 err = genphy_read_lpa(phydev);
1493 phy_resolve_aneg_pause(phydev);
1495 lpa = phy_read(phydev, MII_LPA);
1499 /* The fiber link is only 1000M capable */
1500 fiber_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa);
1502 if (phydev->duplex == DUPLEX_FULL) {
1503 if (!(lpa & LPA_PAUSE_FIBER)) {
1505 phydev->asym_pause = 0;
1506 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1508 phydev->asym_pause = 1;
1511 phydev->asym_pause = 0;
1519 /* marvell_read_status_page
1522 * Check the link, then figure out the current state
1523 * by comparing what we advertise with what the link partner
1524 * advertises. Start by checking the gigabit possibilities,
1525 * then move on to 10/100.
1527 static int marvell_read_status_page(struct phy_device *phydev, int page)
1533 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1537 /* Use the generic register for copper link status,
1538 * and the PHY status register for fiber link status.
1540 if (page == MII_MARVELL_FIBER_PAGE) {
1541 phydev->link = !!(status & MII_M1011_PHY_STATUS_LINK);
1543 err = genphy_update_link(phydev);
1548 if (page == MII_MARVELL_FIBER_PAGE)
1553 linkmode_zero(phydev->lp_advertising);
1555 phydev->asym_pause = 0;
1556 phydev->speed = SPEED_UNKNOWN;
1557 phydev->duplex = DUPLEX_UNKNOWN;
1558 phydev->port = fiber ? PORT_FIBRE : PORT_TP;
1560 if (phydev->autoneg == AUTONEG_ENABLE)
1561 err = marvell_read_status_page_an(phydev, fiber, status);
1563 err = genphy_read_status_fixed(phydev);
1568 /* marvell_read_status
1570 * Some Marvell's phys have two modes: fiber and copper.
1571 * Both need status checked.
1573 * First, check the fiber link and status.
1574 * If the fiber link is down, check the copper link and status which
1575 * will be the default value if both link are down.
1577 static int marvell_read_status(struct phy_device *phydev)
1581 /* Check the fiber mode first */
1582 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1583 phydev->supported) &&
1584 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1585 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1589 err = marvell_read_status_page(phydev, MII_MARVELL_FIBER_PAGE);
1593 /* If the fiber link is up, it is the selected and
1594 * used link. In this case, we need to stay in the
1595 * fiber page. Please to be careful about that, avoid
1596 * to restore Copper page in other functions which
1597 * could break the behaviour for some fiber phy like
1603 /* If fiber link is down, check and save copper mode state */
1604 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1609 return marvell_read_status_page(phydev, MII_MARVELL_COPPER_PAGE);
1612 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1618 * Some Marvell's phys have two modes: fiber and copper.
1619 * Both need to be suspended
1621 static int marvell_suspend(struct phy_device *phydev)
1625 /* Suspend the fiber mode first */
1626 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1627 phydev->supported)) {
1628 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1632 /* With the page set, use the generic suspend */
1633 err = genphy_suspend(phydev);
1637 /* Then, the copper link */
1638 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1643 /* With the page set, use the generic suspend */
1644 return genphy_suspend(phydev);
1647 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1653 * Some Marvell's phys have two modes: fiber and copper.
1654 * Both need to be resumed
1656 static int marvell_resume(struct phy_device *phydev)
1660 /* Resume the fiber mode first */
1661 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1662 phydev->supported)) {
1663 err = marvell_set_page(phydev, MII_MARVELL_FIBER_PAGE);
1667 /* With the page set, use the generic resume */
1668 err = genphy_resume(phydev);
1672 /* Then, the copper link */
1673 err = marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1678 /* With the page set, use the generic resume */
1679 return genphy_resume(phydev);
1682 marvell_set_page(phydev, MII_MARVELL_COPPER_PAGE);
1686 static int marvell_aneg_done(struct phy_device *phydev)
1688 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1690 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1693 static void m88e1318_get_wol(struct phy_device *phydev,
1694 struct ethtool_wolinfo *wol)
1698 wol->supported = WAKE_MAGIC;
1701 ret = phy_read_paged(phydev, MII_MARVELL_WOL_PAGE,
1702 MII_88E1318S_PHY_WOL_CTRL);
1703 if (ret >= 0 && ret & MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1704 wol->wolopts |= WAKE_MAGIC;
1707 static int m88e1318_set_wol(struct phy_device *phydev,
1708 struct ethtool_wolinfo *wol)
1710 int err = 0, oldpage;
1712 oldpage = phy_save_page(phydev);
1716 if (wol->wolopts & WAKE_MAGIC) {
1717 /* Explicitly switch to page 0x00, just to be sure */
1718 err = marvell_write_page(phydev, MII_MARVELL_COPPER_PAGE);
1722 /* If WOL event happened once, the LED[2] interrupt pin
1723 * will not be cleared unless we reading the interrupt status
1724 * register. If interrupts are in use, the normal interrupt
1725 * handling will clear the WOL event. Clear the WOL event
1726 * before enabling it if !phy_interrupt_is_valid()
1728 if (!phy_interrupt_is_valid(phydev))
1729 __phy_read(phydev, MII_M1011_IEVENT);
1731 /* Enable the WOL interrupt */
1732 err = __phy_set_bits(phydev, MII_88E1318S_PHY_CSIER,
1733 MII_88E1318S_PHY_CSIER_WOL_EIE);
1737 err = marvell_write_page(phydev, MII_MARVELL_LED_PAGE);
1741 /* Setup LED[2] as interrupt pin (active low) */
1742 err = __phy_modify(phydev, MII_88E1318S_PHY_LED_TCR,
1743 MII_88E1318S_PHY_LED_TCR_FORCE_INT,
1744 MII_88E1318S_PHY_LED_TCR_INTn_ENABLE |
1745 MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW);
1749 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1753 /* Store the device address for the magic packet */
1754 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1755 ((phydev->attached_dev->dev_addr[5] << 8) |
1756 phydev->attached_dev->dev_addr[4]));
1759 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1760 ((phydev->attached_dev->dev_addr[3] << 8) |
1761 phydev->attached_dev->dev_addr[2]));
1764 err = __phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1765 ((phydev->attached_dev->dev_addr[1] << 8) |
1766 phydev->attached_dev->dev_addr[0]));
1770 /* Clear WOL status and enable magic packet matching */
1771 err = __phy_set_bits(phydev, MII_88E1318S_PHY_WOL_CTRL,
1772 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS |
1773 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE);
1777 err = marvell_write_page(phydev, MII_MARVELL_WOL_PAGE);
1781 /* Clear WOL status and disable magic packet matching */
1782 err = __phy_modify(phydev, MII_88E1318S_PHY_WOL_CTRL,
1783 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE,
1784 MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS);
1790 return phy_restore_page(phydev, oldpage, err);
1793 static int marvell_get_sset_count(struct phy_device *phydev)
1795 if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
1797 return ARRAY_SIZE(marvell_hw_stats);
1799 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1802 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1804 int count = marvell_get_sset_count(phydev);
1807 for (i = 0; i < count; i++) {
1808 strlcpy(data + i * ETH_GSTRING_LEN,
1809 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1813 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1815 struct marvell_hw_stat stat = marvell_hw_stats[i];
1816 struct marvell_priv *priv = phydev->priv;
1820 val = phy_read_paged(phydev, stat.page, stat.reg);
1824 val = val & ((1 << stat.bits) - 1);
1825 priv->stats[i] += val;
1826 ret = priv->stats[i];
1832 static void marvell_get_stats(struct phy_device *phydev,
1833 struct ethtool_stats *stats, u64 *data)
1835 int count = marvell_get_sset_count(phydev);
1838 for (i = 0; i < count; i++)
1839 data[i] = marvell_get_stat(phydev, i);
1842 static int marvell_vct5_wait_complete(struct phy_device *phydev)
1847 for (i = 0; i < 32; i++) {
1848 val = __phy_read(phydev, MII_VCT5_CTRL);
1852 if (val & MII_VCT5_CTRL_COMPLETE)
1856 phydev_err(phydev, "Timeout while waiting for cable test to finish\n");
1860 static int marvell_vct5_amplitude(struct phy_device *phydev, int pair)
1866 reg = MII_VCT5_TX_RX_MDI0_COUPLING + pair;
1867 val = __phy_read(phydev, reg);
1872 amplitude = (val & MII_VCT5_TX_RX_AMPLITUDE_MASK) >>
1873 MII_VCT5_TX_RX_AMPLITUDE_SHIFT;
1875 if (!(val & MII_VCT5_TX_RX_COUPLING_POSITIVE_REFLECTION))
1876 amplitude = -amplitude;
1878 return 1000 * amplitude / 128;
1881 static u32 marvell_vct5_distance2cm(int distance)
1883 return distance * 805 / 10;
1886 static u32 marvell_vct5_cm2distance(int cm)
1888 return cm * 10 / 805;
1891 static int marvell_vct5_amplitude_distance(struct phy_device *phydev,
1892 int distance, int pair)
1899 err = __phy_write(phydev, MII_VCT5_SAMPLE_POINT_DISTANCE,
1904 reg = MII_VCT5_CTRL_ENABLE |
1905 MII_VCT5_CTRL_TX_SAME_CHANNEL |
1906 MII_VCT5_CTRL_SAMPLES_DEFAULT |
1907 MII_VCT5_CTRL_SAMPLE_POINT |
1908 MII_VCT5_CTRL_PEEK_HYST_DEFAULT;
1909 err = __phy_write(phydev, MII_VCT5_CTRL, reg);
1913 err = marvell_vct5_wait_complete(phydev);
1917 for (i = 0; i < 4; i++) {
1918 if (pair != PHY_PAIR_ALL && i != pair)
1921 mV = marvell_vct5_amplitude(phydev, i);
1922 ethnl_cable_test_amplitude(phydev, i, mV);
1928 static int marvell_vct5_amplitude_graph(struct phy_device *phydev)
1930 struct marvell_priv *priv = phydev->priv;
1937 if (priv->first <= TDR_SHORT_CABLE_LENGTH)
1938 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS;
1940 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1942 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1943 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1944 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1946 err = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
1947 MII_VCT5_TX_PULSE_CTRL, reg);
1951 /* Reading the TDR data is very MDIO heavy. We need to optimize
1952 * access to keep the time to a minimum. So lock the bus once,
1953 * and don't release it until complete. We can then avoid having
1954 * to change the page for every access, greatly speeding things
1957 page = phy_select_page(phydev, MII_MARVELL_VCT5_PAGE);
1961 for (distance = priv->first;
1962 distance <= priv->last;
1963 distance += priv->step) {
1964 err = marvell_vct5_amplitude_distance(phydev, distance,
1969 if (distance > TDR_SHORT_CABLE_LENGTH &&
1970 width == MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_32nS) {
1971 width = MII_VCT5_TX_PULSE_CTRL_PULSE_WIDTH_128nS;
1972 reg = MII_VCT5_TX_PULSE_CTRL_GT_140m_46_86mV |
1973 MII_VCT5_TX_PULSE_CTRL_DONT_WAIT_LINK_DOWN |
1974 MII_VCT5_TX_PULSE_CTRL_MAX_AMP | width;
1975 err = __phy_write(phydev, MII_VCT5_TX_PULSE_CTRL, reg);
1982 return phy_restore_page(phydev, page, err);
1985 static int marvell_cable_test_start_common(struct phy_device *phydev)
1987 int bmcr, bmsr, ret;
1989 /* If auto-negotiation is enabled, but not complete, the cable
1990 * test never completes. So disable auto-neg.
1992 bmcr = phy_read(phydev, MII_BMCR);
1996 bmsr = phy_read(phydev, MII_BMSR);
2001 if (bmcr & BMCR_ANENABLE) {
2002 ret = phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE);
2005 ret = genphy_soft_reset(phydev);
2010 /* If the link is up, allow it some time to go down */
2011 if (bmsr & BMSR_LSTATUS)
2017 static int marvell_vct7_cable_test_start(struct phy_device *phydev)
2019 struct marvell_priv *priv = phydev->priv;
2022 ret = marvell_cable_test_start_common(phydev);
2026 priv->cable_test_tdr = false;
2028 /* Reset the VCT5 API control to defaults, otherwise
2029 * VCT7 does not work correctly.
2031 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2033 MII_VCT5_CTRL_TX_SAME_CHANNEL |
2034 MII_VCT5_CTRL_SAMPLES_DEFAULT |
2035 MII_VCT5_CTRL_MODE_MAXIMUM_PEEK |
2036 MII_VCT5_CTRL_PEEK_HYST_DEFAULT);
2040 ret = phy_write_paged(phydev, MII_MARVELL_VCT5_PAGE,
2041 MII_VCT5_SAMPLE_POINT_DISTANCE, 0);
2045 return phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2047 MII_VCT7_CTRL_RUN_NOW |
2048 MII_VCT7_CTRL_CENTIMETERS);
2051 static int marvell_vct5_cable_test_tdr_start(struct phy_device *phydev,
2052 const struct phy_tdr_config *cfg)
2054 struct marvell_priv *priv = phydev->priv;
2057 priv->cable_test_tdr = true;
2058 priv->first = marvell_vct5_cm2distance(cfg->first);
2059 priv->last = marvell_vct5_cm2distance(cfg->last);
2060 priv->step = marvell_vct5_cm2distance(cfg->step);
2061 priv->pair = cfg->pair;
2063 if (priv->first > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2066 if (priv->last > MII_VCT5_SAMPLE_POINT_DISTANCE_MAX)
2070 ret = phy_write_paged(phydev, MII_MARVELL_VCT7_PAGE,
2075 ret = marvell_cable_test_start_common(phydev);
2079 ret = ethnl_cable_test_pulse(phydev, 1000);
2083 return ethnl_cable_test_step(phydev,
2084 marvell_vct5_distance2cm(priv->first),
2085 marvell_vct5_distance2cm(priv->last),
2086 marvell_vct5_distance2cm(priv->step));
2089 static int marvell_vct7_distance_to_length(int distance, bool meter)
2097 static bool marvell_vct7_distance_valid(int result)
2100 case MII_VCT7_RESULTS_OPEN:
2101 case MII_VCT7_RESULTS_SAME_SHORT:
2102 case MII_VCT7_RESULTS_CROSS_SHORT:
2108 static int marvell_vct7_report_length(struct phy_device *phydev,
2109 int pair, bool meter)
2114 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2115 MII_VCT7_PAIR_0_DISTANCE + pair);
2119 length = marvell_vct7_distance_to_length(ret, meter);
2121 ethnl_cable_test_fault_length(phydev, pair, length);
2126 static int marvell_vct7_cable_test_report_trans(int result)
2129 case MII_VCT7_RESULTS_OK:
2130 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2131 case MII_VCT7_RESULTS_OPEN:
2132 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2133 case MII_VCT7_RESULTS_SAME_SHORT:
2134 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2135 case MII_VCT7_RESULTS_CROSS_SHORT:
2136 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2138 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2142 static int marvell_vct7_cable_test_report(struct phy_device *phydev)
2144 int pair0, pair1, pair2, pair3;
2148 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2153 pair3 = (ret & MII_VCT7_RESULTS_PAIR3_MASK) >>
2154 MII_VCT7_RESULTS_PAIR3_SHIFT;
2155 pair2 = (ret & MII_VCT7_RESULTS_PAIR2_MASK) >>
2156 MII_VCT7_RESULTS_PAIR2_SHIFT;
2157 pair1 = (ret & MII_VCT7_RESULTS_PAIR1_MASK) >>
2158 MII_VCT7_RESULTS_PAIR1_SHIFT;
2159 pair0 = (ret & MII_VCT7_RESULTS_PAIR0_MASK) >>
2160 MII_VCT7_RESULTS_PAIR0_SHIFT;
2162 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
2163 marvell_vct7_cable_test_report_trans(pair0));
2164 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_B,
2165 marvell_vct7_cable_test_report_trans(pair1));
2166 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_C,
2167 marvell_vct7_cable_test_report_trans(pair2));
2168 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_D,
2169 marvell_vct7_cable_test_report_trans(pair3));
2171 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE, MII_VCT7_CTRL);
2175 meter = ret & MII_VCT7_CTRL_METERS;
2177 if (marvell_vct7_distance_valid(pair0))
2178 marvell_vct7_report_length(phydev, 0, meter);
2179 if (marvell_vct7_distance_valid(pair1))
2180 marvell_vct7_report_length(phydev, 1, meter);
2181 if (marvell_vct7_distance_valid(pair2))
2182 marvell_vct7_report_length(phydev, 2, meter);
2183 if (marvell_vct7_distance_valid(pair3))
2184 marvell_vct7_report_length(phydev, 3, meter);
2189 static int marvell_vct7_cable_test_get_status(struct phy_device *phydev,
2192 struct marvell_priv *priv = phydev->priv;
2195 if (priv->cable_test_tdr) {
2196 ret = marvell_vct5_amplitude_graph(phydev);
2203 ret = phy_read_paged(phydev, MII_MARVELL_VCT7_PAGE,
2209 if (!(ret & MII_VCT7_CTRL_IN_PROGRESS)) {
2212 return marvell_vct7_cable_test_report(phydev);
2219 static int m88e1121_get_temp(struct phy_device *phydev, long *temp)
2227 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2231 /* Enable temperature sensor */
2232 ret = __phy_read(phydev, MII_88E1121_MISC_TEST);
2236 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2237 ret | MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2241 /* Wait for temperature to stabilize */
2242 usleep_range(10000, 12000);
2244 val = __phy_read(phydev, MII_88E1121_MISC_TEST);
2250 /* Disable temperature sensor */
2251 ret = __phy_write(phydev, MII_88E1121_MISC_TEST,
2252 ret & ~MII_88E1121_MISC_TEST_TEMP_SENSOR_EN);
2256 *temp = ((val & MII_88E1121_MISC_TEST_TEMP_MASK) - 5) * 5000;
2259 return phy_restore_page(phydev, oldpage, ret);
2262 static int m88e1121_hwmon_read(struct device *dev,
2263 enum hwmon_sensor_types type,
2264 u32 attr, int channel, long *temp)
2266 struct phy_device *phydev = dev_get_drvdata(dev);
2270 case hwmon_temp_input:
2271 err = m88e1121_get_temp(phydev, temp);
2280 static umode_t m88e1121_hwmon_is_visible(const void *data,
2281 enum hwmon_sensor_types type,
2282 u32 attr, int channel)
2284 if (type != hwmon_temp)
2288 case hwmon_temp_input:
2295 static u32 m88e1121_hwmon_chip_config[] = {
2296 HWMON_C_REGISTER_TZ,
2300 static const struct hwmon_channel_info m88e1121_hwmon_chip = {
2302 .config = m88e1121_hwmon_chip_config,
2305 static u32 m88e1121_hwmon_temp_config[] = {
2310 static const struct hwmon_channel_info m88e1121_hwmon_temp = {
2312 .config = m88e1121_hwmon_temp_config,
2315 static const struct hwmon_channel_info *m88e1121_hwmon_info[] = {
2316 &m88e1121_hwmon_chip,
2317 &m88e1121_hwmon_temp,
2321 static const struct hwmon_ops m88e1121_hwmon_hwmon_ops = {
2322 .is_visible = m88e1121_hwmon_is_visible,
2323 .read = m88e1121_hwmon_read,
2326 static const struct hwmon_chip_info m88e1121_hwmon_chip_info = {
2327 .ops = &m88e1121_hwmon_hwmon_ops,
2328 .info = m88e1121_hwmon_info,
2331 static int m88e1510_get_temp(struct phy_device *phydev, long *temp)
2337 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2338 MII_88E1510_TEMP_SENSOR);
2342 *temp = ((ret & MII_88E1510_TEMP_SENSOR_MASK) - 25) * 1000;
2347 static int m88e1510_get_temp_critical(struct phy_device *phydev, long *temp)
2353 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2354 MII_88E1121_MISC_TEST);
2358 *temp = (((ret & MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK) >>
2359 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT) * 5) - 25;
2366 static int m88e1510_set_temp_critical(struct phy_device *phydev, long temp)
2369 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2371 return phy_modify_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2372 MII_88E1121_MISC_TEST,
2373 MII_88E1510_MISC_TEST_TEMP_THRESHOLD_MASK,
2374 temp << MII_88E1510_MISC_TEST_TEMP_THRESHOLD_SHIFT);
2377 static int m88e1510_get_temp_alarm(struct phy_device *phydev, long *alarm)
2383 ret = phy_read_paged(phydev, MII_MARVELL_MISC_TEST_PAGE,
2384 MII_88E1121_MISC_TEST);
2388 *alarm = !!(ret & MII_88E1510_MISC_TEST_TEMP_IRQ);
2393 static int m88e1510_hwmon_read(struct device *dev,
2394 enum hwmon_sensor_types type,
2395 u32 attr, int channel, long *temp)
2397 struct phy_device *phydev = dev_get_drvdata(dev);
2401 case hwmon_temp_input:
2402 err = m88e1510_get_temp(phydev, temp);
2404 case hwmon_temp_crit:
2405 err = m88e1510_get_temp_critical(phydev, temp);
2407 case hwmon_temp_max_alarm:
2408 err = m88e1510_get_temp_alarm(phydev, temp);
2417 static int m88e1510_hwmon_write(struct device *dev,
2418 enum hwmon_sensor_types type,
2419 u32 attr, int channel, long temp)
2421 struct phy_device *phydev = dev_get_drvdata(dev);
2425 case hwmon_temp_crit:
2426 err = m88e1510_set_temp_critical(phydev, temp);
2434 static umode_t m88e1510_hwmon_is_visible(const void *data,
2435 enum hwmon_sensor_types type,
2436 u32 attr, int channel)
2438 if (type != hwmon_temp)
2442 case hwmon_temp_input:
2443 case hwmon_temp_max_alarm:
2445 case hwmon_temp_crit:
2452 static u32 m88e1510_hwmon_temp_config[] = {
2453 HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_MAX_ALARM,
2457 static const struct hwmon_channel_info m88e1510_hwmon_temp = {
2459 .config = m88e1510_hwmon_temp_config,
2462 static const struct hwmon_channel_info *m88e1510_hwmon_info[] = {
2463 &m88e1121_hwmon_chip,
2464 &m88e1510_hwmon_temp,
2468 static const struct hwmon_ops m88e1510_hwmon_hwmon_ops = {
2469 .is_visible = m88e1510_hwmon_is_visible,
2470 .read = m88e1510_hwmon_read,
2471 .write = m88e1510_hwmon_write,
2474 static const struct hwmon_chip_info m88e1510_hwmon_chip_info = {
2475 .ops = &m88e1510_hwmon_hwmon_ops,
2476 .info = m88e1510_hwmon_info,
2479 static int m88e6390_get_temp(struct phy_device *phydev, long *temp)
2488 oldpage = phy_select_page(phydev, MII_MARVELL_MISC_TEST_PAGE);
2492 /* Enable temperature sensor */
2493 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2497 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2498 ret |= MII_88E6390_MISC_TEST_SAMPLE_ENABLE |
2499 MII_88E6390_MISC_TEST_SAMPLE_1S;
2501 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2505 /* Wait for temperature to stabilize */
2506 usleep_range(10000, 12000);
2508 /* Reading the temperature sense has an errata. You need to read
2509 * a number of times and take an average.
2511 for (i = 0; i < MII_88E6390_TEMP_SENSOR_SAMPLES; i++) {
2512 ret = __phy_read(phydev, MII_88E6390_TEMP_SENSOR);
2515 sum += ret & MII_88E6390_TEMP_SENSOR_MASK;
2518 sum /= MII_88E6390_TEMP_SENSOR_SAMPLES;
2519 *temp = (sum - 75) * 1000;
2521 /* Disable temperature sensor */
2522 ret = __phy_read(phydev, MII_88E6390_MISC_TEST);
2526 ret = ret & ~MII_88E6390_MISC_TEST_SAMPLE_MASK;
2527 ret |= MII_88E6390_MISC_TEST_SAMPLE_DISABLE;
2529 ret = __phy_write(phydev, MII_88E6390_MISC_TEST, ret);
2532 phy_restore_page(phydev, oldpage, ret);
2537 static int m88e6390_hwmon_read(struct device *dev,
2538 enum hwmon_sensor_types type,
2539 u32 attr, int channel, long *temp)
2541 struct phy_device *phydev = dev_get_drvdata(dev);
2545 case hwmon_temp_input:
2546 err = m88e6390_get_temp(phydev, temp);
2555 static umode_t m88e6390_hwmon_is_visible(const void *data,
2556 enum hwmon_sensor_types type,
2557 u32 attr, int channel)
2559 if (type != hwmon_temp)
2563 case hwmon_temp_input:
2570 static u32 m88e6390_hwmon_temp_config[] = {
2575 static const struct hwmon_channel_info m88e6390_hwmon_temp = {
2577 .config = m88e6390_hwmon_temp_config,
2580 static const struct hwmon_channel_info *m88e6390_hwmon_info[] = {
2581 &m88e1121_hwmon_chip,
2582 &m88e6390_hwmon_temp,
2586 static const struct hwmon_ops m88e6390_hwmon_hwmon_ops = {
2587 .is_visible = m88e6390_hwmon_is_visible,
2588 .read = m88e6390_hwmon_read,
2591 static const struct hwmon_chip_info m88e6390_hwmon_chip_info = {
2592 .ops = &m88e6390_hwmon_hwmon_ops,
2593 .info = m88e6390_hwmon_info,
2596 static int marvell_hwmon_name(struct phy_device *phydev)
2598 struct marvell_priv *priv = phydev->priv;
2599 struct device *dev = &phydev->mdio.dev;
2600 const char *devname = dev_name(dev);
2601 size_t len = strlen(devname);
2604 priv->hwmon_name = devm_kzalloc(dev, len, GFP_KERNEL);
2605 if (!priv->hwmon_name)
2608 for (i = j = 0; i < len && devname[i]; i++) {
2609 if (isalnum(devname[i]))
2610 priv->hwmon_name[j++] = devname[i];
2616 static int marvell_hwmon_probe(struct phy_device *phydev,
2617 const struct hwmon_chip_info *chip)
2619 struct marvell_priv *priv = phydev->priv;
2620 struct device *dev = &phydev->mdio.dev;
2623 err = marvell_hwmon_name(phydev);
2627 priv->hwmon_dev = devm_hwmon_device_register_with_info(
2628 dev, priv->hwmon_name, phydev, chip, NULL);
2630 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
2633 static int m88e1121_hwmon_probe(struct phy_device *phydev)
2635 return marvell_hwmon_probe(phydev, &m88e1121_hwmon_chip_info);
2638 static int m88e1510_hwmon_probe(struct phy_device *phydev)
2640 return marvell_hwmon_probe(phydev, &m88e1510_hwmon_chip_info);
2643 static int m88e6390_hwmon_probe(struct phy_device *phydev)
2645 return marvell_hwmon_probe(phydev, &m88e6390_hwmon_chip_info);
2648 static int m88e1121_hwmon_probe(struct phy_device *phydev)
2653 static int m88e1510_hwmon_probe(struct phy_device *phydev)
2658 static int m88e6390_hwmon_probe(struct phy_device *phydev)
2664 static int marvell_probe(struct phy_device *phydev)
2666 struct marvell_priv *priv;
2668 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2672 phydev->priv = priv;
2677 static int m88e1121_probe(struct phy_device *phydev)
2681 err = marvell_probe(phydev);
2685 return m88e1121_hwmon_probe(phydev);
2688 static int m88e1510_probe(struct phy_device *phydev)
2692 err = marvell_probe(phydev);
2696 return m88e1510_hwmon_probe(phydev);
2699 static int m88e6390_probe(struct phy_device *phydev)
2703 err = marvell_probe(phydev);
2707 return m88e6390_hwmon_probe(phydev);
2710 static struct phy_driver marvell_drivers[] = {
2712 .phy_id = MARVELL_PHY_ID_88E1101,
2713 .phy_id_mask = MARVELL_PHY_ID_MASK,
2714 .name = "Marvell 88E1101",
2715 /* PHY_GBIT_FEATURES */
2716 .probe = marvell_probe,
2717 .config_init = marvell_config_init,
2718 .config_aneg = m88e1101_config_aneg,
2719 .config_intr = marvell_config_intr,
2720 .handle_interrupt = marvell_handle_interrupt,
2721 .resume = genphy_resume,
2722 .suspend = genphy_suspend,
2723 .read_page = marvell_read_page,
2724 .write_page = marvell_write_page,
2725 .get_sset_count = marvell_get_sset_count,
2726 .get_strings = marvell_get_strings,
2727 .get_stats = marvell_get_stats,
2730 .phy_id = MARVELL_PHY_ID_88E1112,
2731 .phy_id_mask = MARVELL_PHY_ID_MASK,
2732 .name = "Marvell 88E1112",
2733 /* PHY_GBIT_FEATURES */
2734 .probe = marvell_probe,
2735 .config_init = m88e1111_config_init,
2736 .config_aneg = marvell_config_aneg,
2737 .config_intr = marvell_config_intr,
2738 .handle_interrupt = marvell_handle_interrupt,
2739 .resume = genphy_resume,
2740 .suspend = genphy_suspend,
2741 .read_page = marvell_read_page,
2742 .write_page = marvell_write_page,
2743 .get_sset_count = marvell_get_sset_count,
2744 .get_strings = marvell_get_strings,
2745 .get_stats = marvell_get_stats,
2746 .get_tunable = m88e1011_get_tunable,
2747 .set_tunable = m88e1011_set_tunable,
2750 .phy_id = MARVELL_PHY_ID_88E1111,
2751 .phy_id_mask = MARVELL_PHY_ID_MASK,
2752 .name = "Marvell 88E1111",
2753 /* PHY_GBIT_FEATURES */
2754 .probe = marvell_probe,
2755 .config_init = m88e1111_config_init,
2756 .config_aneg = m88e1111_config_aneg,
2757 .read_status = marvell_read_status,
2758 .config_intr = marvell_config_intr,
2759 .handle_interrupt = marvell_handle_interrupt,
2760 .resume = genphy_resume,
2761 .suspend = genphy_suspend,
2762 .read_page = marvell_read_page,
2763 .write_page = marvell_write_page,
2764 .get_sset_count = marvell_get_sset_count,
2765 .get_strings = marvell_get_strings,
2766 .get_stats = marvell_get_stats,
2767 .get_tunable = m88e1111_get_tunable,
2768 .set_tunable = m88e1111_set_tunable,
2771 .phy_id = MARVELL_PHY_ID_88E1111_FINISAR,
2772 .phy_id_mask = MARVELL_PHY_ID_MASK,
2773 .name = "Marvell 88E1111 (Finisar)",
2774 /* PHY_GBIT_FEATURES */
2775 .probe = marvell_probe,
2776 .config_init = m88e1111_config_init,
2777 .config_aneg = m88e1111_config_aneg,
2778 .read_status = marvell_read_status,
2779 .config_intr = marvell_config_intr,
2780 .handle_interrupt = marvell_handle_interrupt,
2781 .resume = genphy_resume,
2782 .suspend = genphy_suspend,
2783 .read_page = marvell_read_page,
2784 .write_page = marvell_write_page,
2785 .get_sset_count = marvell_get_sset_count,
2786 .get_strings = marvell_get_strings,
2787 .get_stats = marvell_get_stats,
2788 .get_tunable = m88e1111_get_tunable,
2789 .set_tunable = m88e1111_set_tunable,
2792 .phy_id = MARVELL_PHY_ID_88E1118,
2793 .phy_id_mask = MARVELL_PHY_ID_MASK,
2794 .name = "Marvell 88E1118",
2795 /* PHY_GBIT_FEATURES */
2796 .probe = marvell_probe,
2797 .config_init = m88e1118_config_init,
2798 .config_aneg = m88e1118_config_aneg,
2799 .config_intr = marvell_config_intr,
2800 .handle_interrupt = marvell_handle_interrupt,
2801 .resume = genphy_resume,
2802 .suspend = genphy_suspend,
2803 .read_page = marvell_read_page,
2804 .write_page = marvell_write_page,
2805 .get_sset_count = marvell_get_sset_count,
2806 .get_strings = marvell_get_strings,
2807 .get_stats = marvell_get_stats,
2810 .phy_id = MARVELL_PHY_ID_88E1121R,
2811 .phy_id_mask = MARVELL_PHY_ID_MASK,
2812 .name = "Marvell 88E1121R",
2813 /* PHY_GBIT_FEATURES */
2814 .probe = m88e1121_probe,
2815 .config_init = marvell_config_init,
2816 .config_aneg = m88e1121_config_aneg,
2817 .read_status = marvell_read_status,
2818 .config_intr = marvell_config_intr,
2819 .handle_interrupt = marvell_handle_interrupt,
2820 .resume = genphy_resume,
2821 .suspend = genphy_suspend,
2822 .read_page = marvell_read_page,
2823 .write_page = marvell_write_page,
2824 .get_sset_count = marvell_get_sset_count,
2825 .get_strings = marvell_get_strings,
2826 .get_stats = marvell_get_stats,
2827 .get_tunable = m88e1011_get_tunable,
2828 .set_tunable = m88e1011_set_tunable,
2831 .phy_id = MARVELL_PHY_ID_88E1318S,
2832 .phy_id_mask = MARVELL_PHY_ID_MASK,
2833 .name = "Marvell 88E1318S",
2834 /* PHY_GBIT_FEATURES */
2835 .probe = marvell_probe,
2836 .config_init = m88e1318_config_init,
2837 .config_aneg = m88e1318_config_aneg,
2838 .read_status = marvell_read_status,
2839 .config_intr = marvell_config_intr,
2840 .handle_interrupt = marvell_handle_interrupt,
2841 .get_wol = m88e1318_get_wol,
2842 .set_wol = m88e1318_set_wol,
2843 .resume = genphy_resume,
2844 .suspend = genphy_suspend,
2845 .read_page = marvell_read_page,
2846 .write_page = marvell_write_page,
2847 .get_sset_count = marvell_get_sset_count,
2848 .get_strings = marvell_get_strings,
2849 .get_stats = marvell_get_stats,
2852 .phy_id = MARVELL_PHY_ID_88E1145,
2853 .phy_id_mask = MARVELL_PHY_ID_MASK,
2854 .name = "Marvell 88E1145",
2855 /* PHY_GBIT_FEATURES */
2856 .probe = marvell_probe,
2857 .config_init = m88e1145_config_init,
2858 .config_aneg = m88e1101_config_aneg,
2859 .config_intr = marvell_config_intr,
2860 .handle_interrupt = marvell_handle_interrupt,
2861 .resume = genphy_resume,
2862 .suspend = genphy_suspend,
2863 .read_page = marvell_read_page,
2864 .write_page = marvell_write_page,
2865 .get_sset_count = marvell_get_sset_count,
2866 .get_strings = marvell_get_strings,
2867 .get_stats = marvell_get_stats,
2868 .get_tunable = m88e1111_get_tunable,
2869 .set_tunable = m88e1111_set_tunable,
2872 .phy_id = MARVELL_PHY_ID_88E1149R,
2873 .phy_id_mask = MARVELL_PHY_ID_MASK,
2874 .name = "Marvell 88E1149R",
2875 /* PHY_GBIT_FEATURES */
2876 .probe = marvell_probe,
2877 .config_init = m88e1149_config_init,
2878 .config_aneg = m88e1118_config_aneg,
2879 .config_intr = marvell_config_intr,
2880 .handle_interrupt = marvell_handle_interrupt,
2881 .resume = genphy_resume,
2882 .suspend = genphy_suspend,
2883 .read_page = marvell_read_page,
2884 .write_page = marvell_write_page,
2885 .get_sset_count = marvell_get_sset_count,
2886 .get_strings = marvell_get_strings,
2887 .get_stats = marvell_get_stats,
2890 .phy_id = MARVELL_PHY_ID_88E1240,
2891 .phy_id_mask = MARVELL_PHY_ID_MASK,
2892 .name = "Marvell 88E1240",
2893 /* PHY_GBIT_FEATURES */
2894 .probe = marvell_probe,
2895 .config_init = m88e1111_config_init,
2896 .config_aneg = marvell_config_aneg,
2897 .config_intr = marvell_config_intr,
2898 .handle_interrupt = marvell_handle_interrupt,
2899 .resume = genphy_resume,
2900 .suspend = genphy_suspend,
2901 .read_page = marvell_read_page,
2902 .write_page = marvell_write_page,
2903 .get_sset_count = marvell_get_sset_count,
2904 .get_strings = marvell_get_strings,
2905 .get_stats = marvell_get_stats,
2908 .phy_id = MARVELL_PHY_ID_88E1116R,
2909 .phy_id_mask = MARVELL_PHY_ID_MASK,
2910 .name = "Marvell 88E1116R",
2911 /* PHY_GBIT_FEATURES */
2912 .probe = marvell_probe,
2913 .config_init = m88e1116r_config_init,
2914 .config_intr = marvell_config_intr,
2915 .handle_interrupt = marvell_handle_interrupt,
2916 .resume = genphy_resume,
2917 .suspend = genphy_suspend,
2918 .read_page = marvell_read_page,
2919 .write_page = marvell_write_page,
2920 .get_sset_count = marvell_get_sset_count,
2921 .get_strings = marvell_get_strings,
2922 .get_stats = marvell_get_stats,
2923 .get_tunable = m88e1011_get_tunable,
2924 .set_tunable = m88e1011_set_tunable,
2927 .phy_id = MARVELL_PHY_ID_88E1510,
2928 .phy_id_mask = MARVELL_PHY_ID_MASK,
2929 .name = "Marvell 88E1510",
2930 .features = PHY_GBIT_FIBRE_FEATURES,
2931 .flags = PHY_POLL_CABLE_TEST,
2932 .probe = m88e1510_probe,
2933 .config_init = m88e1510_config_init,
2934 .config_aneg = m88e1510_config_aneg,
2935 .read_status = marvell_read_status,
2936 .config_intr = marvell_config_intr,
2937 .handle_interrupt = marvell_handle_interrupt,
2938 .get_wol = m88e1318_get_wol,
2939 .set_wol = m88e1318_set_wol,
2940 .resume = marvell_resume,
2941 .suspend = marvell_suspend,
2942 .read_page = marvell_read_page,
2943 .write_page = marvell_write_page,
2944 .get_sset_count = marvell_get_sset_count,
2945 .get_strings = marvell_get_strings,
2946 .get_stats = marvell_get_stats,
2947 .set_loopback = genphy_loopback,
2948 .get_tunable = m88e1011_get_tunable,
2949 .set_tunable = m88e1011_set_tunable,
2950 .cable_test_start = marvell_vct7_cable_test_start,
2951 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2952 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2955 .phy_id = MARVELL_PHY_ID_88E1540,
2956 .phy_id_mask = MARVELL_PHY_ID_MASK,
2957 .name = "Marvell 88E1540",
2958 /* PHY_GBIT_FEATURES */
2959 .flags = PHY_POLL_CABLE_TEST,
2960 .probe = m88e1510_probe,
2961 .config_init = marvell_config_init,
2962 .config_aneg = m88e1510_config_aneg,
2963 .read_status = marvell_read_status,
2964 .config_intr = marvell_config_intr,
2965 .handle_interrupt = marvell_handle_interrupt,
2966 .resume = genphy_resume,
2967 .suspend = genphy_suspend,
2968 .read_page = marvell_read_page,
2969 .write_page = marvell_write_page,
2970 .get_sset_count = marvell_get_sset_count,
2971 .get_strings = marvell_get_strings,
2972 .get_stats = marvell_get_stats,
2973 .get_tunable = m88e1540_get_tunable,
2974 .set_tunable = m88e1540_set_tunable,
2975 .cable_test_start = marvell_vct7_cable_test_start,
2976 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
2977 .cable_test_get_status = marvell_vct7_cable_test_get_status,
2980 .phy_id = MARVELL_PHY_ID_88E1545,
2981 .phy_id_mask = MARVELL_PHY_ID_MASK,
2982 .name = "Marvell 88E1545",
2983 .probe = m88e1510_probe,
2984 /* PHY_GBIT_FEATURES */
2985 .flags = PHY_POLL_CABLE_TEST,
2986 .config_init = marvell_config_init,
2987 .config_aneg = m88e1510_config_aneg,
2988 .read_status = marvell_read_status,
2989 .config_intr = marvell_config_intr,
2990 .handle_interrupt = marvell_handle_interrupt,
2991 .resume = genphy_resume,
2992 .suspend = genphy_suspend,
2993 .read_page = marvell_read_page,
2994 .write_page = marvell_write_page,
2995 .get_sset_count = marvell_get_sset_count,
2996 .get_strings = marvell_get_strings,
2997 .get_stats = marvell_get_stats,
2998 .get_tunable = m88e1540_get_tunable,
2999 .set_tunable = m88e1540_set_tunable,
3000 .cable_test_start = marvell_vct7_cable_test_start,
3001 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3002 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3005 .phy_id = MARVELL_PHY_ID_88E3016,
3006 .phy_id_mask = MARVELL_PHY_ID_MASK,
3007 .name = "Marvell 88E3016",
3008 /* PHY_BASIC_FEATURES */
3009 .probe = marvell_probe,
3010 .config_init = m88e3016_config_init,
3011 .aneg_done = marvell_aneg_done,
3012 .read_status = marvell_read_status,
3013 .config_intr = marvell_config_intr,
3014 .handle_interrupt = marvell_handle_interrupt,
3015 .resume = genphy_resume,
3016 .suspend = genphy_suspend,
3017 .read_page = marvell_read_page,
3018 .write_page = marvell_write_page,
3019 .get_sset_count = marvell_get_sset_count,
3020 .get_strings = marvell_get_strings,
3021 .get_stats = marvell_get_stats,
3024 .phy_id = MARVELL_PHY_ID_88E6390,
3025 .phy_id_mask = MARVELL_PHY_ID_MASK,
3026 .name = "Marvell 88E6390",
3027 /* PHY_GBIT_FEATURES */
3028 .flags = PHY_POLL_CABLE_TEST,
3029 .probe = m88e6390_probe,
3030 .config_init = marvell_config_init,
3031 .config_aneg = m88e6390_config_aneg,
3032 .read_status = marvell_read_status,
3033 .config_intr = marvell_config_intr,
3034 .handle_interrupt = marvell_handle_interrupt,
3035 .resume = genphy_resume,
3036 .suspend = genphy_suspend,
3037 .read_page = marvell_read_page,
3038 .write_page = marvell_write_page,
3039 .get_sset_count = marvell_get_sset_count,
3040 .get_strings = marvell_get_strings,
3041 .get_stats = marvell_get_stats,
3042 .get_tunable = m88e1540_get_tunable,
3043 .set_tunable = m88e1540_set_tunable,
3044 .cable_test_start = marvell_vct7_cable_test_start,
3045 .cable_test_tdr_start = marvell_vct5_cable_test_tdr_start,
3046 .cable_test_get_status = marvell_vct7_cable_test_get_status,
3049 .phy_id = MARVELL_PHY_ID_88E1340S,
3050 .phy_id_mask = MARVELL_PHY_ID_MASK,
3051 .name = "Marvell 88E1340S",
3052 .probe = m88e1510_probe,
3053 /* PHY_GBIT_FEATURES */
3054 .config_init = marvell_config_init,
3055 .config_aneg = m88e1510_config_aneg,
3056 .read_status = marvell_read_status,
3057 .config_intr = marvell_config_intr,
3058 .handle_interrupt = marvell_handle_interrupt,
3059 .resume = genphy_resume,
3060 .suspend = genphy_suspend,
3061 .read_page = marvell_read_page,
3062 .write_page = marvell_write_page,
3063 .get_sset_count = marvell_get_sset_count,
3064 .get_strings = marvell_get_strings,
3065 .get_stats = marvell_get_stats,
3066 .get_tunable = m88e1540_get_tunable,
3067 .set_tunable = m88e1540_set_tunable,
3070 .phy_id = MARVELL_PHY_ID_88E1548P,
3071 .phy_id_mask = MARVELL_PHY_ID_MASK,
3072 .name = "Marvell 88E1548P",
3073 .probe = m88e1510_probe,
3074 .features = PHY_GBIT_FIBRE_FEATURES,
3075 .config_init = marvell_config_init,
3076 .config_aneg = m88e1510_config_aneg,
3077 .read_status = marvell_read_status,
3078 .config_intr = marvell_config_intr,
3079 .handle_interrupt = marvell_handle_interrupt,
3080 .resume = genphy_resume,
3081 .suspend = genphy_suspend,
3082 .read_page = marvell_read_page,
3083 .write_page = marvell_write_page,
3084 .get_sset_count = marvell_get_sset_count,
3085 .get_strings = marvell_get_strings,
3086 .get_stats = marvell_get_stats,
3087 .get_tunable = m88e1540_get_tunable,
3088 .set_tunable = m88e1540_set_tunable,
3092 module_phy_driver(marvell_drivers);
3094 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
3095 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
3096 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
3097 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
3098 { MARVELL_PHY_ID_88E1111_FINISAR, MARVELL_PHY_ID_MASK },
3099 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
3100 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
3101 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
3102 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
3103 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
3104 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
3105 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
3106 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
3107 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
3108 { MARVELL_PHY_ID_88E1545, MARVELL_PHY_ID_MASK },
3109 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
3110 { MARVELL_PHY_ID_88E6390, MARVELL_PHY_ID_MASK },
3111 { MARVELL_PHY_ID_88E1340S, MARVELL_PHY_ID_MASK },
3112 { MARVELL_PHY_ID_88E1548P, MARVELL_PHY_ID_MASK },
3116 MODULE_DEVICE_TABLE(mdio, marvell_tbl);