drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 struct amdgpu_fence {
  51         struct dma_fence base;
  52
  53         /* RB, DMA, etc. */
  54         struct amdgpu_ring              *ring;
  55 };
  56
  57 static struct kmem_cache *amdgpu_fence_slab;
  58
  59 int amdgpu_fence_slab_init(void)
  60 {
  61         amdgpu_fence_slab = kmem_cache_create(
  62                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  63                 SLAB_HWCACHE_ALIGN, NULL);
  64         if (!amdgpu_fence_slab)
  65                 return -ENOMEM;
  66         return 0;
  67 }
  68
  69 void amdgpu_fence_slab_fini(void)
  70 {
  71         rcu_barrier();
  72         kmem_cache_destroy(amdgpu_fence_slab);
  73 }
  74 /*
  75  * Cast helper
  76  */
  77 static const struct dma_fence_ops amdgpu_fence_ops;
  78 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  79 {
  80         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  81
  82         if (__f->base.ops == &amdgpu_fence_ops)
  83                 return __f;
  84
  85         return NULL;
  86 }
  87
  88 /**
  89  * amdgpu_fence_write - write a fence value
  90  *
  91  * @ring: ring the fence is associated with
  92  * @seq: sequence number to write
  93  *
  94  * Writes a fence value to memory (all asics).
  95  */
  96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  97 {
  98         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  99
 100         if (drv->cpu_addr)
 101                 *drv->cpu_addr = cpu_to_le32(seq);
 102 }
 103
 104 /**
 105  * amdgpu_fence_read - read a fence value
 106  *
 107  * @ring: ring the fence is associated with
 108  *
 109  * Reads a fence value from memory (all asics).
 110  * Returns the value of the fence read from memory.
 111  */
 112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 113 {
 114         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 115         u32 seq = 0;
 116
 117         if (drv->cpu_addr)
 118                 seq = le32_to_cpu(*drv->cpu_addr);
 119         else
 120                 seq = atomic_read(&drv->last_seq);
 121
 122         return seq;
 123 }
 124
 125 /**
 126  * amdgpu_fence_emit - emit a fence on the requested ring
 127  *
 128  * @ring: ring the fence is associated with
 129  * @f: resulting fence object
 130  *
 131  * Emits a fence command on the requested ring (all asics).
 132  * Returns 0 on success, -ENOMEM on failure.
 133  */
 134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
 135                       unsigned flags)
 136 {
 137         struct amdgpu_device *adev = ring->adev;
 138         struct amdgpu_fence *fence;
 139         struct dma_fence *old, **ptr;
 140         uint32_t seq;
 141
 142         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 143         if (fence == NULL)
 144                 return -ENOMEM;
 145
 146         seq = ++ring->fence_drv.sync_seq;
 147         fence->ring = ring;
 148         dma_fence_init(&fence->base, &amdgpu_fence_ops,
 149                        &ring->fence_drv.lock,
 150                        adev->fence_context + ring->idx,
 151                        seq);
 152         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 153                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 154
 155         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 156         /* This function can't be called concurrently anyway, otherwise
 157          * emitting the fence would mess up the hardware ring buffer.
 158          */
 159         old = rcu_dereference_protected(*ptr, 1);
 160         if (old && !dma_fence_is_signaled(old)) {
 161                 DRM_INFO("rcu slot is busy\n");
 162                 dma_fence_wait(old, false);
 163         }
 164
 165         rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
 166
 167         *f = &fence->base;
 168
 169         return 0;
 170 }
 171
 172 /**
 173  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 174  *
 175  * @ring: ring the fence is associated with
 176  * @s: resulting sequence number
 177  *
 178  * Emits a fence command on the requested ring (all asics).
 179  * Used For polling fence.
 180  * Returns 0 on success, -ENOMEM on failure.
 181  */
 182 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
 183 {
 184         uint32_t seq;
 185
 186         if (!s)
 187                 return -EINVAL;
 188
 189         seq = ++ring->fence_drv.sync_seq;
 190         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 191                                seq, 0);
 192
 193         *s = seq;
 194
 195         return 0;
 196 }
 197
 198 /**
 199  * amdgpu_fence_process - check for fence activity
 200  *
 201  * @ring: pointer to struct amdgpu_ring
 202  *
 203  * Checks the current fence value and calculates the last
 204  * signalled fence value. Wakes the fence queue if the
 205  * sequence number has increased.
 206  */
 207 void amdgpu_fence_process(struct amdgpu_ring *ring)
 208 {
 209         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 210         uint32_t seq, last_seq;
 211         int r;
 212
 213         do {
 214                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 215                 seq = amdgpu_fence_read(ring);
 216
 217         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 218
 219         if (unlikely(seq == last_seq))
 220                 return;
 221
 222         last_seq &= drv->num_fences_mask;
 223         seq &= drv->num_fences_mask;
 224
 225         do {
 226                 struct dma_fence *fence, **ptr;
 227
 228                 ++last_seq;
 229                 last_seq &= drv->num_fences_mask;
 230                 ptr = &drv->fences[last_seq];
 231
 232                 /* There is always exactly one thread signaling this fence slot */
 233                 fence = rcu_dereference_protected(*ptr, 1);
 234                 RCU_INIT_POINTER(*ptr, NULL);
 235
 236                 if (!fence)
 237                         continue;
 238
 239                 r = dma_fence_signal(fence);
 240                 if (!r)
 241                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 242                 else
 243                         BUG();
 244
 245                 dma_fence_put(fence);
 246         } while (last_seq != seq);
 247 }
 248
 249 /**
 250  * amdgpu_fence_wait_empty - wait for all fences to signal
 251  *
 252  * @adev: amdgpu device pointer
 253  * @ring: ring index the fence is associated with
 254  *
 255  * Wait for all fences on the requested ring to signal (all asics).
 256  * Returns 0 if the fences have passed, error for all other cases.
 257  */
 258 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 259 {
 260         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 261         struct dma_fence *fence, **ptr;
 262         int r;
 263
 264         if (!seq)
 265                 return 0;
 266
 267         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 268         rcu_read_lock();
 269         fence = rcu_dereference(*ptr);
 270         if (!fence || !dma_fence_get_rcu(fence)) {
 271                 rcu_read_unlock();
 272                 return 0;
 273         }
 274         rcu_read_unlock();
 275
 276         r = dma_fence_wait(fence, false);
 277         dma_fence_put(fence);
 278         return r;
 279 }
 280
 281 /**
 282  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 283  *
 284  * @ring: ring index the fence is associated with
 285  * @wait_seq: sequence number to wait
 286  * @timeout: the timeout for waiting in usecs
 287  *
 288  * Wait for all fences on the requested ring to signal (all asics).
 289  * Returns left time if no timeout, 0 or minus if timeout.
 290  */
 291 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 292                                       uint32_t wait_seq,
 293                                       signed long timeout)
 294 {
 295         uint32_t seq;
 296
 297         do {
 298                 seq = amdgpu_fence_read(ring);
 299                 udelay(5);
 300                 timeout -= 5;
 301         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 302
 303         return timeout > 0 ? timeout : 0;
 304 }
 305 /**
 306  * amdgpu_fence_count_emitted - get the count of emitted fences
 307  *
 308  * @ring: ring the fence is associated with
 309  *
 310  * Get the number of fences emitted on the requested ring (all asics).
 311  * Returns the number of emitted fences on the ring.  Used by the
 312  * dynpm code to ring track activity.
 313  */
 314 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 315 {
 316         uint64_t emitted;
 317
 318         /* We are not protected by ring lock when reading the last sequence
 319          * but it's ok to report slightly wrong fence count here.
 320          */
 321         amdgpu_fence_process(ring);
 322         emitted = 0x100000000ull;
 323         emitted -= atomic_read(&ring->fence_drv.last_seq);
 324         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 325         return lower_32_bits(emitted);
 326 }
 327
 328 /**
 329  * amdgpu_fence_driver_start_ring - make the fence driver
 330  * ready for use on the requested ring.
 331  *
 332  * @ring: ring to start the fence driver on
 333  * @irq_src: interrupt source to use for this ring
 334  * @irq_type: interrupt type to use for this ring
 335  *
 336  * Make the fence driver ready for processing (all asics).
 337  * Not all asics have all rings, so each asic will only
 338  * start the fence driver on the rings it has.
 339  * Returns 0 for success, errors for failure.
 340  */
 341 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 342                                    struct amdgpu_irq_src *irq_src,
 343                                    unsigned irq_type)
 344 {
 345         struct amdgpu_device *adev = ring->adev;
 346         uint64_t index;
 347
 348         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 349                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 350                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 351         } else {
 352                 /* put fence directly behind firmware */
 353                 index = ALIGN(adev->uvd.fw->size, 8);
 354                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 355                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 356         }
 357         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 358         amdgpu_irq_get(adev, irq_src, irq_type);
 359
 360         ring->fence_drv.irq_src = irq_src;
 361         ring->fence_drv.irq_type = irq_type;
 362         ring->fence_drv.initialized = true;
 363
 364         dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 365                 "cpu addr 0x%p\n", ring->idx,
 366                 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 367         return 0;
 368 }
 369
 370 /**
 371  * amdgpu_fence_driver_init_ring - init the fence driver
 372  * for the requested ring.
 373  *
 374  * @ring: ring to init the fence driver on
 375  * @num_hw_submission: number of entries on the hardware queue
 376  *
 377  * Init the fence driver for the requested ring (all asics).
 378  * Helper function for amdgpu_fence_driver_init().
 379  */
 380 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 381                                   unsigned num_hw_submission)
 382 {
 383         long timeout;
 384         int r;
 385
 386         /* Check that num_hw_submission is a power of two */
 387         if ((num_hw_submission & (num_hw_submission - 1)) != 0)
 388                 return -EINVAL;
 389
 390         ring->fence_drv.cpu_addr = NULL;
 391         ring->fence_drv.gpu_addr = 0;
 392         ring->fence_drv.sync_seq = 0;
 393         atomic_set(&ring->fence_drv.last_seq, 0);
 394         ring->fence_drv.initialized = false;
 395
 396         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 397         spin_lock_init(&ring->fence_drv.lock);
 398         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 399                                          GFP_KERNEL);
 400         if (!ring->fence_drv.fences)
 401                 return -ENOMEM;
 402
 403         /* No need to setup the GPU scheduler for KIQ ring */
 404         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
 405                 /* for non-sriov case, no timeout enforce on compute ring */
 406                 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
 407                                 && !amdgpu_sriov_vf(ring->adev))
 408                         timeout = MAX_SCHEDULE_TIMEOUT;
 409                 else
 410                         timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
 411
 412                 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 413                                    num_hw_submission, amdgpu_job_hang_limit,
 414                                    timeout, ring->name);
 415                 if (r) {
 416                         DRM_ERROR("Failed to create scheduler on ring %s.\n",
 417                                   ring->name);
 418                         return r;
 419                 }
 420         }
 421
 422         return 0;
 423 }
 424
 425 /**
 426  * amdgpu_fence_driver_init - init the fence driver
 427  * for all possible rings.
 428  *
 429  * @adev: amdgpu device pointer
 430  *
 431  * Init the fence driver for all possible rings (all asics).
 432  * Not all asics have all rings, so each asic will only
 433  * start the fence driver on the rings it has using
 434  * amdgpu_fence_driver_start_ring().
 435  * Returns 0 for success.
 436  */
 437 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 438 {
 439         if (amdgpu_debugfs_fence_init(adev))
 440                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 441
 442         return 0;
 443 }
 444
 445 /**
 446  * amdgpu_fence_driver_fini - tear down the fence driver
 447  * for all possible rings.
 448  *
 449  * @adev: amdgpu device pointer
 450  *
 451  * Tear down the fence driver for all possible rings (all asics).
 452  */
 453 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 454 {
 455         unsigned i, j;
 456         int r;
 457
 458         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 459                 struct amdgpu_ring *ring = adev->rings[i];
 460
 461                 if (!ring || !ring->fence_drv.initialized)
 462                         continue;
 463                 r = amdgpu_fence_wait_empty(ring);
 464                 if (r) {
 465                         /* no need to trigger GPU reset as we are unloading */
 466                         amdgpu_fence_driver_force_completion(ring);
 467                 }
 468                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 469                                ring->fence_drv.irq_type);
 470                 drm_sched_fini(&ring->sched);
 471                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 472                         dma_fence_put(ring->fence_drv.fences[j]);
 473                 kfree(ring->fence_drv.fences);
 474                 ring->fence_drv.fences = NULL;
 475                 ring->fence_drv.initialized = false;
 476         }
 477 }
 478
 479 /**
 480  * amdgpu_fence_driver_suspend - suspend the fence driver
 481  * for all possible rings.
 482  *
 483  * @adev: amdgpu device pointer
 484  *
 485  * Suspend the fence driver for all possible rings (all asics).
 486  */
 487 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 488 {
 489         int i, r;
 490
 491         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 492                 struct amdgpu_ring *ring = adev->rings[i];
 493                 if (!ring || !ring->fence_drv.initialized)
 494                         continue;
 495
 496                 /* wait for gpu to finish processing current batch */
 497                 r = amdgpu_fence_wait_empty(ring);
 498                 if (r) {
 499                         /* delay GPU reset to resume */
 500                         amdgpu_fence_driver_force_completion(ring);
 501                 }
 502
 503                 /* disable the interrupt */
 504                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 505                                ring->fence_drv.irq_type);
 506         }
 507 }
 508
 509 /**
 510  * amdgpu_fence_driver_resume - resume the fence driver
 511  * for all possible rings.
 512  *
 513  * @adev: amdgpu device pointer
 514  *
 515  * Resume the fence driver for all possible rings (all asics).
 516  * Not all asics have all rings, so each asic will only
 517  * start the fence driver on the rings it has using
 518  * amdgpu_fence_driver_start_ring().
 519  * Returns 0 for success.
 520  */
 521 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 522 {
 523         int i;
 524
 525         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 526                 struct amdgpu_ring *ring = adev->rings[i];
 527                 if (!ring || !ring->fence_drv.initialized)
 528                         continue;
 529
 530                 /* enable the interrupt */
 531                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 532                                ring->fence_drv.irq_type);
 533         }
 534 }
 535
 536 /**
 537  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 538  *
 539  * @ring: fence of the ring to signal
 540  *
 541  */
 542 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 543 {
 544         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 545         amdgpu_fence_process(ring);
 546 }
 547
 548 /*
 549  * Common fence implementation
 550  */
 551
 552 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 553 {
 554         return "amdgpu";
 555 }
 556
 557 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 558 {
 559         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 560         return (const char *)fence->ring->name;
 561 }
 562
 563 /**
 564  * amdgpu_fence_free - free up the fence memory
 565  *
 566  * @rcu: RCU callback head
 567  *
 568  * Free up the fence memory after the RCU grace period.
 569  */
 570 static void amdgpu_fence_free(struct rcu_head *rcu)
 571 {
 572         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 573         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 574         kmem_cache_free(amdgpu_fence_slab, fence);
 575 }
 576
 577 /**
 578  * amdgpu_fence_release - callback that fence can be freed
 579  *
 580  * @fence: fence
 581  *
 582  * This function is called when the reference count becomes zero.
 583  * It just RCU schedules freeing up the fence.
 584  */
 585 static void amdgpu_fence_release(struct dma_fence *f)
 586 {
 587         call_rcu(&f->rcu, amdgpu_fence_free);
 588 }
 589
 590 static const struct dma_fence_ops amdgpu_fence_ops = {
 591         .get_driver_name = amdgpu_fence_get_driver_name,
 592         .get_timeline_name = amdgpu_fence_get_timeline_name,
 593         .release = amdgpu_fence_release,
 594 };
 595
 596 /*
 597  * Fence debugfs
 598  */
 599 #if defined(CONFIG_DEBUG_FS)
 600 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 601 {
 602         struct drm_info_node *node = (struct drm_info_node *)m->private;
 603         struct drm_device *dev = node->minor->dev;
 604         struct amdgpu_device *adev = dev->dev_private;
 605         int i;
 606
 607         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 608                 struct amdgpu_ring *ring = adev->rings[i];
 609                 if (!ring || !ring->fence_drv.initialized)
 610                         continue;
 611
 612                 amdgpu_fence_process(ring);
 613
 614                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 615                 seq_printf(m, "Last signaled fence 0x%08x\n",
 616                            atomic_read(&ring->fence_drv.last_seq));
 617                 seq_printf(m, "Last emitted        0x%08x\n",
 618                            ring->fence_drv.sync_seq);
 619
 620                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 621                         continue;
 622
 623                 /* set in CP_VMID_PREEMPT and preemption occurred */
 624                 seq_printf(m, "Last preempted      0x%08x\n",
 625                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 626                 /* set in CP_VMID_RESET and reset occurred */
 627                 seq_printf(m, "Last reset          0x%08x\n",
 628                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 629                 /* Both preemption and reset occurred */
 630                 seq_printf(m, "Last both           0x%08x\n",
 631                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 632         }
 633         return 0;
 634 }
 635
 636 /**
 637  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 638  *
 639  * Manually trigger a gpu reset at the next fence wait.
 640  */
 641 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
 642 {
 643         struct drm_info_node *node = (struct drm_info_node *) m->private;
 644         struct drm_device *dev = node->minor->dev;
 645         struct amdgpu_device *adev = dev->dev_private;
 646
 647         seq_printf(m, "gpu recover\n");
 648         amdgpu_device_gpu_recover(adev, NULL);
 649
 650         return 0;
 651 }
 652
 653 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
 654         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 655         {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
 656 };
 657
 658 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
 659         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 660 };
 661 #endif
 662
 663 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 664 {
 665 #if defined(CONFIG_DEBUG_FS)
 666         if (amdgpu_sriov_vf(adev))
 667                 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
 668         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
 669 #else
 670         return 0;
 671 #endif
 672 }
 673