drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31
  32 enum smu_event_type {
  33         SMU_EVENT_RESET_COMPLETE = 0,
  34 };
  35
  36 struct amd_vce_state {
  37         /* vce clocks */
  38         u32 evclk;
  39         u32 ecclk;
  40         /* gpu clocks */
  41         u32 sclk;
  42         u32 mclk;
  43         u8 clk_idx;
  44         u8 pstate;
  45 };
  46
  47
  48 enum amd_dpm_forced_level {
  49         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  50         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  51         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  52         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  53         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  58         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  59 };
  60
  61 enum amd_pm_state_type {
  62         /* not used for dpm */
  63         POWER_STATE_TYPE_DEFAULT,
  64         POWER_STATE_TYPE_POWERSAVE,
  65         /* user selectable states */
  66         POWER_STATE_TYPE_BATTERY,
  67         POWER_STATE_TYPE_BALANCED,
  68         POWER_STATE_TYPE_PERFORMANCE,
  69         /* internal states */
  70         POWER_STATE_TYPE_INTERNAL_UVD,
  71         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  74         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  75         POWER_STATE_TYPE_INTERNAL_BOOT,
  76         POWER_STATE_TYPE_INTERNAL_THERMAL,
  77         POWER_STATE_TYPE_INTERNAL_ACPI,
  78         POWER_STATE_TYPE_INTERNAL_ULV,
  79         POWER_STATE_TYPE_INTERNAL_3DPERF,
  80 };
  81
  82 #define AMD_MAX_VCE_LEVELS 6
  83
  84 enum amd_vce_level {
  85         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  86         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  87         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  88         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  89         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  90         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  91 };
  92
  93 enum amd_fan_ctrl_mode {
  94         AMD_FAN_CTRL_NONE = 0,
  95         AMD_FAN_CTRL_MANUAL = 1,
  96         AMD_FAN_CTRL_AUTO = 2,
  97 };
  98
  99 enum pp_clock_type {
 100         PP_SCLK,
 101         PP_MCLK,
 102         PP_PCIE,
 103         PP_SOCCLK,
 104         PP_FCLK,
 105         PP_DCEFCLK,
 106         PP_VCLK,
 107         PP_VCLK1,
 108         PP_DCLK,
 109         PP_DCLK1,
 110         OD_SCLK,
 111         OD_MCLK,
 112         OD_VDDC_CURVE,
 113         OD_RANGE,
 114         OD_VDDGFX_OFFSET,
 115         OD_CCLK,
 116         OD_FAN_CURVE,
 117         OD_ACOUSTIC_LIMIT,
 118         OD_ACOUSTIC_TARGET,
 119         OD_FAN_TARGET_TEMPERATURE,
 120         OD_FAN_MINIMUM_PWM,
 121 };
 122
 123 enum amd_pp_sensors {
 124         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 125         AMDGPU_PP_SENSOR_CPU_CLK,
 126         AMDGPU_PP_SENSOR_VDDNB,
 127         AMDGPU_PP_SENSOR_VDDGFX,
 128         AMDGPU_PP_SENSOR_UVD_VCLK,
 129         AMDGPU_PP_SENSOR_UVD_DCLK,
 130         AMDGPU_PP_SENSOR_VCE_ECCLK,
 131         AMDGPU_PP_SENSOR_GPU_LOAD,
 132         AMDGPU_PP_SENSOR_MEM_LOAD,
 133         AMDGPU_PP_SENSOR_GFX_MCLK,
 134         AMDGPU_PP_SENSOR_GPU_TEMP,
 135         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 136         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 137         AMDGPU_PP_SENSOR_MEM_TEMP,
 138         AMDGPU_PP_SENSOR_VCE_POWER,
 139         AMDGPU_PP_SENSOR_UVD_POWER,
 140         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 141         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 142         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 143         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 144         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 145         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 146         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 147         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 148         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 149         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 150         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 151         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 152 };
 153
 154 enum amd_pp_task {
 155         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 156         AMD_PP_TASK_ENABLE_USER_STATE,
 157         AMD_PP_TASK_READJUST_POWER_STATE,
 158         AMD_PP_TASK_COMPLETE_INIT,
 159         AMD_PP_TASK_MAX
 160 };
 161
 162 enum PP_SMC_POWER_PROFILE {
 163         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 164         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 165         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 166         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 167         PP_SMC_POWER_PROFILE_VR           = 0x4,
 168         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 169         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 170         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 171         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 172         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 173         PP_SMC_POWER_PROFILE_COUNT,
 174 };
 175
 176 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 177
 178
 179
 180 enum {
 181         PP_GROUP_UNKNOWN = 0,
 182         PP_GROUP_GFX = 1,
 183         PP_GROUP_SYS,
 184         PP_GROUP_MAX
 185 };
 186
 187 enum PP_OD_DPM_TABLE_COMMAND {
 188         PP_OD_EDIT_SCLK_VDDC_TABLE,
 189         PP_OD_EDIT_MCLK_VDDC_TABLE,
 190         PP_OD_EDIT_CCLK_VDDC_TABLE,
 191         PP_OD_EDIT_VDDC_CURVE,
 192         PP_OD_RESTORE_DEFAULT_TABLE,
 193         PP_OD_COMMIT_DPM_TABLE,
 194         PP_OD_EDIT_VDDGFX_OFFSET,
 195         PP_OD_EDIT_FAN_CURVE,
 196         PP_OD_EDIT_ACOUSTIC_LIMIT,
 197         PP_OD_EDIT_ACOUSTIC_TARGET,
 198         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 199         PP_OD_EDIT_FAN_MINIMUM_PWM,
 200 };
 201
 202 struct pp_states_info {
 203         uint32_t nums;
 204         uint32_t states[16];
 205 };
 206
 207 enum PP_HWMON_TEMP {
 208         PP_TEMP_EDGE = 0,
 209         PP_TEMP_JUNCTION,
 210         PP_TEMP_MEM,
 211         PP_TEMP_MAX
 212 };
 213
 214 enum pp_mp1_state {
 215         PP_MP1_STATE_NONE,
 216         PP_MP1_STATE_SHUTDOWN,
 217         PP_MP1_STATE_UNLOAD,
 218         PP_MP1_STATE_RESET,
 219 };
 220
 221 enum pp_df_cstate {
 222         DF_CSTATE_DISALLOW = 0,
 223         DF_CSTATE_ALLOW,
 224 };
 225
 226 /**
 227  * DOC: amdgpu_pp_power
 228  *
 229  * APU power is managed to system-level requirements through the PPT
 230  * (package power tracking) feature. PPT is intended to limit power to the
 231  * requirements of the power source and could be dynamically updated to
 232  * maximize APU performance within the system power budget.
 233  *
 234  * Two types of power measurement can be requested, where supported, with
 235  * :c:type:`enum pp_power_type <pp_power_type>`.
 236  */
 237
 238 /**
 239  * enum pp_power_limit_level - Used to query the power limits
 240  *
 241  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 242  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 243  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 244  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 245  */
 246 enum pp_power_limit_level
 247 {
 248         PP_PWR_LIMIT_MIN = -1,
 249         PP_PWR_LIMIT_CURRENT,
 250         PP_PWR_LIMIT_DEFAULT,
 251         PP_PWR_LIMIT_MAX,
 252 };
 253
 254 /**
 255  * enum pp_power_type - Used to specify the type of the requested power
 256  *
 257  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 258  * moving average of APU power (default ~5000 ms).
 259  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 260  * where supported.
 261  */
 262 enum pp_power_type
 263 {
 264         PP_PWR_TYPE_SUSTAINED,
 265         PP_PWR_TYPE_FAST,
 266 };
 267
 268 #define PP_GROUP_MASK        0xF0000000
 269 #define PP_GROUP_SHIFT       28
 270
 271 #define PP_BLOCK_MASK        0x0FFFFF00
 272 #define PP_BLOCK_SHIFT       8
 273
 274 #define PP_BLOCK_GFX_CG         0x01
 275 #define PP_BLOCK_GFX_MG         0x02
 276 #define PP_BLOCK_GFX_3D         0x04
 277 #define PP_BLOCK_GFX_RLC        0x08
 278 #define PP_BLOCK_GFX_CP         0x10
 279 #define PP_BLOCK_SYS_BIF        0x01
 280 #define PP_BLOCK_SYS_MC         0x02
 281 #define PP_BLOCK_SYS_ROM        0x04
 282 #define PP_BLOCK_SYS_DRM        0x08
 283 #define PP_BLOCK_SYS_HDP        0x10
 284 #define PP_BLOCK_SYS_SDMA       0x20
 285
 286 #define PP_STATE_MASK           0x0000000F
 287 #define PP_STATE_SHIFT          0
 288 #define PP_STATE_SUPPORT_MASK   0x000000F0
 289 #define PP_STATE_SUPPORT_SHIFT  0
 290
 291 #define PP_STATE_CG             0x01
 292 #define PP_STATE_LS             0x02
 293 #define PP_STATE_DS             0x04
 294 #define PP_STATE_SD             0x08
 295 #define PP_STATE_SUPPORT_CG     0x10
 296 #define PP_STATE_SUPPORT_LS     0x20
 297 #define PP_STATE_SUPPORT_DS     0x40
 298 #define PP_STATE_SUPPORT_SD     0x80
 299
 300 #define PP_CG_MSG_ID(group, block, support, state) \
 301                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 302                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 303
 304 #define XGMI_MODE_PSTATE_D3 0
 305 #define XGMI_MODE_PSTATE_D0 1
 306
 307 #define NUM_HBM_INSTANCES 4
 308
 309 struct seq_file;
 310 enum amd_pp_clock_type;
 311 struct amd_pp_simple_clock_info;
 312 struct amd_pp_display_configuration;
 313 struct amd_pp_clock_info;
 314 struct pp_display_clock_request;
 315 struct pp_clock_levels_with_voltage;
 316 struct pp_clock_levels_with_latency;
 317 struct amd_pp_clocks;
 318 struct pp_smu_wm_range_sets;
 319 struct pp_smu_nv_clock_table;
 320 struct dpm_clocks;
 321
 322 struct amd_pm_funcs {
 323 /* export for dpm on ci and si */
 324         int (*pre_set_power_state)(void *handle);
 325         int (*set_power_state)(void *handle);
 326         void (*post_set_power_state)(void *handle);
 327         void (*display_configuration_changed)(void *handle);
 328         void (*print_power_state)(void *handle, void *ps);
 329         bool (*vblank_too_short)(void *handle);
 330         void (*enable_bapm)(void *handle, bool enable);
 331         int (*check_state_equal)(void *handle,
 332                                 void  *cps,
 333                                 void  *rps,
 334                                 bool  *equal);
 335 /* export for sysfs */
 336         int (*set_fan_control_mode)(void *handle, u32 mode);
 337         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 338         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 339         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 340         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 341         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 342         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 343         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 344         int (*get_sclk_od)(void *handle);
 345         int (*set_sclk_od)(void *handle, uint32_t value);
 346         int (*get_mclk_od)(void *handle);
 347         int (*set_mclk_od)(void *handle, uint32_t value);
 348         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 349         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 350         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 351         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 352         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 353         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 354         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 355         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 356         int (*get_pp_table)(void *handle, char **table);
 357         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 358         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 359         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 360 /* export to amdgpu */
 361         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 362         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 363                         enum amd_pm_state_type *user_state);
 364         int (*load_firmware)(void *handle);
 365         int (*wait_for_fw_loading_complete)(void *handle);
 366         int (*set_powergating_by_smu)(void *handle,
 367                                 uint32_t block_type, bool gate);
 368         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 369         int (*set_power_limit)(void *handle, uint32_t n);
 370         int (*get_power_limit)(void *handle, uint32_t *limit,
 371                         enum pp_power_limit_level pp_limit_level,
 372                         enum pp_power_type power_type);
 373         int (*get_power_profile_mode)(void *handle, char *buf);
 374         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 375         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 376         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 377                                   long *input, uint32_t size);
 378         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 379         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 380         int (*gfx_state_change_set)(void *handle, uint32_t state);
 381 /* export to DC */
 382         u32 (*get_sclk)(void *handle, bool low);
 383         u32 (*get_mclk)(void *handle, bool low);
 384         int (*display_configuration_change)(void *handle,
 385                 const struct amd_pp_display_configuration *input);
 386         int (*get_display_power_level)(void *handle,
 387                 struct amd_pp_simple_clock_info *output);
 388         int (*get_current_clocks)(void *handle,
 389                 struct amd_pp_clock_info *clocks);
 390         int (*get_clock_by_type)(void *handle,
 391                 enum amd_pp_clock_type type,
 392                 struct amd_pp_clocks *clocks);
 393         int (*get_clock_by_type_with_latency)(void *handle,
 394                 enum amd_pp_clock_type type,
 395                 struct pp_clock_levels_with_latency *clocks);
 396         int (*get_clock_by_type_with_voltage)(void *handle,
 397                 enum amd_pp_clock_type type,
 398                 struct pp_clock_levels_with_voltage *clocks);
 399         int (*set_watermarks_for_clocks_ranges)(void *handle,
 400                                                 void *clock_ranges);
 401         int (*display_clock_voltage_request)(void *handle,
 402                                 struct pp_display_clock_request *clock);
 403         int (*get_display_mode_validation_clocks)(void *handle,
 404                 struct amd_pp_simple_clock_info *clocks);
 405         int (*notify_smu_enable_pwe)(void *handle);
 406         int (*enable_mgpu_fan_boost)(void *handle);
 407         int (*set_active_display_count)(void *handle, uint32_t count);
 408         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 409         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 410         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 411         int (*get_asic_baco_capability)(void *handle, bool *cap);
 412         int (*get_asic_baco_state)(void *handle, int *state);
 413         int (*set_asic_baco_state)(void *handle, int state);
 414         int (*get_ppfeature_status)(void *handle, char *buf);
 415         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 416         int (*asic_reset_mode_2)(void *handle);
 417         int (*asic_reset_enable_gfx_features)(void *handle);
 418         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 419         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 420         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 421         int (*set_watermarks_for_clock_ranges)(void *handle,
 422                                                struct pp_smu_wm_range_sets *ranges);
 423         int (*display_disable_memory_clock_switch)(void *handle,
 424                                                    bool disable_memory_clock_switch);
 425         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 426                                                 struct pp_smu_nv_clock_table *max_clocks);
 427         int (*get_uclk_dpm_states)(void *handle,
 428                                    unsigned int *clock_values_in_khz,
 429                                    unsigned int *num_states);
 430         int (*get_dpm_clock_table)(void *handle,
 431                                    struct dpm_clocks *clock_table);
 432         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 433         void (*pm_compute_clocks)(void *handle);
 434 };
 435
 436 struct metrics_table_header {
 437         uint16_t                        structure_size;
 438         uint8_t                         format_revision;
 439         uint8_t                         content_revision;
 440 };
 441
 442 /*
 443  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 444  * Use gpu_metrics_v1_1 or later instead.
 445  */
 446 struct gpu_metrics_v1_0 {
 447         struct metrics_table_header     common_header;
 448
 449         /* Driver attached timestamp (in ns) */
 450         uint64_t                        system_clock_counter;
 451
 452         /* Temperature */
 453         uint16_t                        temperature_edge;
 454         uint16_t                        temperature_hotspot;
 455         uint16_t                        temperature_mem;
 456         uint16_t                        temperature_vrgfx;
 457         uint16_t                        temperature_vrsoc;
 458         uint16_t                        temperature_vrmem;
 459
 460         /* Utilization */
 461         uint16_t                        average_gfx_activity;
 462         uint16_t                        average_umc_activity; // memory controller
 463         uint16_t                        average_mm_activity; // UVD or VCN
 464
 465         /* Power/Energy */
 466         uint16_t                        average_socket_power;
 467         uint32_t                        energy_accumulator;
 468
 469         /* Average clocks */
 470         uint16_t                        average_gfxclk_frequency;
 471         uint16_t                        average_socclk_frequency;
 472         uint16_t                        average_uclk_frequency;
 473         uint16_t                        average_vclk0_frequency;
 474         uint16_t                        average_dclk0_frequency;
 475         uint16_t                        average_vclk1_frequency;
 476         uint16_t                        average_dclk1_frequency;
 477
 478         /* Current clocks */
 479         uint16_t                        current_gfxclk;
 480         uint16_t                        current_socclk;
 481         uint16_t                        current_uclk;
 482         uint16_t                        current_vclk0;
 483         uint16_t                        current_dclk0;
 484         uint16_t                        current_vclk1;
 485         uint16_t                        current_dclk1;
 486
 487         /* Throttle status */
 488         uint32_t                        throttle_status;
 489
 490         /* Fans */
 491         uint16_t                        current_fan_speed;
 492
 493         /* Link width/speed */
 494         uint8_t                         pcie_link_width;
 495         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 496 };
 497
 498 struct gpu_metrics_v1_1 {
 499         struct metrics_table_header     common_header;
 500
 501         /* Temperature */
 502         uint16_t                        temperature_edge;
 503         uint16_t                        temperature_hotspot;
 504         uint16_t                        temperature_mem;
 505         uint16_t                        temperature_vrgfx;
 506         uint16_t                        temperature_vrsoc;
 507         uint16_t                        temperature_vrmem;
 508
 509         /* Utilization */
 510         uint16_t                        average_gfx_activity;
 511         uint16_t                        average_umc_activity; // memory controller
 512         uint16_t                        average_mm_activity; // UVD or VCN
 513
 514         /* Power/Energy */
 515         uint16_t                        average_socket_power;
 516         uint64_t                        energy_accumulator;
 517
 518         /* Driver attached timestamp (in ns) */
 519         uint64_t                        system_clock_counter;
 520
 521         /* Average clocks */
 522         uint16_t                        average_gfxclk_frequency;
 523         uint16_t                        average_socclk_frequency;
 524         uint16_t                        average_uclk_frequency;
 525         uint16_t                        average_vclk0_frequency;
 526         uint16_t                        average_dclk0_frequency;
 527         uint16_t                        average_vclk1_frequency;
 528         uint16_t                        average_dclk1_frequency;
 529
 530         /* Current clocks */
 531         uint16_t                        current_gfxclk;
 532         uint16_t                        current_socclk;
 533         uint16_t                        current_uclk;
 534         uint16_t                        current_vclk0;
 535         uint16_t                        current_dclk0;
 536         uint16_t                        current_vclk1;
 537         uint16_t                        current_dclk1;
 538
 539         /* Throttle status */
 540         uint32_t                        throttle_status;
 541
 542         /* Fans */
 543         uint16_t                        current_fan_speed;
 544
 545         /* Link width/speed */
 546         uint16_t                        pcie_link_width;
 547         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 548
 549         uint16_t                        padding;
 550
 551         uint32_t                        gfx_activity_acc;
 552         uint32_t                        mem_activity_acc;
 553
 554         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 555 };
 556
 557 struct gpu_metrics_v1_2 {
 558         struct metrics_table_header     common_header;
 559
 560         /* Temperature */
 561         uint16_t                        temperature_edge;
 562         uint16_t                        temperature_hotspot;
 563         uint16_t                        temperature_mem;
 564         uint16_t                        temperature_vrgfx;
 565         uint16_t                        temperature_vrsoc;
 566         uint16_t                        temperature_vrmem;
 567
 568         /* Utilization */
 569         uint16_t                        average_gfx_activity;
 570         uint16_t                        average_umc_activity; // memory controller
 571         uint16_t                        average_mm_activity; // UVD or VCN
 572
 573         /* Power/Energy */
 574         uint16_t                        average_socket_power;
 575         uint64_t                        energy_accumulator;
 576
 577         /* Driver attached timestamp (in ns) */
 578         uint64_t                        system_clock_counter;
 579
 580         /* Average clocks */
 581         uint16_t                        average_gfxclk_frequency;
 582         uint16_t                        average_socclk_frequency;
 583         uint16_t                        average_uclk_frequency;
 584         uint16_t                        average_vclk0_frequency;
 585         uint16_t                        average_dclk0_frequency;
 586         uint16_t                        average_vclk1_frequency;
 587         uint16_t                        average_dclk1_frequency;
 588
 589         /* Current clocks */
 590         uint16_t                        current_gfxclk;
 591         uint16_t                        current_socclk;
 592         uint16_t                        current_uclk;
 593         uint16_t                        current_vclk0;
 594         uint16_t                        current_dclk0;
 595         uint16_t                        current_vclk1;
 596         uint16_t                        current_dclk1;
 597
 598         /* Throttle status (ASIC dependent) */
 599         uint32_t                        throttle_status;
 600
 601         /* Fans */
 602         uint16_t                        current_fan_speed;
 603
 604         /* Link width/speed */
 605         uint16_t                        pcie_link_width;
 606         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 607
 608         uint16_t                        padding;
 609
 610         uint32_t                        gfx_activity_acc;
 611         uint32_t                        mem_activity_acc;
 612
 613         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 614
 615         /* PMFW attached timestamp (10ns resolution) */
 616         uint64_t                        firmware_timestamp;
 617 };
 618
 619 struct gpu_metrics_v1_3 {
 620         struct metrics_table_header     common_header;
 621
 622         /* Temperature */
 623         uint16_t                        temperature_edge;
 624         uint16_t                        temperature_hotspot;
 625         uint16_t                        temperature_mem;
 626         uint16_t                        temperature_vrgfx;
 627         uint16_t                        temperature_vrsoc;
 628         uint16_t                        temperature_vrmem;
 629
 630         /* Utilization */
 631         uint16_t                        average_gfx_activity;
 632         uint16_t                        average_umc_activity; // memory controller
 633         uint16_t                        average_mm_activity; // UVD or VCN
 634
 635         /* Power/Energy */
 636         uint16_t                        average_socket_power;
 637         uint64_t                        energy_accumulator;
 638
 639         /* Driver attached timestamp (in ns) */
 640         uint64_t                        system_clock_counter;
 641
 642         /* Average clocks */
 643         uint16_t                        average_gfxclk_frequency;
 644         uint16_t                        average_socclk_frequency;
 645         uint16_t                        average_uclk_frequency;
 646         uint16_t                        average_vclk0_frequency;
 647         uint16_t                        average_dclk0_frequency;
 648         uint16_t                        average_vclk1_frequency;
 649         uint16_t                        average_dclk1_frequency;
 650
 651         /* Current clocks */
 652         uint16_t                        current_gfxclk;
 653         uint16_t                        current_socclk;
 654         uint16_t                        current_uclk;
 655         uint16_t                        current_vclk0;
 656         uint16_t                        current_dclk0;
 657         uint16_t                        current_vclk1;
 658         uint16_t                        current_dclk1;
 659
 660         /* Throttle status */
 661         uint32_t                        throttle_status;
 662
 663         /* Fans */
 664         uint16_t                        current_fan_speed;
 665
 666         /* Link width/speed */
 667         uint16_t                        pcie_link_width;
 668         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 669
 670         uint16_t                        padding;
 671
 672         uint32_t                        gfx_activity_acc;
 673         uint32_t                        mem_activity_acc;
 674
 675         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 676
 677         /* PMFW attached timestamp (10ns resolution) */
 678         uint64_t                        firmware_timestamp;
 679
 680         /* Voltage (mV) */
 681         uint16_t                        voltage_soc;
 682         uint16_t                        voltage_gfx;
 683         uint16_t                        voltage_mem;
 684
 685         uint16_t                        padding1;
 686
 687         /* Throttle status (ASIC independent) */
 688         uint64_t                        indep_throttle_status;
 689 };
 690
 691 /*
 692  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 693  * Use gpu_metrics_v2_1 or later instead.
 694  */
 695 struct gpu_metrics_v2_0 {
 696         struct metrics_table_header     common_header;
 697
 698         /* Driver attached timestamp (in ns) */
 699         uint64_t                        system_clock_counter;
 700
 701         /* Temperature */
 702         uint16_t                        temperature_gfx; // gfx temperature on APUs
 703         uint16_t                        temperature_soc; // soc temperature on APUs
 704         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 705         uint16_t                        temperature_l3[2];
 706
 707         /* Utilization */
 708         uint16_t                        average_gfx_activity;
 709         uint16_t                        average_mm_activity; // UVD or VCN
 710
 711         /* Power/Energy */
 712         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 713         uint16_t                        average_cpu_power;
 714         uint16_t                        average_soc_power;
 715         uint16_t                        average_gfx_power;
 716         uint16_t                        average_core_power[8]; // CPU core power on APUs
 717
 718         /* Average clocks */
 719         uint16_t                        average_gfxclk_frequency;
 720         uint16_t                        average_socclk_frequency;
 721         uint16_t                        average_uclk_frequency;
 722         uint16_t                        average_fclk_frequency;
 723         uint16_t                        average_vclk_frequency;
 724         uint16_t                        average_dclk_frequency;
 725
 726         /* Current clocks */
 727         uint16_t                        current_gfxclk;
 728         uint16_t                        current_socclk;
 729         uint16_t                        current_uclk;
 730         uint16_t                        current_fclk;
 731         uint16_t                        current_vclk;
 732         uint16_t                        current_dclk;
 733         uint16_t                        current_coreclk[8]; // CPU core clocks
 734         uint16_t                        current_l3clk[2];
 735
 736         /* Throttle status */
 737         uint32_t                        throttle_status;
 738
 739         /* Fans */
 740         uint16_t                        fan_pwm;
 741
 742         uint16_t                        padding;
 743 };
 744
 745 struct gpu_metrics_v2_1 {
 746         struct metrics_table_header     common_header;
 747
 748         /* Temperature */
 749         uint16_t                        temperature_gfx; // gfx temperature on APUs
 750         uint16_t                        temperature_soc; // soc temperature on APUs
 751         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 752         uint16_t                        temperature_l3[2];
 753
 754         /* Utilization */
 755         uint16_t                        average_gfx_activity;
 756         uint16_t                        average_mm_activity; // UVD or VCN
 757
 758         /* Driver attached timestamp (in ns) */
 759         uint64_t                        system_clock_counter;
 760
 761         /* Power/Energy */
 762         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 763         uint16_t                        average_cpu_power;
 764         uint16_t                        average_soc_power;
 765         uint16_t                        average_gfx_power;
 766         uint16_t                        average_core_power[8]; // CPU core power on APUs
 767
 768         /* Average clocks */
 769         uint16_t                        average_gfxclk_frequency;
 770         uint16_t                        average_socclk_frequency;
 771         uint16_t                        average_uclk_frequency;
 772         uint16_t                        average_fclk_frequency;
 773         uint16_t                        average_vclk_frequency;
 774         uint16_t                        average_dclk_frequency;
 775
 776         /* Current clocks */
 777         uint16_t                        current_gfxclk;
 778         uint16_t                        current_socclk;
 779         uint16_t                        current_uclk;
 780         uint16_t                        current_fclk;
 781         uint16_t                        current_vclk;
 782         uint16_t                        current_dclk;
 783         uint16_t                        current_coreclk[8]; // CPU core clocks
 784         uint16_t                        current_l3clk[2];
 785
 786         /* Throttle status */
 787         uint32_t                        throttle_status;
 788
 789         /* Fans */
 790         uint16_t                        fan_pwm;
 791
 792         uint16_t                        padding[3];
 793 };
 794
 795 struct gpu_metrics_v2_2 {
 796         struct metrics_table_header     common_header;
 797
 798         /* Temperature */
 799         uint16_t                        temperature_gfx; // gfx temperature on APUs
 800         uint16_t                        temperature_soc; // soc temperature on APUs
 801         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 802         uint16_t                        temperature_l3[2];
 803
 804         /* Utilization */
 805         uint16_t                        average_gfx_activity;
 806         uint16_t                        average_mm_activity; // UVD or VCN
 807
 808         /* Driver attached timestamp (in ns) */
 809         uint64_t                        system_clock_counter;
 810
 811         /* Power/Energy */
 812         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 813         uint16_t                        average_cpu_power;
 814         uint16_t                        average_soc_power;
 815         uint16_t                        average_gfx_power;
 816         uint16_t                        average_core_power[8]; // CPU core power on APUs
 817
 818         /* Average clocks */
 819         uint16_t                        average_gfxclk_frequency;
 820         uint16_t                        average_socclk_frequency;
 821         uint16_t                        average_uclk_frequency;
 822         uint16_t                        average_fclk_frequency;
 823         uint16_t                        average_vclk_frequency;
 824         uint16_t                        average_dclk_frequency;
 825
 826         /* Current clocks */
 827         uint16_t                        current_gfxclk;
 828         uint16_t                        current_socclk;
 829         uint16_t                        current_uclk;
 830         uint16_t                        current_fclk;
 831         uint16_t                        current_vclk;
 832         uint16_t                        current_dclk;
 833         uint16_t                        current_coreclk[8]; // CPU core clocks
 834         uint16_t                        current_l3clk[2];
 835
 836         /* Throttle status (ASIC dependent) */
 837         uint32_t                        throttle_status;
 838
 839         /* Fans */
 840         uint16_t                        fan_pwm;
 841
 842         uint16_t                        padding[3];
 843
 844         /* Throttle status (ASIC independent) */
 845         uint64_t                        indep_throttle_status;
 846 };
 847
 848 struct gpu_metrics_v2_3 {
 849         struct metrics_table_header     common_header;
 850
 851         /* Temperature */
 852         uint16_t                        temperature_gfx; // gfx temperature on APUs
 853         uint16_t                        temperature_soc; // soc temperature on APUs
 854         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 855         uint16_t                        temperature_l3[2];
 856
 857         /* Utilization */
 858         uint16_t                        average_gfx_activity;
 859         uint16_t                        average_mm_activity; // UVD or VCN
 860
 861         /* Driver attached timestamp (in ns) */
 862         uint64_t                        system_clock_counter;
 863
 864         /* Power/Energy */
 865         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
 866         uint16_t                        average_cpu_power;
 867         uint16_t                        average_soc_power;
 868         uint16_t                        average_gfx_power;
 869         uint16_t                        average_core_power[8]; // CPU core power on APUs
 870
 871         /* Average clocks */
 872         uint16_t                        average_gfxclk_frequency;
 873         uint16_t                        average_socclk_frequency;
 874         uint16_t                        average_uclk_frequency;
 875         uint16_t                        average_fclk_frequency;
 876         uint16_t                        average_vclk_frequency;
 877         uint16_t                        average_dclk_frequency;
 878
 879         /* Current clocks */
 880         uint16_t                        current_gfxclk;
 881         uint16_t                        current_socclk;
 882         uint16_t                        current_uclk;
 883         uint16_t                        current_fclk;
 884         uint16_t                        current_vclk;
 885         uint16_t                        current_dclk;
 886         uint16_t                        current_coreclk[8]; // CPU core clocks
 887         uint16_t                        current_l3clk[2];
 888
 889         /* Throttle status (ASIC dependent) */
 890         uint32_t                        throttle_status;
 891
 892         /* Fans */
 893         uint16_t                        fan_pwm;
 894
 895         uint16_t                        padding[3];
 896
 897         /* Throttle status (ASIC independent) */
 898         uint64_t                        indep_throttle_status;
 899
 900         /* Average Temperature */
 901         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
 902         uint16_t                        average_temperature_soc; // average soc temperature on APUs
 903         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
 904         uint16_t                        average_temperature_l3[2];
 905 };
 906
 907 struct gpu_metrics_v2_4 {
 908         struct metrics_table_header     common_header;
 909
 910         /* Temperature (unit: centi-Celsius) */
 911         uint16_t                        temperature_gfx;
 912         uint16_t                        temperature_soc;
 913         uint16_t                        temperature_core[8];
 914         uint16_t                        temperature_l3[2];
 915
 916         /* Utilization (unit: centi) */
 917         uint16_t                        average_gfx_activity;
 918         uint16_t                        average_mm_activity;
 919
 920         /* Driver attached timestamp (in ns) */
 921         uint64_t                        system_clock_counter;
 922
 923         /* Power/Energy (unit: mW) */
 924         uint16_t                        average_socket_power;
 925         uint16_t                        average_cpu_power;
 926         uint16_t                        average_soc_power;
 927         uint16_t                        average_gfx_power;
 928         uint16_t                        average_core_power[8];
 929
 930         /* Average clocks (unit: MHz) */
 931         uint16_t                        average_gfxclk_frequency;
 932         uint16_t                        average_socclk_frequency;
 933         uint16_t                        average_uclk_frequency;
 934         uint16_t                        average_fclk_frequency;
 935         uint16_t                        average_vclk_frequency;
 936         uint16_t                        average_dclk_frequency;
 937
 938         /* Current clocks (unit: MHz) */
 939         uint16_t                        current_gfxclk;
 940         uint16_t                        current_socclk;
 941         uint16_t                        current_uclk;
 942         uint16_t                        current_fclk;
 943         uint16_t                        current_vclk;
 944         uint16_t                        current_dclk;
 945         uint16_t                        current_coreclk[8];
 946         uint16_t                        current_l3clk[2];
 947
 948         /* Throttle status (ASIC dependent) */
 949         uint32_t                        throttle_status;
 950
 951         /* Fans */
 952         uint16_t                        fan_pwm;
 953
 954         uint16_t                        padding[3];
 955
 956         /* Throttle status (ASIC independent) */
 957         uint64_t                        indep_throttle_status;
 958
 959         /* Average Temperature (unit: centi-Celsius) */
 960         uint16_t                        average_temperature_gfx;
 961         uint16_t                        average_temperature_soc;
 962         uint16_t                        average_temperature_core[8];
 963         uint16_t                        average_temperature_l3[2];
 964
 965         /* Power/Voltage (unit: mV) */
 966         uint16_t                        average_cpu_voltage;
 967         uint16_t                        average_soc_voltage;
 968         uint16_t                        average_gfx_voltage;
 969
 970         /* Power/Current (unit: mA) */
 971         uint16_t                        average_cpu_current;
 972         uint16_t                        average_soc_current;
 973         uint16_t                        average_gfx_current;
 974 };
 975 #endif