drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "nbio_v7_11.h"
  26
  27 #include "nbio/nbio_7_11_0_offset.h"
  28 #include "nbio/nbio_7_11_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 static u32 nbio_v7_11_get_rev_id(struct amdgpu_device *adev)
  32 {
  33         u32 tmp;
  34
  35         tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0);
  36         tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
  37         tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
  38
  39         return tmp;
  40 }
  41
  42 static void nbio_v7_11_mc_access_enable(struct amdgpu_device *adev, bool enable)
  43 {
  44         if (enable)
  45                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN,
  46                         BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK |
  47                         BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK);
  48         else
  49                 WREG32_SOC15(NBIO, 0, regBIF_BX1_BIF_FB_EN, 0);
  50 }
  51
  52 static u32 nbio_v7_11_get_memsize(struct amdgpu_device *adev)
  53 {
  54         return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_CONFIG_MEMSIZE);
  55 }
  56
  57 static void nbio_v7_11_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
  58                                           bool use_doorbell, int doorbell_index,
  59                                           int doorbell_size)
  60 {
  61         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_SDMA0_DOORBELL_RANGE);
  62         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  63
  64         if (use_doorbell) {
  65                 doorbell_range = REG_SET_FIELD(doorbell_range,
  66                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  67                                                OFFSET, doorbell_index);
  68                 doorbell_range = REG_SET_FIELD(doorbell_range,
  69                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  70                                                SIZE, doorbell_size);
  71         } else {
  72                 doorbell_range = REG_SET_FIELD(doorbell_range,
  73                                                GDC0_BIF_SDMA0_DOORBELL_RANGE,
  74                                                SIZE, 0);
  75         }
  76
  77         WREG32_PCIE_PORT(reg, doorbell_range);
  78 }
  79
  80 static void nbio_v7_11_vpe_doorbell_range(struct amdgpu_device *adev, int instance,
  81                                           bool use_doorbell, int doorbell_index,
  82                                           int doorbell_size)
  83 {
  84         u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VPE_DOORBELL_RANGE);
  85         u32 doorbell_range = RREG32_PCIE_PORT(reg);
  86
  87         if (use_doorbell) {
  88                 doorbell_range = REG_SET_FIELD(doorbell_range,
  89                                                GDC0_BIF_VPE_DOORBELL_RANGE,
  90                                                OFFSET, doorbell_index);
  91                 doorbell_range = REG_SET_FIELD(doorbell_range,
  92                                                GDC0_BIF_VPE_DOORBELL_RANGE,
  93                                                SIZE, doorbell_size);
  94         } else {
  95                 doorbell_range = REG_SET_FIELD(doorbell_range,
  96                                                GDC0_BIF_VPE_DOORBELL_RANGE,
  97                                                SIZE, 0);
  98         }
  99
 100         WREG32_PCIE_PORT(reg, doorbell_range);
 101 }
 102
 103 static void nbio_v7_11_enable_doorbell_aperture(struct amdgpu_device *adev,
 104                                                bool enable)
 105 {
 106         u32 reg;
 107
 108
 109         reg = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN);
 110         reg = REG_SET_FIELD(reg, RCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN,
 111                             BIF_DOORBELL_APER_EN, enable ? 1 : 0);
 112
 113         WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_0_RCC_DOORBELL_APER_EN, reg);
 114 }
 115
 116 static void nbio_v7_11_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
 117                                                         bool enable)
 118 {
 119 /*      u32 tmp = 0;
 120
 121         if (enable) {
 122                 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 123                                 DOORBELL_SELFRING_GPA_APER_EN, 1) |
 124                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 125                                 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
 126                         REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 127                                 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
 128
 129                 WREG32_SOC15(NBIO, 0,
 130                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
 131                         lower_32_bits(adev->doorbell.base));
 132                 WREG32_SOC15(NBIO, 0,
 133                         regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
 134                         upper_32_bits(adev->doorbell.base));
 135         }
 136
 137         WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
 138                 tmp);
 139 */
 140 }
 141
 142
 143 static void nbio_v7_11_ih_doorbell_range(struct amdgpu_device *adev,
 144                                         bool use_doorbell, int doorbell_index)
 145 {
 146         u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0,regGDC0_BIF_IH_DOORBELL_RANGE);
 147
 148         if (use_doorbell) {
 149                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 150                                                   GDC0_BIF_IH_DOORBELL_RANGE, OFFSET,
 151                                                   doorbell_index);
 152                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 153                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 154                                                   2);
 155         } else {
 156                 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
 157                                                   GDC0_BIF_IH_DOORBELL_RANGE, SIZE,
 158                                                   0);
 159         }
 160
 161         WREG32_SOC15(NBIO, 0, regGDC0_BIF_IH_DOORBELL_RANGE,
 162                          ih_doorbell_range);
 163 }
 164
 165 static void nbio_v7_11_ih_control(struct amdgpu_device *adev)
 166 {
 167         u32 interrupt_cntl;
 168
 169         /* setup interrupt control */
 170         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL2,
 171                      adev->dummy_page_addr >> 8);
 172
 173         interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL);
 174         /*
 175          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
 176          * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
 177          */
 178         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 179                                        IH_DUMMY_RD_OVERRIDE, 0);
 180
 181         /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
 182         interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX1_INTERRUPT_CNTL,
 183                                        IH_REQ_NONSNOOP_EN, 0);
 184
 185         WREG32_SOC15(NBIO, 0, regBIF_BX1_INTERRUPT_CNTL, interrupt_cntl);
 186 }
 187
 188 static u32 nbio_v7_11_get_hdp_flush_req_offset(struct amdgpu_device *adev)
 189 {
 190         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
 191 }
 192
 193 static u32 nbio_v7_11_get_hdp_flush_done_offset(struct amdgpu_device *adev)
 194 {
 195         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
 196 }
 197
 198 static u32 nbio_v7_11_get_pcie_index_offset(struct amdgpu_device *adev)
 199 {
 200         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_INDEX2);
 201 }
 202
 203 static u32 nbio_v7_11_get_pcie_data_offset(struct amdgpu_device *adev)
 204 {
 205         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX1_PCIE_DATA2);
 206 }
 207
 208 static u32 nbio_v7_11_get_pcie_port_index_offset(struct amdgpu_device *adev)
 209 {
 210         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX);
 211 }
 212
 213 static u32 nbio_v7_11_get_pcie_port_data_offset(struct amdgpu_device *adev)
 214 {
 215         return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA);
 216 }
 217
 218 const struct nbio_hdp_flush_reg nbio_v7_11_hdp_flush_reg = {
 219         .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
 220         .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
 221         .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
 222         .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
 223         .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
 224         .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
 225         .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
 226         .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
 227         .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
 228         .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
 229         .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
 230         .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
 231 };
 232
 233 static void nbio_v7_11_init_registers(struct amdgpu_device *adev)
 234 {
 235 /*      uint32_t def, data;
 236
 237                 def = data = RREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3);
 238                 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
 239                         CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
 240                 data = REG_SET_FIELD(data, BIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3,
 241                         CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
 242
 243                 if (def != data)
 244                         WREG32_SOC15(NBIO, 0, regBIF_BIF256_CI256_RC3X4_USB4_PCIE_MST_CTRL_3, data);
 245 */
 246 }
 247
 248 const struct amdgpu_nbio_funcs nbio_v7_11_funcs = {
 249         .get_hdp_flush_req_offset = nbio_v7_11_get_hdp_flush_req_offset,
 250         .get_hdp_flush_done_offset = nbio_v7_11_get_hdp_flush_done_offset,
 251         .get_pcie_index_offset = nbio_v7_11_get_pcie_index_offset,
 252         .get_pcie_data_offset = nbio_v7_11_get_pcie_data_offset,
 253         .get_pcie_port_index_offset = nbio_v7_11_get_pcie_port_index_offset,
 254         .get_pcie_port_data_offset = nbio_v7_11_get_pcie_port_data_offset,
 255         .get_rev_id = nbio_v7_11_get_rev_id,
 256         .mc_access_enable = nbio_v7_11_mc_access_enable,
 257         .get_memsize = nbio_v7_11_get_memsize,
 258         .sdma_doorbell_range = nbio_v7_11_sdma_doorbell_range,
 259         .vpe_doorbell_range = nbio_v7_11_vpe_doorbell_range,
 260         .enable_doorbell_aperture = nbio_v7_11_enable_doorbell_aperture,
 261         .enable_doorbell_selfring_aperture = nbio_v7_11_enable_doorbell_selfring_aperture,
 262         .ih_doorbell_range = nbio_v7_11_ih_doorbell_range,
 263         .ih_control = nbio_v7_11_ih_control,
 264         .init_registers = nbio_v7_11_init_registers,
 265 };